FPGA-Neural

T

micheleandClaude Sonnet 5 32d32f4c0e docs: capture exploratory 4x4 hybrid systolic scaling direction (not built)

Brainstorming session outcome: instead of flat N=16 independent DDR3
requesters, group cores into 4 weight-stationary systolic chains of 4
PEs each - reduces independent DDR3 contenders from 16 to 4 while
preserving task-level parallelism across the 4 groups. Captured as
docs/ARCHITECTURE_ANALYSIS.md S5.6, explicitly marked exploratory/not
decided/not built - revisit after the 32-bit channel widening and real
N=2/4/8 flat-core scaling tests produce real numbers.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-20 13:18:46 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: capture exploratory 4x4 hybrid systolic scaling direction (not built)

2026-09-20 13:18:46 +02:00

hardware

feat: DDRManager phase 1 - single-slot look-ahead activation prefetch (EXP-0083)

2026-09-20 10:59:45 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze