micheleandClaude Sonnet 5
20b0b1f4c0
mac_unit.v: exhaustive unit test (all 65536 (x,w) combinations at DATA_WIDTH=8, plus 486 boundary acc_in vectors) against an independent Python oracle (tools/validation/mac_oracle.py). 66022/66022 match, 0 reserves. mac8.v: first-ever dedicated unit test (previously only indirect coverage at whatever single PARALLEL neuron_parallel_tb.v happens to use). Verified at PARALLEL=2/8/32 with structural adversarial vectors (catches swapped/duplicated tree wiring), 300 random INT8 pairs per PARALLEL with realistic accumulating acc_in, and worst-case magnitude adversarial vectors. 939/939 match. Confirms BUG-002 (N_INPUTS=0 bypasses the N_INPUTS%PARALLEL elaboration guard) is real, on both simulation and real Yosys synthesis -- root cause: [DATA_WIDTH*N_INPUTS-1:0] becomes [-1:0] for N_INPUTS=0, which both tools treat as a genuine 2-bit undriven vector rather than collapsing to zero width. Includes a documented self-correction: the first verification attempt produced a false "hang" using an invalid one-shot late check of a single-cycle done pulse -- caught by reproducing the same false result on a known-good sanity config before trusting it. Full regression re-run clean after adding 3 new testbenches: 36/36 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
105 lines
3.9 KiB
Verilog
105 lines
3.9 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// MAC_UNIT TESTBENCH (certification campaign, aspect C.1)
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//
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// rtl/mac_unit.v had NO dedicated unit-level testbench before this
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// (docs/validation/00-inventario.md §0.4/§0.5): only indirect coverage
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// through neuron_parallel_tb.v and friends, where acc_in is always
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// hardwired to 0 by mac8.v and a bug isolated to this module would only
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// surface if it happened to propagate visibly through the full layer.
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//
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// Oracle: tools/validation/mac_oracle.py, an independent Python
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// reimplementation (two's complement from first principles, not a
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// transcription of this RTL) -- see that file's own header. Vectors are
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// pre-generated (tools/validation/mac_unit_vectors_*.hex) rather than
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// computed at Verilog runtime, so the comparison at each step is purely
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// mechanical (no chance of Verilog-side arithmetic accidentally
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// re-deriving the same bug the oracle exists to catch).
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//
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// Coverage: EXHAUSTIVE on (x,w) at DATA_WIDTH=8 -- all 256*256=65536
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// combinations, acc_in=0 (matches mac8.v's real usage). Plus a second,
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// separate file exercising the module's own full port contract
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// (acc_out = acc_in + product for ANY acc_in, not just the acc_in=0 case
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// this design happens to use today) across boundary/random acc_in values
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// including the four true product-magnitude corners
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// (-128*-128, 127*127, -128*127, 127*-128).
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// ================================================================
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module tb;
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localparam DATA_WIDTH = 8;
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localparam ACC_WIDTH = 32;
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reg signed [DATA_WIDTH-1:0] x;
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reg signed [DATA_WIDTH-1:0] w;
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reg signed [ACC_WIDTH-1:0] acc_in;
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wire signed [ACC_WIDTH-1:0] acc_out;
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mac_unit #(.DATA_WIDTH(DATA_WIDTH), .ACC_WIDTH(ACC_WIDTH)) dut (
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.x(x), .w(w), .acc_in(acc_in), .acc_out(acc_out)
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);
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// 80-bit packed vector: x[79:72] w[71:64] acc_in[63:32] expected[31:0]
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reg [79:0] exhaustive_vec [0:65535];
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reg [79:0] boundary_vec [0:485];
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integer i;
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integer errors;
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integer checked;
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reg [7:0] vx;
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reg [7:0] vw;
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reg [31:0] vacc_in;
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reg [31:0] vexpected;
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task automatic check_one(input [79:0] packed_vec);
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begin
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vx = packed_vec[79:72];
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vw = packed_vec[71:64];
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vacc_in = packed_vec[63:32];
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vexpected = packed_vec[31:0];
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x = vx;
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w = vw;
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acc_in = vacc_in;
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#1;
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checked = checked + 1;
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if (acc_out !== $signed(vexpected)) begin
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errors = errors + 1;
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if (errors <= 20) begin
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$display("MISMATCH: x=%0d w=%0d acc_in=%0d -> got=%0d expected=%0d",
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$signed(vx), $signed(vw), $signed(vacc_in), acc_out, $signed(vexpected));
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end
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end
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end
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endtask
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initial begin
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errors = 0;
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checked = 0;
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$readmemh("tools/validation/mac_unit_vectors_exhaustive.hex", exhaustive_vec);
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$readmemh("tools/validation/mac_unit_vectors_boundary_accin.hex", boundary_vec);
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$display("--- TEST 1: exhaustive (x,w), acc_in=0 -- 65536 combinations ---");
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for (i = 0; i < 65536; i = i + 1) begin
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check_one(exhaustive_vec[i]);
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end
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$display(" checked %0d, errors so far %0d", checked, errors);
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$display("--- TEST 2: full port contract, boundary/random acc_in -- 486 vectors ---");
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for (i = 0; i < 486; i = i + 1) begin
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check_one(boundary_vec[i]);
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end
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$display(" checked %0d total, errors %0d", checked, errors);
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if (errors == 0) begin
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$display("ALL TESTS PASSED (%0d vectors, 0 mismatches against independent Python oracle)", checked);
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end else begin
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$display("FAILED: %0d/%0d vectors mismatched", errors, checked);
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end
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$finish;
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end
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endmodule
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