micheleandClaude Sonnet 5
3026dcd997
Implements M2 of the V2 roadmap: neural_processor_array.v instantiates
N_PROCESSORS independent neural_processor (M1) units, each with its
own dedicated point-to-point job/operand/result interface -- no shared
bus or mux at this level (arbitration is explicitly the Neural
Director's job, M5).
Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4):
7/7 tests pass, including a same-cycle 4-way concurrent launch with
different tile counts and a staggered-start test where a
later-launched, shorter job completes before an earlier-launched,
longer one -- confirming genuine independent concurrent execution
(§18/§34: a blocked/busy processor must not block the others).
Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys +
nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target
throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales
linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while
LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard
ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured
via a dedicated synthesis-only timing harness after the array's wide
per-processor buses were found to exhaust the device's TRELLIS_IO pin
budget as a bare top-level module beyond N=1 (errors.log ERR-0005) --
not a logic limit, an artifact of testing the array in isolation
before the Memory Manager/Director (M4/M5) exist to consume those
ports on-chip.
Full log trail (development/experiments/errors/decisions/simulation/
synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's
logging mandate.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
31 lines
1.7 KiB
Plaintext
31 lines
1.7 KiB
Plaintext
# V2 simulation log -- solo append, mai troncato/sovrascritto (vedi README.md)
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# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
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[2026-09-05] EXP-0001/EXP-0002 -- hardware/v2/sim/tb_neural_processor.v
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test: 7 cases (16/32/8/8/8/8/64-input jobs; ACT_NONE + ACT_RELU;
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extreme INT8 saturation; back-to-back zero-idle-gap tiles)
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vectors: regular positive, mixed-sign cancellation, extreme INT8
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(-128,-127,-1,0,1,126,127,127 in one 8-lane tile), back-to-back
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jobs, 8-tile (64-input) job
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simulator: Verilator 5.050 (--binary --timing) -- see decisions.log
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DEC-0004 for why Icarus v13.0 is not trusted for this testbench
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cycles: not separately profiled at this milestone (throughput/stall
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cycle counting deferred to M9 per §22)
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PASS/FAIL: 7/7 PASS (ACC_WIDTH=32); 7/7 PASS (ACC_WIDTH=24, EXP-0002)
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bit-exact result: V1.y === V2.result_data for every case, both widths
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stall cycles / memory wait / utilization: N/A (no Memory Manager yet,
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M1 operands fed directly by testbench per the roadmap)
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[2026-09-05] EXP-0003 -- hardware/v2/sim/tb_neural_processor_array.v
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(N_PROCESSORS=4)
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test: 7 cases (single-processor sanity; 4-way same-cycle concurrent
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launch with different tile counts; staggered-start 2-processor test)
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 7/7 PASS
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bit-exact result: N/A at this milestone (hand-computed expected
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values, arithmetic itself already bit-exact-certified vs V1 at M1)
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concurrency: confirmed genuine -- in the staggered test, the
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later-launched, shorter job (processor 1) completes BEFORE the
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earlier-launched, longer job (processor 0), proving independent
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progress rather than serialization.
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