FPGA-Neural

T

micheleandClaude Sonnet 5 2ab2ff7769 docs: N=8 re-verified with MAC pipeline fix (improves margin), N=16 margin-hunt result (EXP-0097 cont.)

N=8 with the same pipelined neural_processor_packed.v: 16/16 functional
PASS, real P&R WNS=+0.108ns (up from the original exact-zero 0.000ns),
0 failing endpoints, no regression -- the fix is a pure improvement for
N=8 too.

N=16 margin-hunt: worst path moved again (now inside
neural_director_grouped.v's own queue update logic, still route-
dominated) -- confirms the MAC fix resolved its own real bottleneck.
A second real P&R attempt with alternate directives gave WNS=+0.168ns,
worse than the first attempt's +0.269ns -- confirms real P&R variance,
not further systematic gain available without touching Director RTL
(not attempted, current margin already comfortable).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-22 00:44:54 +02:00

benchmark_results

feat: add FPGA-Neural benchmark tooling + same-tier ECP5 P2/P4/P8 results

2026-09-02 19:48:03 +02:00

docs

docs: add preliminary datasheet for FPGA-Neural N8 (semiconductor-style)

2026-09-21 08:57:15 +02:00

hardware

docs: N=8 re-verified with MAC pipeline fix (improves margin), N=16 margin-hunt result (EXP-0097 cont.)

2026-09-22 00:44:54 +02:00

sim

chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze