micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
7290 lines
738 KiB
Plaintext
7290 lines
738 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Executing script file `synth/ecp5/irq_pins/synth.ys' --
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1. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v' to AST representation.
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Generating RTLIL representation for module `\spi_slave'.
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v' to AST representation.
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Generating RTLIL representation for module `\spi_engine'.
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Successfully finished Verilog frontend.
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3. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v' to AST representation.
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Generating RTLIL representation for module `\layer_sequencer'.
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Successfully finished Verilog frontend.
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4. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v' to AST representation.
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Generating RTLIL representation for module `\act_buffer'.
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Successfully finished Verilog frontend.
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5. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v' to AST representation.
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Generating RTLIL representation for module `\graph_engine'.
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Successfully finished Verilog frontend.
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6. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v' to AST representation.
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Generating RTLIL representation for module `\mem_arbiter'.
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Successfully finished Verilog frontend.
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7. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v' to AST representation.
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Generating RTLIL representation for module `\neuron_memory'.
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Successfully finished Verilog frontend.
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8. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v' to AST representation.
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Generating RTLIL representation for module `\int8_memory_access'.
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Successfully finished Verilog frontend.
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9. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v' to AST representation.
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Generating RTLIL representation for module `\memory_interface'.
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Successfully finished Verilog frontend.
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10. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v' to AST representation.
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/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:93: Warning: Yosys has only limited support for tri-state logic at the moment.
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Generating RTLIL representation for module `\psram_controller'.
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Successfully finished Verilog frontend.
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11. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v' to AST representation.
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Generating RTLIL representation for module `\neuron_parallel'.
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Successfully finished Verilog frontend.
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12. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v' to AST representation.
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Generating RTLIL representation for module `\mac8'.
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Successfully finished Verilog frontend.
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13. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v' to AST representation.
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Generating RTLIL representation for module `\mac_unit'.
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Successfully finished Verilog frontend.
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14. Executing Verilog-2005 frontend: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v
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Parsing SystemVerilog input from `/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v' to AST representation.
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Generating RTLIL representation for module `\spi_neuron_top'.
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Successfully finished Verilog frontend.
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Parameter \PARALLEL = 2
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15. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_neuron_top'.
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Parameter \PARALLEL = 2
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Generating RTLIL representation for module `$paramod\spi_neuron_top\PARALLEL=s32'00000000000000000000000000000010'.
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16. Executing HIERARCHY pass (managing design hierarchy).
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16.1. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
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Used module: \spi_engine
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Used module: \layer_sequencer
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Used module: \graph_engine
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Used module: \neuron_parallel
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Used module: \mac8
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Used module: \mac_unit
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Used module: \act_buffer
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Used module: \neuron_memory
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Used module: \int8_memory_access
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Used module: \mem_arbiter
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Used module: \memory_interface
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Used module: \psram_controller
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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16.2. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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16.3. Executing AST frontend in derive mode using pre-parsed AST for module `\act_buffer'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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Generating RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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16.4. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 8
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
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Parameter \ADDR_WIDTH = 23
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16.5. Executing AST frontend in derive mode using pre-parsed AST for module `\int8_memory_access'.
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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16.6. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Generating RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Parameter \DATA_WIDTH = 16
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Parameter \ACC_WIDTH = 40
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Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
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Reprocessing module mac8 because instantiated module mac_unit has become available.
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Generating RTLIL representation for module `\mac8'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \N_TOTAL = 4096
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16.7. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \N_TOTAL = 4096
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Generating RTLIL representation for module `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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16.8. Executing AST frontend in derive mode using pre-parsed AST for module `\layer_sequencer'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_WIDTH = 1
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Parameter \N_LAYERS = 4
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Generating RTLIL representation for module `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 2
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Parameter \MAX_CONN = 32
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Parameter \N_TOTAL = 4096
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16.9. Executing AST frontend in derive mode using pre-parsed AST for module `\graph_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Parameter \PARALLEL = 2
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Parameter \MAX_CONN = 32
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Parameter \N_TOTAL = 4096
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Generating RTLIL representation for module `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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16.10. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_memory'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \N_NEURONS = 1
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory'.
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Parameter \ADDR_WIDTH = 23
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16.11. Executing AST frontend in derive mode using pre-parsed AST for module `\mem_arbiter'.
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Parameter \ADDR_WIDTH = 23
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Generating RTLIL representation for module `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \ADDR_WIDTH = 23
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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16.12. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_interface'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Generating RTLIL representation for module `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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16.13. Executing AST frontend in derive mode using pre-parsed AST for module `\psram_controller'.
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Parameter \ADDR_WIDTH = 23
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Parameter \DATA_WIDTH = 16
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Parameter \CLK_FREQ_MHZ = 80
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Generating RTLIL representation for module `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller'.
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16.14. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
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Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
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Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
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Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
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Used module: \neuron_parallel
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Used module: $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8
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Used module: \mac_unit
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Used module: \act_buffer
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Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
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Used module: \int8_memory_access
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Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
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Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
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Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
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Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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16.15. Executing AST frontend in derive mode using pre-parsed AST for module `\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Parameter \DATA_WIDTH = 8
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
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Reprocessing module $paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8 because instantiated module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit has become available.
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Generating RTLIL representation for module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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16.16. Executing AST frontend in derive mode using pre-parsed AST for module `\neuron_parallel'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Generating RTLIL representation for module `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel'.
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Parameter \N_TOTAL = 4096
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Parameter \DATA_WIDTH = 8
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Found cached RTLIL representation for module `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer'.
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Parameter \DATA_WIDTH = 8
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Parameter \N_INPUTS = 32
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Parameter \PARALLEL = 2
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Parameter \ACC_WIDTH = 32
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Found cached RTLIL representation for module `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel'.
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Parameter \ADDR_WIDTH = 23
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Found cached RTLIL representation for module `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111'.
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16.17. Analyzing design hierarchy..
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Top module: \spi_neuron_top
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Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: \mac8
|
|
Used module: \mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 16
|
|
Parameter \ACC_WIDTH = 40
|
|
Found cached RTLIL representation for module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Parameter \PARALLEL = 2
|
|
|
|
16.18. Executing AST frontend in derive mode using pre-parsed AST for module `\mac8'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Parameter \PARALLEL = 2
|
|
Generating RTLIL representation for module `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8'.
|
|
|
|
16.19. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: \mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
Parameter \DATA_WIDTH = 8
|
|
Parameter \ACC_WIDTH = 32
|
|
Found cached RTLIL representation for module `$paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit'.
|
|
|
|
16.20. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
|
|
16.21. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Removing unused module `$paramod$24a3a7236073cb7c12a30999f26614228c51a089\mac8'.
|
|
Removing unused module `\mac8'.
|
|
Removing unused module `$paramod$18f95495176adabb8b1efa1a4c23d17992af7212\neuron_parallel'.
|
|
Removing unused module `\mac_unit'.
|
|
Removing unused module `$paramod$913793164bb5cb5821e69ced9b7f953b27ebd911\mac_unit'.
|
|
Removing unused module `\neuron_parallel'.
|
|
Removing unused module `\psram_controller'.
|
|
Removing unused module `\memory_interface'.
|
|
Removing unused module `\int8_memory_access'.
|
|
Removing unused module `\neuron_memory'.
|
|
Removing unused module `\mem_arbiter'.
|
|
Removing unused module `\graph_engine'.
|
|
Removing unused module `\act_buffer'.
|
|
Removing unused module `\layer_sequencer'.
|
|
Removing unused module `\spi_engine'.
|
|
Removed 15 unused modules.
|
|
|
|
17. Executing SYNTH_LATTICE pass.
|
|
|
|
17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\LUT4'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT5'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT6'.
|
|
Generating RTLIL representation for module `\$__ABC9_LUT7'.
|
|
Generating RTLIL representation for module `\L6MUX21'.
|
|
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
|
|
Generating RTLIL representation for module `\PFUMX'.
|
|
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
|
|
Generating RTLIL representation for module `\DPR16X4C'.
|
|
Generating RTLIL representation for module `\LUT2'.
|
|
Generating RTLIL representation for module `\TRELLIS_FF'.
|
|
Generating RTLIL representation for module `\TRELLIS_IO'.
|
|
Generating RTLIL representation for module `\INV'.
|
|
Generating RTLIL representation for module `\TRELLIS_COMB'.
|
|
Generating RTLIL representation for module `\VLO'.
|
|
Generating RTLIL representation for module `\VHI'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\CCU2C'.
|
|
Generating RTLIL representation for module `\DP16KD'.
|
|
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
|
|
Generating RTLIL representation for module `\GSR'.
|
|
Generating RTLIL representation for module `\PUR'.
|
|
Generating RTLIL representation for module `\SGSR'.
|
|
Generating RTLIL representation for module `\PDPW16KD'.
|
|
Generating RTLIL representation for module `\MULT18X18D'.
|
|
Generating RTLIL representation for module `\ALU54B'.
|
|
Generating RTLIL representation for module `\CLKDIVF'.
|
|
Generating RTLIL representation for module `\PCSCLKDIV'.
|
|
Generating RTLIL representation for module `\DCSC'.
|
|
Generating RTLIL representation for module `\DCCA'.
|
|
Generating RTLIL representation for module `\ECLKSYNCB'.
|
|
Generating RTLIL representation for module `\ECLKBRIDGECS'.
|
|
Generating RTLIL representation for module `\DELAYF'.
|
|
Generating RTLIL representation for module `\DELAYG'.
|
|
Generating RTLIL representation for module `\USRMCLK'.
|
|
Generating RTLIL representation for module `\DQSBUFM'.
|
|
Generating RTLIL representation for module `\DDRDLLA'.
|
|
Generating RTLIL representation for module `\DLLDELD'.
|
|
Generating RTLIL representation for module `\IDDRX1F'.
|
|
Generating RTLIL representation for module `\IDDRX2F'.
|
|
Generating RTLIL representation for module `\IDDR71B'.
|
|
Generating RTLIL representation for module `\IDDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX1F'.
|
|
Generating RTLIL representation for module `\ODDRX2F'.
|
|
Generating RTLIL representation for module `\ODDR71B'.
|
|
Generating RTLIL representation for module `\OSHX2A'.
|
|
Generating RTLIL representation for module `\TSHX2DQA'.
|
|
Generating RTLIL representation for module `\TSHX2DQSA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQA'.
|
|
Generating RTLIL representation for module `\ODDRX2DQSB'.
|
|
Generating RTLIL representation for module `\EHXPLLL'.
|
|
Generating RTLIL representation for module `\DTR'.
|
|
Generating RTLIL representation for module `\OSCG'.
|
|
Generating RTLIL representation for module `\EXTREFB'.
|
|
Generating RTLIL representation for module `\JTAGG'.
|
|
Generating RTLIL representation for module `\DCUA'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.3. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
17.3.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
|
|
17.3.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Used module: \spi_slave
|
|
Used module: $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine
|
|
Used module: $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer
|
|
Used module: $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine
|
|
Used module: $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel
|
|
Used module: $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8
|
|
Used module: $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit
|
|
Used module: $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer
|
|
Used module: $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory
|
|
Used module: $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111
|
|
Used module: $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface
|
|
Used module: $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller
|
|
Removed 0 unused modules.
|
|
|
|
17.4. Executing PROC pass (convert processes to netlists).
|
|
|
|
17.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Cleaned up 0 empty switches.
|
|
|
|
17.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 2 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257 in module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
Removed 1 dead cases from process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256 in module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 8 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136 in module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
Marked 11 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887 in module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798 in module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
Marked 13 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:281$773 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 3 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:260$771 in module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260 in module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
Marked 4 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694 in module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662 in module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Marked 5 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353 in module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
Marked 6 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2 in module spi_slave.
|
|
Marked 1 switch rules as full_case in process $proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1 in module spi_slave.
|
|
Removed a total of 1 dead cases.
|
|
|
|
17.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 40 redundant assignments.
|
|
Promoted 92 assignments to connections.
|
|
|
|
17.4.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
17.4.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
17.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 1 switch.
|
|
<suppressed ~118 debug messages>
|
|
|
|
17.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
1/9: $0\mem_req[0:0]
|
|
2/9: $0\ready[0:0]
|
|
3/9: $0\mem_ub_n[0:0]
|
|
4/9: $0\mem_lb_n[0:0]
|
|
5/9: $0\rdata[15:0]
|
|
6/9: $0\mem_wdata[15:0]
|
|
7/9: $0\mem_addr[22:0]
|
|
8/9: $0\mem_wr[0:0]
|
|
9/9: $0\state[1:0]
|
|
Creating decoders for process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
1/11: $0\c_ready[0:0]
|
|
2/11: $0\b_ready[0:0]
|
|
3/11: $0\a_ready[0:0]
|
|
4/11: $0\m_req[0:0]
|
|
5/11: $0\owner[1:0]
|
|
6/11: $0\m_wdata[7:0]
|
|
7/11: $0\m_addr[22:0]
|
|
8/11: $0\m_wr[0:0]
|
|
9/11: $0\c_rdata[7:0]
|
|
10/11: $0\b_rdata[7:0]
|
|
11/11: $0\a_rdata[7:0]
|
|
Creating decoders for process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
1/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1184
|
|
2/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_DATA[7:0]$1183
|
|
3/42: $3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_ADDR[0:0]$1182
|
|
4/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1176
|
|
5/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_DATA[7:0]$1175
|
|
6/42: $3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1174
|
|
7/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1168
|
|
8/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_DATA[7:0]$1167
|
|
9/42: $3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR[5:0]$1166
|
|
10/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1165
|
|
11/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_DATA[7:0]$1164
|
|
12/42: $2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_ADDR[0:0]$1163
|
|
13/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1162
|
|
14/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_DATA[7:0]$1161
|
|
15/42: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1160
|
|
16/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1159
|
|
17/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_DATA[7:0]$1158
|
|
18/42: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR[5:0]$1157
|
|
19/42: $0\done[0:0]
|
|
20/42: $1\rst_i[31:0]
|
|
21/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1147
|
|
22/42: $0\neuron_start[0:0]
|
|
23/42: $0\access_req[0:0]
|
|
24/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1156
|
|
25/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_DATA[7:0]$1155
|
|
26/42: $1$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_ADDR[0:0]$1154
|
|
27/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1153
|
|
28/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_DATA[7:0]$1152
|
|
29/42: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1151
|
|
30/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1150
|
|
31/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_DATA[7:0]$1149
|
|
32/42: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR[5:0]$1148
|
|
33/42: $0\access_wdata[7:0]
|
|
34/42: $0\access_addr[22:0]
|
|
35/42: $0\access_wr[0:0]
|
|
36/42: $0\bias_group_addr[22:0]
|
|
37/42: $0\w_group_base[22:0]
|
|
38/42: $0\neuron_index[0:0]
|
|
39/42: $0\index[5:0]
|
|
40/42: $0\bias_reg[7:0]
|
|
41/42: $0\busy[0:0]
|
|
42/42: $0\state[3:0]
|
|
Creating decoders for process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
1/108: $0\src_id_acc[15:0] [15:8]
|
|
2/108: $0\src_id_acc[15:0] [7:0]
|
|
3/108: $0\out_id_acc[15:0] [7:0]
|
|
4/108: $0\n_conn_acc[15:0] [7:0]
|
|
5/108: $0\conn_ptr_acc[23:0] [7:0]
|
|
6/108: $0\conn_ptr_acc[23:0] [23:16]
|
|
7/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_DATA[7:0]$1032
|
|
8/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_ADDR[5:0]$1031
|
|
9/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$1030
|
|
10/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_DATA[7:0]$1029
|
|
11/108: $2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_ADDR[5:0]$1028
|
|
12/108: $1\ri[31:0]
|
|
13/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$1021
|
|
14/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$1020
|
|
15/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$1019
|
|
16/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$1018
|
|
17/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$1017
|
|
18/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$1016
|
|
19/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$1015
|
|
20/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$1014
|
|
21/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$1013
|
|
22/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$1012
|
|
23/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$1011
|
|
24/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$1010
|
|
25/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$1009
|
|
26/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$1008
|
|
27/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$1007
|
|
28/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$1006
|
|
29/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$1005
|
|
30/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$1004
|
|
31/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$1003
|
|
32/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$1002
|
|
33/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$1001
|
|
34/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$1000
|
|
35/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$999
|
|
36/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$998
|
|
37/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$997
|
|
38/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$996
|
|
39/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$995
|
|
40/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$994
|
|
41/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$993
|
|
42/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$992
|
|
43/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$991
|
|
44/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$990
|
|
45/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$989
|
|
46/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$988
|
|
47/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$987
|
|
48/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$986
|
|
49/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$985
|
|
50/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$984
|
|
51/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$983
|
|
52/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$982
|
|
53/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$981
|
|
54/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$980
|
|
55/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$979
|
|
56/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$978
|
|
57/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$977
|
|
58/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$976
|
|
59/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$975
|
|
60/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$974
|
|
61/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$973
|
|
62/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$972
|
|
63/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$971
|
|
64/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$970
|
|
65/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$969
|
|
66/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$968
|
|
67/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$967
|
|
68/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$966
|
|
69/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$965
|
|
70/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$964
|
|
71/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$963
|
|
72/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$962
|
|
73/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$961
|
|
74/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$960
|
|
75/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$959
|
|
76/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$958
|
|
77/108: $0\ram_req[0:0]
|
|
78/108: $0\neuron_start[0:0]
|
|
79/108: $0\act_wr_en[0:0]
|
|
80/108: $0\done[0:0]
|
|
81/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$1027
|
|
82/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_DATA[7:0]$1026
|
|
83/108: $1$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_ADDR[5:0]$1025
|
|
84/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$1024
|
|
85/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_DATA[7:0]$1023
|
|
86/108: $1$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_ADDR[5:0]$1022
|
|
87/108: $0\n_conn_padded_reg[15:0]
|
|
88/108: $0\activation_reg[1:0]
|
|
89/108: $0\bias_reg[7:0]
|
|
90/108: $0\act_wr_data[7:0]
|
|
91/108: $0\act_wr_addr[11:0]
|
|
92/108: $0\weight_acc[7:0]
|
|
93/108: $0\out_id_acc[15:0] [15:8]
|
|
94/108: $0\edge_byte_idx[1:0]
|
|
95/108: $0\conn_i[5:0]
|
|
96/108: $0\n_conn_acc[15:0] [15:8]
|
|
97/108: $0\conn_ptr_acc[23:0] [15:8]
|
|
98/108: $2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$1033
|
|
99/108: $0\desc_addr[22:0]
|
|
100/108: $0\neuron_idx[15:0]
|
|
101/108: $0\in_idx[15:0]
|
|
102/108: $0\err[0:0]
|
|
103/108: $0\busy[0:0]
|
|
104/108: $0\desc_byte_idx[3:0]
|
|
105/108: $0\state[3:0]
|
|
106/108: $0\ram_wdata[7:0]
|
|
107/108: $0\ram_addr[22:0]
|
|
108/108: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
1/32: $0\n_neurons_acc[15:0] [15:8]
|
|
2/32: $0\n_neurons_acc[15:0] [7:0]
|
|
3/32: $0\n_inputs_acc[15:0] [7:0]
|
|
4/32: $0\bias_addr_acc[23:0] [7:0]
|
|
5/32: $0\bias_addr_acc[23:0] [23:16]
|
|
6/32: $0\w_base_acc[23:0] [7:0]
|
|
7/32: $0\w_base_acc[23:0] [23:16]
|
|
8/32: $0\ram_req[0:0]
|
|
9/32: $0\nm_start[0:0]
|
|
10/32: $0\copy_idx[0:0]
|
|
11/32: $0\write_sel[0:0]
|
|
12/32: $0\cur_sel[0:0]
|
|
13/32: $0\n_inputs_acc[15:0] [15:8]
|
|
14/32: $0\bias_addr_acc[23:0] [15:8]
|
|
15/32: $0\activation_acc[7:0]
|
|
16/32: $0\w_base_acc[23:0] [15:8]
|
|
17/32: $0\seq_done[0:0]
|
|
18/32: $0\desc_byte_idx[3:0]
|
|
19/32: $0\desc_table_addr[22:0]
|
|
20/32: $0\num_layers_reg[7:0]
|
|
21/32: $0\layer_idx[7:0]
|
|
22/32: $0\nm_n_neurons[15:0]
|
|
23/32: $0\nm_n_inputs[15:0]
|
|
24/32: $0\nm_activation[1:0]
|
|
25/32: $0\nm_bias_addr[22:0]
|
|
26/32: $0\nm_w_base[22:0]
|
|
27/32: $0\nm_x_base[22:0]
|
|
28/32: $0\state[3:0]
|
|
29/32: $0\seq_busy[0:0]
|
|
30/32: $0\ram_wdata[7:0]
|
|
31/32: $0\ram_addr[22:0]
|
|
32/32: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
1/36: $0\len_acc[15:0] [15:8]
|
|
2/36: $0\len_acc[15:0] [7:0]
|
|
3/36: $0\nm_soft_rst[0:0]
|
|
4/36: $0\nm_start[0:0]
|
|
5/36: $0\ram_req[0:0]
|
|
6/36: $0\status_snapshot[7:0]
|
|
7/36: $0\graph_mode[0:0]
|
|
8/36: $0\net_mode[0:0]
|
|
9/36: $0\resp_len[3:0]
|
|
10/36: $0\resp_index[3:0]
|
|
11/36: $0\cur_read_byte[7:0]
|
|
12/36: $0\pending_wdata[7:0]
|
|
13/36: $0\pending_write[0:0]
|
|
14/36: $0\cur_addr[22:0]
|
|
15/36: $0\len_remaining[15:0]
|
|
16/36: $0\run_start[0:0]
|
|
17/36: $0\addr_acc[23:0]
|
|
18/36: $0\byte_pos[1:0]
|
|
19/36: $0\opcode[7:0]
|
|
20/36: $0\state[3:0]
|
|
21/36: $0\n_out[15:0]
|
|
22/36: $0\num_neurons_graph[15:0]
|
|
23/36: $0\net_type[7:0]
|
|
24/36: $0\run_num_layers[7:0]
|
|
25/36: $0\buf_b_base[22:0]
|
|
26/36: $0\buf_a_base[22:0]
|
|
27/36: $0\table_base[22:0]
|
|
28/36: $0\n_neurons_real[15:0]
|
|
29/36: $0\n_inputs_real[15:0]
|
|
30/36: $0\activation[1:0]
|
|
31/36: $0\bias_addr[22:0]
|
|
32/36: $0\w_base[22:0]
|
|
33/36: $0\x_base[22:0]
|
|
34/36: $0\ram_wdata[7:0]
|
|
35/36: $0\ram_addr[22:0]
|
|
36/36: $0\ram_wr[0:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:281$773'.
|
|
1/4: $4\tx_byte_comb[7:0]
|
|
2/4: $3\tx_byte_comb[7:0]
|
|
3/4: $2\tx_byte_comb[7:0]
|
|
4/4: $1\tx_byte_comb[7:0]
|
|
Creating decoders for process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:260$771'.
|
|
1/1: $0\status_done_sticky[0:0]
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1372'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1371'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1370'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1369'.
|
|
Creating decoders for process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1368'.
|
|
Creating decoders for process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
1/18: $0\dq_oe[0:0]
|
|
2/18: $0\psram_zz_n[0:0]
|
|
3/18: $0\psram_ub_n[0:0]
|
|
4/18: $0\psram_lb_n[0:0]
|
|
5/18: $0\psram_we_n[0:0]
|
|
6/18: $0\psram_oe_n[0:0]
|
|
7/18: $0\psram_ce_n[0:0]
|
|
8/18: $0\mem_ready[0:0]
|
|
9/18: $0\dq_out[15:0]
|
|
10/18: $0\ub_reg[0:0]
|
|
11/18: $0\lb_reg[0:0]
|
|
12/18: $0\wr_reg[0:0]
|
|
13/18: $0\wdata_reg[15:0]
|
|
14/18: $0\address_reg[22:0]
|
|
15/18: $0\counter[13:0]
|
|
16/18: $0\psram_a[22:0]
|
|
17/18: $0\mem_rdata[15:0]
|
|
18/18: $0\state[2:0]
|
|
Creating decoders for process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
1/10: $0\mem_req[0:0]
|
|
2/10: $0\ready[0:0]
|
|
3/10: $0\addr_reg[22:0]
|
|
4/10: $0\mem_ub_n[0:0]
|
|
5/10: $0\mem_lb_n[0:0]
|
|
6/10: $0\rdata[7:0]
|
|
7/10: $0\mem_wdata[15:0]
|
|
8/10: $0\mem_addr[22:0]
|
|
9/10: $0\mem_wr[0:0]
|
|
10/10: $0\state[1:0]
|
|
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$669'.
|
|
Creating decoders for process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
1/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$668
|
|
2/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_DATA[7:0]$667
|
|
3/3: $1$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_ADDR[11:0]$666
|
|
Creating decoders for process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
1/6: $0\done[0:0]
|
|
2/6: $0\finishing[0:0]
|
|
3/6: $0\acc[31:0]
|
|
4/6: $0\group_index[3:0]
|
|
5/6: $0\busy[0:0]
|
|
6/6: $0\y[7:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
1/9: $0\cs_end[0:0]
|
|
2/9: $0\cs_start[0:0]
|
|
3/9: $0\tx_byte_req[0:0]
|
|
4/9: $0\rx_valid[0:0]
|
|
5/9: $0\tx_shift[7:0]
|
|
6/9: $0\rx_shift[7:0]
|
|
7/9: $0\bit_count[2:0]
|
|
8/9: $0\rx_byte[7:0]
|
|
9/9: $0\miso[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
1/2: $0\cs_n_prev[0:0]
|
|
2/2: $0\sclk_prev[0:0]
|
|
Creating decoders for process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
1/3: $0\cs_n_sync[2:0]
|
|
2/3: $0\mosi_sync[2:0]
|
|
3/3: $0\sclk_sync[2:0]
|
|
|
|
17.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\tx_byte_comb' from process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:281$773'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[2]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1372'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1371'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\tree[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1370'.
|
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No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[1]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1369'.
|
|
No latch inferred for signal `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.\products[0]' from process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1368'.
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|
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17.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
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Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\state' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5312' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_req' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5313' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5314' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_addr' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5315' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_wdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5316' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\rdata' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5317' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\ready' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5318' with positive edge clock.
|
|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_lb_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5319' with positive edge clock.
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|
Creating register for signal `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.\mem_ub_n' using process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
created $dff cell `$procdff$5320' with positive edge clock.
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|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5321' with positive edge clock.
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|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\a_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5322' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5323' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\b_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5324' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_rdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5325' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\c_ready' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5326' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_req' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5327' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5328' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_addr' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5329' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\m_wdata' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5330' with positive edge clock.
|
|
Creating register for signal `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.\owner' using process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
created $dff cell `$procdff$5331' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\state' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5332' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\busy' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5333' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\done' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5334' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\neuron_start' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5335' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\bias_reg' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5336' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\index' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5337' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\neuron_index' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5338' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\w_group_base' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5339' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\bias_group_addr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5340' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_req' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5341' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_wr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5342' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_addr' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5343' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\access_wdata' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5344' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.\rst_i' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5345' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5346' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5347' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5348' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5349' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5350' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5351' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5352' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_ADDR' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5353' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_DATA' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5354' with positive edge clock.
|
|
Creating register for signal `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN' using process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
created $dff cell `$procdff$5355' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_req' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5356' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_wr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5357' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5358' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ram_wdata' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5359' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\state' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5360' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\desc_byte_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5361' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\busy' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5362' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\done' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5363' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\err' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5364' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\in_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5365' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\neuron_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5366' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\desc_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5367' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\conn_ptr_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5368' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\n_conn_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5369' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\out_id_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5370' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\conn_i' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5371' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\edge_byte_idx' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5372' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\src_id_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5373' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\weight_acc' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5374' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_en' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5375' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_addr' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5376' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\act_wr_data' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5377' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\neuron_start' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5378' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\bias_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5379' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\activation_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5380' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\n_conn_padded_reg' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5381' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.\ri' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5382' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5383' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5384' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5385' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5386' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5387' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5388' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5389' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5390' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5391' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5392' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5393' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5394' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5395' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5396' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5397' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5398' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5399' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5400' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5401' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5402' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5403' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5404' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5405' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5406' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5407' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5408' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5409' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5410' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5411' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5412' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5413' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5414' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5415' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5416' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5417' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5418' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5419' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5420' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5421' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5422' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5423' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5424' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5425' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5426' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5427' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5428' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5429' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5430' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5431' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5432' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5433' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5434' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5435' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5436' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5437' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5438' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5439' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5440' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5441' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5442' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5443' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5444' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5445' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5446' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_ADDR' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5447' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_DATA' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5448' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5449' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_ADDR' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5450' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_DATA' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5451' with positive edge clock.
|
|
Creating register for signal `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN' using process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
created $dff cell `$procdff$5452' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_req' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5453' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5454' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5455' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\ram_wdata' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5456' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_start' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5457' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_busy' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5458' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\seq_done' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
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created $dff cell `$procdff$5459' with positive edge clock.
|
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Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\state' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
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created $dff cell `$procdff$5460' with positive edge clock.
|
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Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_x_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
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created $dff cell `$procdff$5461' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_w_base' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5462' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_bias_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5463' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_activation' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5464' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_inputs' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5465' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\nm_n_neurons' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5466' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\layer_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5467' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\num_layers_reg' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5468' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_table_addr' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5469' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\desc_byte_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5470' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\w_base_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5471' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\bias_addr_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5472' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\activation_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5473' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_inputs_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5474' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\n_neurons_acc' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5475' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\cur_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5476' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\write_sel' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5477' with positive edge clock.
|
|
Creating register for signal `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.\copy_idx' using process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
created $dff cell `$procdff$5478' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_req' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5479' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_wr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5480' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5481' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\ram_wdata' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5482' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\x_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5483' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\w_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5484' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\bias_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5485' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\activation' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5486' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_inputs_real' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5487' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_neurons_real' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5488' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\nm_start' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5489' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\nm_soft_rst' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5490' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\table_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5491' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\buf_a_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5492' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\buf_b_base' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5493' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\run_start' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5494' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\run_num_layers' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5495' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\net_type' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5496' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\num_neurons_graph' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5497' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\n_out' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5498' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\state' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5499' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\opcode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5500' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\byte_pos' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5501' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\addr_acc' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5502' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\len_acc' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5503' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\len_remaining' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5504' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\cur_addr' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5505' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\pending_write' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5506' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\pending_wdata' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5507' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\cur_read_byte' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5508' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\resp_index' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5509' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\resp_len' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5510' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\net_mode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5511' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\graph_mode' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5512' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\status_snapshot' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
created $dff cell `$procdff$5513' with positive edge clock.
|
|
Creating register for signal `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.\status_done_sticky' using process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:260$771'.
|
|
created $dff cell `$procdff$5514' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\state' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5515' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_rdata' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5516' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\mem_ready' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5517' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_a' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5518' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ce_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5519' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_oe_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5520' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_we_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5521' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_lb_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5522' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_ub_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5523' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\psram_zz_n' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5524' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\counter' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5525' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\address_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5526' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wdata_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5527' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\wr_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5528' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\lb_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5529' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\ub_reg' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5530' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_out' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5531' with positive edge clock.
|
|
Creating register for signal `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.\dq_oe' using process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
created $dff cell `$procdff$5532' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\state' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5533' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_req' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5534' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5535' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_addr' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5536' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_wdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5537' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\rdata' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5538' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\ready' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5539' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_lb_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5540' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\mem_ub_n' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5541' with positive edge clock.
|
|
Creating register for signal `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.\addr_reg' using process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
created $dff cell `$procdff$5542' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.\rd_data' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$669'.
|
|
created $dff cell `$procdff$5543' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_ADDR' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
created $dff cell `$procdff$5544' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_DATA' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
created $dff cell `$procdff$5545' with positive edge clock.
|
|
Creating register for signal `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN' using process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
created $dff cell `$procdff$5546' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\y' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5547' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\busy' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5548' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\done' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5549' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\group_index' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5550' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\acc' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5551' with positive edge clock.
|
|
Creating register for signal `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.\finishing' using process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
created $dff cell `$procdff$5552' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\miso' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5553' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_byte' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5554' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_valid' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5555' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_byte_req' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5556' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_start' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5557' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_end' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5558' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\bit_count' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5559' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\rx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5560' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\tx_shift' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
created $dff cell `$procdff$5561' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$5562' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_prev' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
created $dff cell `$procdff$5563' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\sclk_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5564' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\mosi_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5565' with positive edge clock.
|
|
Creating register for signal `\spi_slave.\cs_n_sync' using process `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
created $dff cell `$procdff$5566' with positive edge clock.
|
|
|
|
17.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
17.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 5 empty switches in `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
Removing empty process `$paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/memory_interface.v:33$1257'.
|
|
Found and cleaned up 8 empty switches in `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
Removing empty process `$paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mem_arbiter.v:90$1256'.
|
|
Found and cleaned up 10 empty switches in `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
Removing empty process `$paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:283$1136'.
|
|
Found and cleaned up 19 empty switches in `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
Removing empty process `$paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:247$887'.
|
|
Found and cleaned up 10 empty switches in `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
Removing empty process `$paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:137$798'.
|
|
Found and cleaned up 29 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:333$778'.
|
|
Found and cleaned up 4 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:281$773'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:281$773'.
|
|
Found and cleaned up 4 empty switches in `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:260$771'.
|
|
Removing empty process `$paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:260$771'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:100$1372'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1371'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:81$1370'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1369'.
|
|
Removing empty process `$paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:40$1368'.
|
|
Found and cleaned up 7 empty switches in `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
Removing empty process `$paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:99$1260'.
|
|
Found and cleaned up 6 empty switches in `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
Removing empty process `$paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/int8_memory_access.v:55$694'.
|
|
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:60$669'.
|
|
Found and cleaned up 1 empty switch in `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
Removing empty process `$paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:55$662'.
|
|
Found and cleaned up 6 empty switches in `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
Removing empty process `$paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:194$1353'.
|
|
Found and cleaned up 8 empty switches in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:119$12'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:93$2'.
|
|
Found and cleaned up 1 empty switch in `\spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Removing empty process `spi_slave.$proc$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:71$1'.
|
|
Cleaned up 119 empty switches.
|
|
|
|
17.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
Optimizing module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
<suppressed ~8 debug messages>
|
|
Optimizing module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
<suppressed ~5 debug messages>
|
|
Optimizing module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
<suppressed ~9 debug messages>
|
|
Optimizing module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
<suppressed ~11 debug messages>
|
|
Optimizing module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
<suppressed ~9 debug messages>
|
|
Optimizing module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
<suppressed ~19 debug messages>
|
|
Optimizing module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.
|
|
Optimizing module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
<suppressed ~4 debug messages>
|
|
Optimizing module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
<suppressed ~15 debug messages>
|
|
Optimizing module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Optimizing module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Optimizing module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
<suppressed ~2 debug messages>
|
|
Optimizing module spi_slave.
|
|
<suppressed ~8 debug messages>
|
|
|
|
17.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Checking module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface...
|
|
Checking module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111...
|
|
Checking module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory...
|
|
Checking module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine...
|
|
Checking module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer...
|
|
Checking module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine...
|
|
Checking module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8...
|
|
Checking module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller...
|
|
Checking module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111...
|
|
Checking module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit...
|
|
Checking module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer...
|
|
Checking module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel...
|
|
Checking module spi_slave...
|
|
Found and reported 0 problems.
|
|
|
|
17.6. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$b3f3d2413f22d50ebc275a55cbfefa4ff7d277a1\memory_interface.
|
|
Deleting now unused module $paramod\mem_arbiter\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Deleting now unused module $paramod$80f5e68183ca7884165c68cdb28403ede9957037\neuron_memory.
|
|
Deleting now unused module $paramod$bb07367a7303d991d2ad86b852435fdcb495afab\graph_engine.
|
|
Deleting now unused module $paramod$347a1e2deb450f9b255363ccc18466ca222ac3a3\layer_sequencer.
|
|
Deleting now unused module $paramod$dd4f06a4ba98f945361f3a45f42984e592ac1bec\spi_engine.
|
|
Deleting now unused module $paramod$8f592f3125e8f7c96bc997ed58933554526412a5\mac8.
|
|
Deleting now unused module $paramod$9788b34e98bdf67d8ea3118da70785469fb65f06\psram_controller.
|
|
Deleting now unused module $paramod\int8_memory_access\ADDR_WIDTH=s32'00000000000000000000000000010111.
|
|
Deleting now unused module $paramod$8392c0aee371eac30cfcd917af9a6c37ac869d3e\mac_unit.
|
|
Deleting now unused module $paramod$c614a16d6b975c0ec2885ffa17a962bce4ddbcec\act_buffer.
|
|
Deleting now unused module $paramod$bcb9324e2b7cabc82145d6a09db8d736ca601b00\neuron_parallel.
|
|
Deleting now unused module spi_slave.
|
|
<suppressed ~16 debug messages>
|
|
|
|
17.7. Executing TRIBUF pass.
|
|
|
|
17.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
17.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~36 debug messages>
|
|
|
|
17.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 148 unused cells and 1612 unused wires.
|
|
<suppressed ~182 debug messages>
|
|
|
|
17.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 2018 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1695 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1687 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~993 debug messages>
|
|
Removed a total of 331 cells.
|
|
|
|
17.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5101: \u_graph_engine.u_neuron.finishing -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_graph_engine.\u_neuron.$procmux$5099: \u_graph_engine.u_neuron.finishing -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5101: \u_neuron_memory.u_neuron.finishing -> 1'0
|
|
Replacing known input bits on port A of cell $flatten\u_neuron_memory.\u_neuron.$procmux$5099: \u_neuron_memory.u_neuron.finishing -> 1'0
|
|
Analyzing evaluation results.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2402.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2412.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2422.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2432.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2442.
|
|
dead port 1/2 on $mux $flatten\u_graph_engine.$procmux$2921.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1824.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1827.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1833.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1836.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1842.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1845.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1854.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1857.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1866.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1869.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1878.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1881.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1891.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1894.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1904.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1907.
|
|
dead port 2/2 on $mux $flatten\u_neuron_memory.$procmux$1917.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1920.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1926.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1932.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1938.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1947.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1956.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1965.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1975.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1985.
|
|
dead port 1/2 on $mux $flatten\u_neuron_memory.$procmux$1995.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4697.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4699.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4707.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4709.
|
|
dead port 2/2 on $mux $flatten\u_spi_engine.$procmux$4717.
|
|
Removed 38 multiplexer ports.
|
|
<suppressed ~1384 debug messages>
|
|
|
|
17.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3308: $auto$opt_reduce.cc:137:opt_pmux$5655
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2419:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2419_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2419_Y [0]
|
|
New connections: $flatten\u_graph_engine.$procmux$2419_Y [7:1] = { $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] $flatten\u_graph_engine.$procmux$2419_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2448:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$881_EN[7:0]$951 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2451:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$880_EN[7:0]$950 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2454:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$879_EN[7:0]$949 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2457:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$878_EN[7:0]$948 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2460:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$877_EN[7:0]$947 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2463:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$876_EN[7:0]$946 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2466:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$875_EN[7:0]$945 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2469:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$874_EN[7:0]$944 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2472:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$873_EN[7:0]$943 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2475:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$872_EN[7:0]$942 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2478:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$871_EN[7:0]$941 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2481:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$870_EN[7:0]$940 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2484:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$869_EN[7:0]$939 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2487:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$868_EN[7:0]$938 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2490:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$867_EN[7:0]$937 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2493:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$866_EN[7:0]$936 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2496:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$865_EN[7:0]$935 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2499:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$864_EN[7:0]$934 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2502:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$863_EN[7:0]$933 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2505:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$862_EN[7:0]$932 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2508:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$861_EN[7:0]$931 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2511:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$860_EN[7:0]$930 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2514:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$859_EN[7:0]$929 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2517:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$858_EN[7:0]$928 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2520:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$857_EN[7:0]$927 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2523:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$856_EN[7:0]$926 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2526:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$855_EN[7:0]$925 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2529:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$854_EN[7:0]$924 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2532:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$853_EN[7:0]$923 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2535:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$852_EN[7:0]$922 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2538:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$851_EN[7:0]$921 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2541:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$850_EN[7:0]$920 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2544:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$849_EN[7:0]$919 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2547:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$848_EN[7:0]$918 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2550:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$847_EN[7:0]$917 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2553:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$846_EN[7:0]$916 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2556:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$845_EN[7:0]$915 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2559:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$844_EN[7:0]$914 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2562:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$843_EN[7:0]$913 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2565:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$842_EN[7:0]$912 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2568:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$841_EN[7:0]$911 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2571:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$840_EN[7:0]$910 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2574:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$839_EN[7:0]$909 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2577:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$838_EN[7:0]$908 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2580:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$837_EN[7:0]$907 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2583:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$836_EN[7:0]$906 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2586:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$835_EN[7:0]$905 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2589:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$834_EN[7:0]$904 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2592:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$833_EN[7:0]$903 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2595:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$832_EN[7:0]$902 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2598:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$831_EN[7:0]$901 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2601:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$830_EN[7:0]$900 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2604:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$829_EN[7:0]$899 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2607:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$828_EN[7:0]$898 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2610:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$827_EN[7:0]$897 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2613:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$826_EN[7:0]$896 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2616:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$825_EN[7:0]$895 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2619:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$824_EN[7:0]$894 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2622:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$823_EN[7:0]$893 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2625:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892
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|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$822_EN[7:0]$892 [0] }
|
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Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2628:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$821_EN[7:0]$891 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2631:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$820_EN[7:0]$890 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2634:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:287$819_EN[7:0]$889 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2637:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:286$818_EN[7:0]$888 [0] }
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New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2641: { $auto$opt_reduce.cc:137:opt_pmux$5657 $flatten\u_graph_engine.$procmux$2646_CMP }
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|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3905: { $flatten\u_spi_engine.$procmux$3906_CMP $auto$opt_reduce.cc:137:opt_pmux$5659 }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2918:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.$procmux$2918_Y
|
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New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.$procmux$2918_Y [0]
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New connections: $flatten\u_graph_engine.$procmux$2918_Y [7:1] = { $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] $flatten\u_graph_engine.$procmux$2918_Y [0] }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4204: { $auto$opt_reduce.cc:137:opt_pmux$5661 $flatten\u_spi_engine.$procmux$4208_CMP $flatten\u_spi_engine.$procmux$4209_CMP $flatten\u_spi_engine.$procmux$4210_CMP $flatten\u_spi_engine.$procmux$4077_CTRL }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3929: $auto$opt_reduce.cc:137:opt_pmux$5663
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New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3164: { $flatten\u_graph_engine.$procmux$2642_CMP $flatten\u_graph_engine.$procmux$2646_CMP $auto$opt_reduce.cc:137:opt_pmux$5665 }
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New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3790: $auto$opt_reduce.cc:137:opt_pmux$5667
|
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Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_act_buffer.$procmux$5081:
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Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665
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New ports: A=1'0, B=1'1, Y=$flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0]
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New connections: $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [7:1] = { $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] $flatten\u_graph_engine.\u_act_buffer.$0$memwr$\mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/act_buffer.v:57$661_EN[7:0]$665 [0] }
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Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1822:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1822_Y
|
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New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1822_Y [0]
|
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New connections: $flatten\u_neuron_memory.$procmux$1822_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] $flatten\u_neuron_memory.$procmux$1822_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1852:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1852_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1852_Y [0]
|
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New connections: $flatten\u_neuron_memory.$procmux$1852_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] $flatten\u_neuron_memory.$procmux$1852_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1889:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$procmux$1889_Y
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$procmux$1889_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1889_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] $flatten\u_neuron_memory.$procmux$1889_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2013:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137
|
|
New ports: A=1'0, B=1'1, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:304$1131_EN[7:0]$1137 [0] }
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New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2228: { $flatten\u_neuron_memory.$procmux$1825_CMP $auto$opt_reduce.cc:137:opt_pmux$5669 $flatten\u_neuron_memory.$procmux$2045_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4669: $auto$opt_reduce.cc:137:opt_pmux$5671
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4855: { $auto$opt_reduce.cc:137:opt_pmux$5673 $flatten\u_psram_ctrl.$procmux$4743_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4867: { $auto$opt_reduce.cc:137:opt_pmux$5675 $flatten\u_psram_ctrl.$procmux$4743_CMP }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2695:
|
|
Old ports: A=$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$1033, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957
|
|
New ports: A=$flatten\u_graph_engine.$procmux$2918_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [7:1] = { $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] $flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_EN[7:0]$957 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.$procmux$2704:
|
|
Old ports: A=$flatten\u_graph_engine.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$1030, B=8'00000000, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954
|
|
New ports: A=$flatten\u_graph_engine.$procmux$2419_Y [0], B=1'0, Y=$flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0]
|
|
New connections: $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [7:1] = { $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] $flatten\u_graph_engine.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:495$882_EN[7:0]$954 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1923:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1184, Y=$flatten\u_neuron_memory.$procmux$1923_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1822_Y [0], Y=$flatten\u_neuron_memory.$procmux$1923_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1923_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] $flatten\u_neuron_memory.$procmux$1923_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1944:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1176, Y=$flatten\u_neuron_memory.$procmux$1944_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1852_Y [0], Y=$flatten\u_neuron_memory.$procmux$1944_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1944_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] $flatten\u_neuron_memory.$procmux$1944_Y [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$1972:
|
|
Old ports: A=8'00000000, B=$flatten\u_neuron_memory.$3$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1168, Y=$flatten\u_neuron_memory.$procmux$1972_Y
|
|
New ports: A=1'0, B=$flatten\u_neuron_memory.$procmux$1889_Y [0], Y=$flatten\u_neuron_memory.$procmux$1972_Y [0]
|
|
New connections: $flatten\u_neuron_memory.$procmux$1972_Y [7:1] = { $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] $flatten\u_neuron_memory.$procmux$1972_Y [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2050:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1165, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1923_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] $flatten\u_neuron_memory.$0$memwr$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:449$1134_EN[7:0]$1146 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2059:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1162, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1944_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] $flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_EN[7:0]$1143 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.$procmux$2068:
|
|
Old ports: A=$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1159, B=8'00000000, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140
|
|
New ports: A=$flatten\u_neuron_memory.$procmux$1972_Y [0], B=1'0, Y=$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0]
|
|
New connections: $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [7:1] = { $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] $flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_EN[7:0]$1140 [0] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 90 changes.
|
|
|
|
17.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1660 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1566 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1563 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~291 debug messages>
|
|
Removed a total of 97 cells.
|
|
|
|
17.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 1-bit at position 0 on $flatten\u_psram_ctrl.$procdff$5524 ($dff) from module spi_neuron_top.
|
|
|
|
17.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 459 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1231 debug messages>
|
|
|
|
17.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4145: { $flatten\u_spi_engine.$procmux$4146_CMP $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:236$767_Y $auto$opt_reduce.cc:137:opt_pmux$5677 $flatten\u_spi_engine.$procmux$3989_CMP $flatten\u_spi_engine.$procmux$3951_CMP $flatten\u_spi_engine.$procmux$3791_CMP $flatten\u_spi_engine.$procmux$3992_CMP $flatten\u_spi_engine.$procmux$3792_CMP $flatten\u_spi_engine.$procmux$3971_CMP $flatten\u_spi_engine.$procmux$3668_CMP $flatten\u_spi_engine.$procmux$3677_CMP $flatten\u_spi_engine.$procmux$3710_CMP $flatten\u_spi_engine.$procmux$3741_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3697: { $auto$opt_reduce.cc:137:opt_pmux$5679 $flatten\u_spi_engine.$procmux$3677_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2029: { $flatten\u_neuron_memory.$procmux$1825_CMP $auto$opt_reduce.cc:137:opt_pmux$5681 $flatten\u_neuron_memory.$procmux$2045_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2115: { $flatten\u_neuron_memory.$procmux$1825_CMP $auto$opt_reduce.cc:137:opt_pmux$5683 $flatten\u_neuron_memory.$procmux$2045_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_arbiter.$procmux$1728: { $auto$opt_reduce.cc:137:opt_pmux$5685 $flatten\u_arbiter.$procmux$1722_CMP }
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4912: { $flatten\u_psram_ctrl.$procmux$4832_CMP $auto$opt_reduce.cc:137:opt_pmux$5687 $flatten\u_psram_ctrl.$procmux$4743_CMP $flatten\u_psram_ctrl.$procmux$4862_CMP }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 6 changes.
|
|
|
|
17.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1568 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1567 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~3 debug messages>
|
|
Removed a total of 1 cells.
|
|
|
|
17.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1212 debug messages>
|
|
|
|
17.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.12.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1567 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.12.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.12.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.12.23. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
17.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Found FSM state register spi_neuron_top.u_neuron_memory.state.
|
|
Not marking spi_neuron_top.u_neuron_memory.access_wdata as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
Found FSM state register spi_neuron_top.u_layer_sequencer.state.
|
|
Found FSM state register spi_neuron_top.u_neuron_memory.u_mem.state.
|
|
Found FSM state register spi_neuron_top.u_arbiter.owner.
|
|
Found FSM state register spi_neuron_top.u_spi_engine.resp_len.
|
|
Found FSM state register spi_neuron_top.u_spi_engine.state.
|
|
Found FSM state register spi_neuron_top.u_int8_access.state.
|
|
Found FSM state register spi_neuron_top.u_memory_if.state.
|
|
Found FSM state register spi_neuron_top.u_psram_ctrl.state.
|
|
Found FSM state register spi_neuron_top.u_graph_engine.state.
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17.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
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Extracting FSM `\u_neuron_memory.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_neuron_memory.$procdff$5332
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root of input selection tree: $flatten\u_neuron_memory.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \graph_rst
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found ctrl input: $flatten\u_neuron_memory.$procmux$1825_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$2018_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$2217_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$1855_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$1892_CMP
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found ctrl input: $flatten\u_neuron_memory.$procmux$2045_CMP
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found state code: 4'0000
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found ctrl input: \u_neuron_memory.u_neuron.done
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found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1186_Y
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found state code: 4'0010
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found state code: 4'0101
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found ctrl input: \u_neuron_memory.u_mem.ready
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found state code: 4'0100
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found ctrl input: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1170_Y
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found state code: 4'0011
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found ctrl input: \mux_nm_start
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found state code: 4'0001
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found ctrl output: $flatten\u_neuron_memory.$procmux$2217_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$2045_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$2018_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1892_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1855_CMP
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found ctrl output: $flatten\u_neuron_memory.$procmux$1825_CMP
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ctrl inputs: { $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1170_Y $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1186_Y \u_neuron_memory.u_mem.ready \u_neuron_memory.u_neuron.done \mux_nm_start \graph_rst }
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ctrl outputs: { $flatten\u_neuron_memory.$0\state[3:0] $flatten\u_neuron_memory.$procmux$1825_CMP $flatten\u_neuron_memory.$procmux$1855_CMP $flatten\u_neuron_memory.$procmux$1892_CMP $flatten\u_neuron_memory.$procmux$2018_CMP $flatten\u_neuron_memory.$procmux$2045_CMP $flatten\u_neuron_memory.$procmux$2217_CMP }
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transition: 4'0000 6'----00 -> 4'0000 10'0000000010
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transition: 4'0000 6'----10 -> 4'0001 10'0001000010
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transition: 4'0000 6'-----1 -> 4'0000 10'0000000010
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transition: 4'0100 6'-----0 -> 4'0101 10'0101000100
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transition: 4'0100 6'-----1 -> 4'0000 10'0000000100
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transition: 4'0010 6'--0--0 -> 4'0010 10'0010010000
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transition: 4'0010 6'0-1--0 -> 4'0010 10'0010010000
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transition: 4'0010 6'1-1--0 -> 4'0011 10'0011010000
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transition: 4'0010 6'-----1 -> 4'0000 10'0000010000
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transition: 4'0001 6'--0--0 -> 4'0001 10'0001001000
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transition: 4'0001 6'0-1--0 -> 4'0001 10'0001001000
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transition: 4'0001 6'1-1--0 -> 4'0010 10'0010001000
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transition: 4'0001 6'-----1 -> 4'0000 10'0000001000
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transition: 4'0101 6'---0-0 -> 4'0101 10'0101100000
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transition: 4'0101 6'-0-1-0 -> 4'0010 10'0010100000
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transition: 4'0101 6'-1-1-0 -> 4'0000 10'0000100000
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transition: 4'0101 6'-----1 -> 4'0000 10'0000100000
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transition: 4'0011 6'--0--0 -> 4'0011 10'0011000001
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transition: 4'0011 6'--1--0 -> 4'0100 10'0100000001
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transition: 4'0011 6'-----1 -> 4'0000 10'0000000001
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Extracting FSM `\u_layer_sequencer.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_layer_sequencer.$procdff$5460
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root of input selection tree: $flatten\u_layer_sequencer.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3330_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3309_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3333_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3319_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3186_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3310_CMP
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found ctrl input: $flatten\u_layer_sequencer.$procmux$3350_CMP
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found state code: 4'0000
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found ctrl input: \u_arbiter.c_ready
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$811_Y
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found state code: 4'0101
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$813_Y
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found state code: 4'0001
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found state code: 4'0110
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found ctrl input: \u_neuron_memory.done
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found state code: 4'0100
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found ctrl input: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$800_Y
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found state code: 4'0011
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found state code: 4'0010
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found ctrl input: \seq_run_start
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3350_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3333_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3330_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3319_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3310_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3309_CMP
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found ctrl output: $flatten\u_layer_sequencer.$procmux$3186_CMP
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ctrl inputs: { $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$800_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$811_Y $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$813_Y \u_neuron_memory.done \u_arbiter.c_ready \seq_run_start \rst }
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ctrl outputs: { $flatten\u_layer_sequencer.$0\state[3:0] $flatten\u_layer_sequencer.$procmux$3186_CMP $flatten\u_layer_sequencer.$procmux$3309_CMP $flatten\u_layer_sequencer.$procmux$3310_CMP $flatten\u_layer_sequencer.$procmux$3319_CMP $flatten\u_layer_sequencer.$procmux$3330_CMP $flatten\u_layer_sequencer.$procmux$3333_CMP $flatten\u_layer_sequencer.$procmux$3350_CMP }
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transition: 4'0000 7'-----00 -> 4'0000 11'00000000001
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transition: 4'0000 7'-----10 -> 4'0001 11'00010000001
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transition: 4'0000 7'------1 -> 4'0000 11'00000000001
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transition: 4'0100 7'---0--0 -> 4'0100 11'01000000010
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transition: 4'0100 7'---1--0 -> 4'0101 11'01010000010
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transition: 4'0100 7'------1 -> 4'0000 11'00000000010
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transition: 4'0010 7'----0-0 -> 4'0010 11'00101000000
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transition: 4'0010 7'0---1-0 -> 4'0001 11'00011000000
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transition: 4'0010 7'1---1-0 -> 4'0011 11'00111000000
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transition: 4'0010 7'------1 -> 4'0000 11'00001000000
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transition: 4'0110 7'----0-0 -> 4'0110 11'01100000100
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transition: 4'0110 7'-0--1-0 -> 4'0101 11'01010000100
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transition: 4'0110 7'-10-1-0 -> 4'0001 11'00010000100
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transition: 4'0110 7'-11-1-0 -> 4'0000 11'00000000100
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transition: 4'0110 7'------1 -> 4'0000 11'00000000100
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transition: 4'0001 7'------0 -> 4'0010 11'00100010000
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transition: 4'0001 7'------1 -> 4'0000 11'00000010000
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transition: 4'0101 7'------0 -> 4'0110 11'01100100000
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transition: 4'0101 7'------1 -> 4'0000 11'00000100000
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transition: 4'0011 7'------0 -> 4'0100 11'01000001000
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transition: 4'0011 7'------1 -> 4'0000 11'00000001000
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Extracting FSM `\u_neuron_memory.u_mem.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_neuron_memory.\u_mem.$procdff$5533
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root of input selection tree: $flatten\u_neuron_memory.\u_mem.$0\state[1:0]
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found reset state: 2'00 (guessed from mux tree)
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found ctrl input: \graph_rst
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found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4991_CMP
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found ctrl input: $flatten\u_neuron_memory.\u_mem.$procmux$4983_CMP
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found state code: 2'00
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found ctrl input: \u_arbiter.b_ready
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found ctrl input: \u_neuron_memory.access_req
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found state code: 2'01
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found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4991_CMP
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found ctrl output: $flatten\u_neuron_memory.\u_mem.$procmux$4983_CMP
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ctrl inputs: { \u_neuron_memory.access_req \u_arbiter.b_ready \graph_rst }
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ctrl outputs: { $flatten\u_neuron_memory.\u_mem.$procmux$4991_CMP $flatten\u_neuron_memory.\u_mem.$procmux$4983_CMP $flatten\u_neuron_memory.\u_mem.$0\state[1:0] }
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transition: 2'00 3'0-0 -> 2'00 4'0100
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transition: 2'00 3'1-0 -> 2'01 4'0101
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transition: 2'00 3'--1 -> 2'00 4'0100
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transition: 2'01 3'-00 -> 2'01 4'1001
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transition: 2'01 3'-10 -> 2'00 4'1000
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transition: 2'01 3'--1 -> 2'00 4'1000
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Extracting FSM `\u_arbiter.owner' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_arbiter.$procdff$5331
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root of input selection tree: $flatten\u_arbiter.$0\owner[1:0]
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found reset state: 2'00 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: $flatten\u_arbiter.$procmux$1722_CMP
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found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5685
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found ctrl input: \u_neuron_memory.u_mem.mem_req
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found ctrl input: \portc_req
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found ctrl input: \u_spi_engine.ram_req
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found state code: 2'01
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found state code: 2'11
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found state code: 2'10
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found ctrl input: \u_int8_access.ready
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found state code: 2'00
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found ctrl output: $flatten\u_arbiter.$procmux$1722_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1706_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1697_CMP
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found ctrl output: $flatten\u_arbiter.$procmux$1689_CMP
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ctrl inputs: { \u_spi_engine.ram_req \u_neuron_memory.u_mem.mem_req \u_int8_access.ready \portc_req \rst $auto$opt_reduce.cc:137:opt_pmux$5685 }
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ctrl outputs: { $flatten\u_arbiter.$0\owner[1:0] $flatten\u_arbiter.$procmux$1689_CMP $flatten\u_arbiter.$procmux$1697_CMP $flatten\u_arbiter.$procmux$1706_CMP $flatten\u_arbiter.$procmux$1722_CMP }
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transition: 2'00 6'00-00- -> 2'00 6'000001
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transition: 2'00 6'10-00- -> 2'01 6'010001
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transition: 2'00 6'-0-10- -> 2'11 6'110001
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transition: 2'00 6'-1--0- -> 2'10 6'100001
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transition: 2'00 6'----1- -> 2'00 6'000001
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transition: 2'10 6'--0-0- -> 2'10 6'100100
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transition: 2'10 6'--1-0- -> 2'00 6'000100
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transition: 2'10 6'----1- -> 2'00 6'000100
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transition: 2'01 6'--0-0- -> 2'01 6'010010
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transition: 2'01 6'--1-0- -> 2'00 6'000010
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transition: 2'01 6'----1- -> 2'00 6'000010
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transition: 2'11 6'--0-0- -> 2'11 6'111000
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transition: 2'11 6'--1-0- -> 2'00 6'001000
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transition: 2'11 6'----1- -> 2'00 6'001000
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Extracting FSM `\u_spi_engine.resp_len' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_spi_engine.$procdff$5510
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root of input selection tree: $flatten\u_spi_engine.$0\resp_len[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: \u_spi_slave.cs_end
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found ctrl input: $flatten\u_spi_engine.$procmux$3741_CMP
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found ctrl input: \u_spi_slave.rx_valid
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found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5659
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found ctrl input: $flatten\u_spi_engine.$procmux$3906_CMP
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found state code: 4'0001
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found state code: 4'1011
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found state code: 4'0000
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ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$procmux$3741_CMP $flatten\u_spi_engine.$procmux$3906_CMP \rst $auto$opt_reduce.cc:137:opt_pmux$5659 }
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ctrl outputs: $flatten\u_spi_engine.$0\resp_len[3:0]
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transition: 4'0000 6'-00-0- -> 4'0000 4'0000
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transition: 4'0000 6'001-0- -> 4'0000 4'0000
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transition: 4'0000 6'101000 -> 4'0000 4'0000
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transition: 4'0000 6'10110- -> 4'1011 4'1011
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transition: 4'0000 6'101-01 -> 4'0001 4'0001
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transition: 4'0000 6'-1--0- -> 4'0000 4'0000
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transition: 4'0000 6'----1- -> 4'0000 4'0000
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transition: 4'0001 6'-00-0- -> 4'0001 4'0001
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transition: 4'0001 6'001-0- -> 4'0001 4'0001
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transition: 4'0001 6'101000 -> 4'0001 4'0001
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transition: 4'0001 6'10110- -> 4'1011 4'1011
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transition: 4'0001 6'101-01 -> 4'0001 4'0001
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transition: 4'0001 6'-1--0- -> 4'0001 4'0001
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transition: 4'0001 6'----1- -> 4'0000 4'0000
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transition: 4'1011 6'-00-0- -> 4'1011 4'1011
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transition: 4'1011 6'001-0- -> 4'1011 4'1011
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transition: 4'1011 6'101000 -> 4'1011 4'1011
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transition: 4'1011 6'10110- -> 4'1011 4'1011
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transition: 4'1011 6'101-01 -> 4'0001 4'0001
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transition: 4'1011 6'-1--0- -> 4'1011 4'1011
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transition: 4'1011 6'----1- -> 4'0000 4'0000
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Extracting FSM `\u_spi_engine.state' from module `\spi_neuron_top'.
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found $dff cell for state register: $flatten\u_spi_engine.$procdff$5499
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root of input selection tree: $flatten\u_spi_engine.$0\state[3:0]
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found reset state: 4'0000 (guessed from mux tree)
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found ctrl input: \rst
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found ctrl input: \u_spi_slave.cs_end
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found ctrl input: $flatten\u_spi_engine.$procmux$3741_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3710_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3677_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3668_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3971_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3792_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3992_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3791_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3951_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$3989_CMP
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found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5677
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:236$767_Y
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found ctrl input: $flatten\u_spi_engine.$procmux$4146_CMP
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found state code: 4'0000
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found ctrl input: \u_spi_slave.rx_valid
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found ctrl input: $flatten\u_spi_engine.$procmux$4077_CTRL
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found ctrl input: $flatten\u_spi_engine.$procmux$4210_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$4209_CMP
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found ctrl input: $flatten\u_spi_engine.$procmux$4208_CMP
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found ctrl input: $auto$opt_reduce.cc:137:opt_pmux$5661
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found state code: 4'1011
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found state code: 4'0010
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found state code: 4'0001
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found state code: 4'1100
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found state code: 4'1101
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found state code: 4'1010
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:507$780_Y
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:511$781_Y
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found state code: 4'0011
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:558$783_Y
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:563$784_Y
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:567$785_Y
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found state code: 4'0111
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found state code: 4'0100
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found state code: 4'0101
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found state code: 4'0110
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found ctrl input: \u_arbiter.a_ready
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:619$789_Y
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found state code: 4'1000
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found state code: 4'1001
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found ctrl input: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$796_Y
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found ctrl output: $flatten\u_spi_engine.$procmux$3792_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3791_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$4155_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$4146_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3710_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3668_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3677_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3992_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3989_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3971_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3951_CMP
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found ctrl output: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:236$767_Y
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found ctrl output: $flatten\u_spi_engine.$procmux$3741_CMP
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found ctrl output: $flatten\u_spi_engine.$procmux$3842_CMP
|
|
ctrl inputs: { \u_spi_slave.rx_valid \u_spi_slave.cs_end $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:507$780_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:511$781_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:558$783_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:563$784_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:567$785_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:619$789_Y $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$796_Y $flatten\u_spi_engine.$procmux$4077_CTRL $flatten\u_spi_engine.$procmux$4208_CMP $flatten\u_spi_engine.$procmux$4209_CMP $flatten\u_spi_engine.$procmux$4210_CMP \u_arbiter.a_ready \rst $auto$opt_reduce.cc:137:opt_pmux$5661 $auto$opt_reduce.cc:137:opt_pmux$5677 }
|
|
ctrl outputs: { $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:236$767_Y $flatten\u_spi_engine.$0\state[3:0] $flatten\u_spi_engine.$procmux$3668_CMP $flatten\u_spi_engine.$procmux$3677_CMP $flatten\u_spi_engine.$procmux$3710_CMP $flatten\u_spi_engine.$procmux$3741_CMP $flatten\u_spi_engine.$procmux$3791_CMP $flatten\u_spi_engine.$procmux$3792_CMP $flatten\u_spi_engine.$procmux$3842_CMP $flatten\u_spi_engine.$procmux$3951_CMP $flatten\u_spi_engine.$procmux$3971_CMP $flatten\u_spi_engine.$procmux$3989_CMP $flatten\u_spi_engine.$procmux$3992_CMP $flatten\u_spi_engine.$procmux$4146_CMP $flatten\u_spi_engine.$procmux$4155_CMP }
|
|
transition: 4'0000 17'00------------0-- -> 4'0000 18'000000001000000000
|
|
transition: 4'0000 17'10-------0000-00- -> 4'1011 18'010110001000000000
|
|
transition: 4'0000 17'10------------01- -> 4'1010 18'010100001000000000
|
|
transition: 4'0000 17'10--------1---0-- -> 4'1101 18'011010001000000000
|
|
transition: 4'0000 17'10---------1--0-- -> 4'1100 18'011000001000000000
|
|
transition: 4'0000 17'10----------1-0-- -> 4'0001 18'000010001000000000
|
|
transition: 4'0000 17'10-------1----0-- -> 4'0010 18'000100001000000000
|
|
transition: 4'0000 17'-1------------0-- -> 4'0000 18'000000001000000000
|
|
transition: 4'0000 17'--------------1-- -> 4'0000 18'000000001000000000
|
|
transition: 4'1000 17'-0-----------00-- -> 4'1000 18'010000000000100000
|
|
transition: 4'1000 17'-0-----------10-- -> 4'1001 18'010010000000100000
|
|
transition: 4'1000 17'-1------------0-- -> 4'0000 18'000000000000100000
|
|
transition: 4'1000 17'--------------1-- -> 4'0000 18'000000000000100000
|
|
transition: 4'0100 17'00------------0-- -> 4'0100 18'001000000000010000
|
|
transition: 4'0100 17'10------------0-- -> 4'0101 18'001010000000010000
|
|
transition: 4'0100 17'-1------------0-- -> 4'0000 18'000000000000010000
|
|
transition: 4'0100 17'--------------1-- -> 4'0000 18'000000000000010000
|
|
transition: 4'1100 17'00------------0-- -> 4'1100 18'011000000001000000
|
|
transition: 4'1100 17'10------------0-- -> 4'1011 18'010110000001000000
|
|
transition: 4'1100 17'-1------------0-- -> 4'0000 18'000000000001000000
|
|
transition: 4'1100 17'--------------1-- -> 4'0000 18'000000000001000000
|
|
transition: 4'0010 17'00------------0-- -> 4'0010 18'000100100000000000
|
|
transition: 4'0010 17'100-----------0-- -> 4'0010 18'000100100000000000
|
|
transition: 4'0010 17'1010----------0-- -> 4'0011 18'000110100000000000
|
|
transition: 4'0010 17'1011----------0-- -> 4'1011 18'010110100000000000
|
|
transition: 4'0010 17'-1------------0-- -> 4'0000 18'000000100000000000
|
|
transition: 4'0010 17'--------------1-- -> 4'0000 18'000000100000000000
|
|
transition: 4'1010 17'00------------0-- -> 4'1010 18'110100000000000000
|
|
transition: 4'1010 17'10------0-----0-- -> 4'1010 18'110100000000000000
|
|
transition: 4'1010 17'10------1-----0-- -> 4'1011 18'110110000000000000
|
|
transition: 4'1010 17'-1------------0-- -> 4'0000 18'100000000000000000
|
|
transition: 4'1010 17'--------------1-- -> 4'0000 18'100000000000000000
|
|
transition: 4'0110 17'-0-----------00-- -> 4'0110 18'001100000000000100
|
|
transition: 4'0110 17'-0-----0-----10-- -> 4'0100 18'001000000000000100
|
|
transition: 4'0110 17'-0-----1-----10-- -> 4'1011 18'010110000000000100
|
|
transition: 4'0110 17'-1------------0-- -> 4'0000 18'000000000000000100
|
|
transition: 4'0110 17'--------------1-- -> 4'0000 18'000000000000000100
|
|
transition: 4'0001 17'00------------0-- -> 4'0001 18'000010010000000000
|
|
transition: 4'0001 17'10------------0-- -> 4'0010 18'000100010000000000
|
|
transition: 4'0001 17'-1------------0-- -> 4'0000 18'000000010000000000
|
|
transition: 4'0001 17'--------------1-- -> 4'0000 18'000000010000000000
|
|
transition: 4'1001 17'00------------0-- -> 4'1001 18'010010000000001000
|
|
transition: 4'1001 17'10-----0------0-- -> 4'0111 18'001110000000001000
|
|
transition: 4'1001 17'10-----1------0-- -> 4'1011 18'010110000000001000
|
|
transition: 4'1001 17'-1------------0-- -> 4'0000 18'000000000000001000
|
|
transition: 4'1001 17'--------------1-- -> 4'0000 18'000000000000001000
|
|
transition: 4'0101 17'-0------------0-- -> 4'0110 18'001100000010000000
|
|
transition: 4'0101 17'-1------------0-- -> 4'0000 18'000000000010000000
|
|
transition: 4'0101 17'--------------1-- -> 4'0000 18'000000000010000000
|
|
transition: 4'1101 17'00------------0-- -> 4'1101 18'011010000000000001
|
|
transition: 4'1101 17'10------------0-- -> 4'1011 18'010110000000000001
|
|
transition: 4'1101 17'-1------------0-- -> 4'0000 18'000000000000000001
|
|
transition: 4'1101 17'--------------1-- -> 4'0000 18'000000000000000001
|
|
transition: 4'0011 17'00------------0-- -> 4'0011 18'000111000000000000
|
|
transition: 4'0011 17'10--0---------0-- -> 4'0011 18'000111000000000000
|
|
transition: 4'0011 17'10--100-------0-- -> 4'0111 18'001111000000000000
|
|
transition: 4'0011 17'10--101-------0-- -> 4'0100 18'001001000000000000
|
|
transition: 4'0011 17'10--11--------0-- -> 4'1011 18'010111000000000000
|
|
transition: 4'0011 17'-1------------0-- -> 4'0000 18'000001000000000000
|
|
transition: 4'0011 17'--------------1-- -> 4'0000 18'000001000000000000
|
|
transition: 4'1011 17'-0------------0-- -> 4'1011 18'010110000000000010
|
|
transition: 4'1011 17'-1------------0-- -> 4'0000 18'000000000000000010
|
|
transition: 4'1011 17'--------------1-- -> 4'0000 18'000000000000000010
|
|
transition: 4'0111 17'-0------------0-- -> 4'1000 18'010000000100000000
|
|
transition: 4'0111 17'-1------------0-- -> 4'0000 18'000000000100000000
|
|
transition: 4'0111 17'--------------1-- -> 4'0000 18'000000000100000000
|
|
Extracting FSM `\u_int8_access.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_int8_access.$procdff$5533
|
|
root of input selection tree: $flatten\u_int8_access.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_int8_access.$procmux$4991_CMP
|
|
found ctrl input: $flatten\u_int8_access.$procmux$4983_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \u_memory_if.ready
|
|
found ctrl input: \u_arbiter.m_req
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\u_int8_access.$procmux$4991_CMP
|
|
found ctrl output: $flatten\u_int8_access.$procmux$4983_CMP
|
|
ctrl inputs: { \u_arbiter.m_req \u_memory_if.ready \rst }
|
|
ctrl outputs: { $flatten\u_int8_access.$0\state[1:0] $flatten\u_int8_access.$procmux$4983_CMP $flatten\u_int8_access.$procmux$4991_CMP }
|
|
transition: 2'00 3'0-0 -> 2'00 4'0010
|
|
transition: 2'00 3'1-0 -> 2'01 4'0110
|
|
transition: 2'00 3'--1 -> 2'00 4'0010
|
|
transition: 2'01 3'-00 -> 2'01 4'0101
|
|
transition: 2'01 3'-10 -> 2'00 4'0001
|
|
transition: 2'01 3'--1 -> 2'00 4'0001
|
|
Extracting FSM `\u_memory_if.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_memory_if.$procdff$5312
|
|
root of input selection tree: $flatten\u_memory_if.$0\state[1:0]
|
|
found reset state: 2'00 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_memory_if.$procmux$1616_CMP
|
|
found ctrl input: $flatten\u_memory_if.$procmux$1608_CMP
|
|
found state code: 2'00
|
|
found ctrl input: \u_psram_ctrl.mem_ready
|
|
found ctrl input: \u_int8_access.mem_req
|
|
found state code: 2'01
|
|
found ctrl output: $flatten\u_memory_if.$procmux$1616_CMP
|
|
found ctrl output: $flatten\u_memory_if.$procmux$1608_CMP
|
|
ctrl inputs: { \u_int8_access.mem_req \u_psram_ctrl.mem_ready \rst }
|
|
ctrl outputs: { $flatten\u_memory_if.$0\state[1:0] $flatten\u_memory_if.$procmux$1608_CMP $flatten\u_memory_if.$procmux$1616_CMP }
|
|
transition: 2'00 3'0-0 -> 2'00 4'0010
|
|
transition: 2'00 3'1-0 -> 2'01 4'0110
|
|
transition: 2'00 3'--1 -> 2'00 4'0010
|
|
transition: 2'01 3'-00 -> 2'01 4'0101
|
|
transition: 2'01 3'-10 -> 2'00 4'0001
|
|
transition: 2'01 3'--1 -> 2'00 4'0001
|
|
Extracting FSM `\u_psram_ctrl.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_psram_ctrl.$procdff$5515
|
|
root of input selection tree: $flatten\u_psram_ctrl.$0\state[2:0]
|
|
found reset state: 3'000 (guessed from mux tree)
|
|
found ctrl input: \rst
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4832_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4762_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4743_CMP
|
|
found ctrl input: $flatten\u_psram_ctrl.$procmux$4862_CMP
|
|
found state code: 3'000
|
|
found state code: 3'001
|
|
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1263_Y
|
|
found state code: 3'100
|
|
found ctrl input: \u_memory_if.mem_req
|
|
found ctrl input: \u_memory_if.mem_wr
|
|
found state code: 3'010
|
|
found state code: 3'011
|
|
found ctrl input: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1261_Y
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4862_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4832_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4762_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4743_CMP
|
|
found ctrl output: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
ctrl inputs: { \u_memory_if.mem_req \u_memory_if.mem_wr $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1261_Y $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1263_Y \rst }
|
|
ctrl outputs: { $flatten\u_psram_ctrl.$0\state[2:0] $flatten\u_psram_ctrl.$procmux$4737_CMP $flatten\u_psram_ctrl.$procmux$4743_CMP $flatten\u_psram_ctrl.$procmux$4762_CMP $flatten\u_psram_ctrl.$procmux$4832_CMP $flatten\u_psram_ctrl.$procmux$4862_CMP }
|
|
transition: 3'000 5'--0-0 -> 3'000 8'00000001
|
|
transition: 3'000 5'--1-0 -> 3'001 8'00100001
|
|
transition: 3'000 5'----1 -> 3'000 8'00000001
|
|
transition: 3'100 5'----0 -> 3'001 8'00100010
|
|
transition: 3'100 5'----1 -> 3'000 8'00000010
|
|
transition: 3'010 5'---00 -> 3'010 8'01000100
|
|
transition: 3'010 5'---10 -> 3'001 8'00100100
|
|
transition: 3'010 5'----1 -> 3'000 8'00000100
|
|
transition: 3'001 5'0---0 -> 3'001 8'00101000
|
|
transition: 3'001 5'10--0 -> 3'010 8'01001000
|
|
transition: 3'001 5'11--0 -> 3'011 8'01101000
|
|
transition: 3'001 5'----1 -> 3'000 8'00001000
|
|
transition: 3'011 5'---00 -> 3'011 8'01110000
|
|
transition: 3'011 5'---10 -> 3'100 8'10010000
|
|
transition: 3'011 5'----1 -> 3'000 8'00010000
|
|
Extracting FSM `\u_graph_engine.state' from module `\spi_neuron_top'.
|
|
found $dff cell for state register: $flatten\u_graph_engine.$procdff$5360
|
|
root of input selection tree: $flatten\u_graph_engine.$0\state[3:0]
|
|
found reset state: 4'0000 (guessed from mux tree)
|
|
found ctrl input: \graph_rst
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2681_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2642_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2667_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2657_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2400_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2286_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2646_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2321_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2647_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2670_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2648_CMP
|
|
found ctrl input: $flatten\u_graph_engine.$procmux$2942_CTRL
|
|
found state code: 4'0000
|
|
found ctrl input: \u_arbiter.c_ready
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1059_Y
|
|
found state code: 4'0011
|
|
found state code: 4'1011
|
|
found ctrl input: \u_graph_engine.u_neuron.done
|
|
found ctrl input: \u_graph_engine.is_output_sink
|
|
found state code: 4'1010
|
|
found state code: 4'1001
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1056_Y
|
|
found state code: 4'0101
|
|
found state code: 4'1000
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1048_Y
|
|
found ctrl input: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1053_Y
|
|
found state code: 4'0111
|
|
found state code: 4'1100
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1044_Y
|
|
found state code: 4'0110
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1039_Y
|
|
found state code: 4'0100
|
|
found ctrl input: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1036_Y
|
|
found state code: 4'0001
|
|
found state code: 4'0010
|
|
found ctrl input: \graph_run_start
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2942_CMP [1]
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2942_CMP [0]
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2681_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2670_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2667_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2657_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2648_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2647_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2646_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2642_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2400_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2321_CMP
|
|
found ctrl output: $flatten\u_graph_engine.$procmux$2286_CMP
|
|
ctrl inputs: { \u_graph_engine.is_output_sink $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1036_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1039_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1044_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1048_Y $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1053_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1056_Y $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1059_Y $flatten\u_graph_engine.$procmux$2942_CTRL \u_graph_engine.u_neuron.done \u_arbiter.c_ready \graph_rst \graph_run_start }
|
|
ctrl outputs: { $flatten\u_graph_engine.$0\state[3:0] $flatten\u_graph_engine.$procmux$2286_CMP $flatten\u_graph_engine.$procmux$2321_CMP $flatten\u_graph_engine.$procmux$2400_CMP $flatten\u_graph_engine.$procmux$2642_CMP $flatten\u_graph_engine.$procmux$2646_CMP $flatten\u_graph_engine.$procmux$2647_CMP $flatten\u_graph_engine.$procmux$2648_CMP $flatten\u_graph_engine.$procmux$2657_CMP $flatten\u_graph_engine.$procmux$2667_CMP $flatten\u_graph_engine.$procmux$2670_CMP $flatten\u_graph_engine.$procmux$2681_CMP $flatten\u_graph_engine.$procmux$2942_CMP }
|
|
transition: 4'0000 13'-----------00 -> 4'0000 17'00000000000000001
|
|
transition: 4'0000 13'-----------01 -> 4'0001 17'00010000000000001
|
|
transition: 4'0000 13'-----------1- -> 4'0000 17'00000000000000001
|
|
transition: 4'1000 13'-----------0- -> 4'1001 17'10010000000100000
|
|
transition: 4'1000 13'-----------1- -> 4'0000 17'00000000000100000
|
|
transition: 4'0100 13'----------00- -> 4'0100 17'01000100000000000
|
|
transition: 4'0100 13'--0-------10- -> 4'0011 17'00110100000000000
|
|
transition: 4'0100 13'--1-------10- -> 4'0101 17'01010100000000000
|
|
transition: 4'0100 13'-----------1- -> 4'0000 17'00000100000000000
|
|
transition: 4'1100 13'-----------00 -> 4'1100 17'11000000000000010
|
|
transition: 4'1100 13'-----------01 -> 4'0001 17'00010000000000010
|
|
transition: 4'1100 13'-----------1- -> 4'0000 17'00000000000000010
|
|
transition: 4'0010 13'----------00- -> 4'0010 17'00100000000001000
|
|
transition: 4'0010 13'-0--------10- -> 4'0001 17'00010000000001000
|
|
transition: 4'0010 13'-1--------10- -> 4'0011 17'00110000000001000
|
|
transition: 4'0010 13'-----------1- -> 4'0000 17'00000000000001000
|
|
transition: 4'1010 13'-----------0- -> 4'1011 17'10110001000000000
|
|
transition: 4'1010 13'-----------1- -> 4'0000 17'00000001000000000
|
|
transition: 4'0110 13'----------00- -> 4'0110 17'01101000000000000
|
|
transition: 4'0110 13'----0-----10- -> 4'0101 17'01011000000000000
|
|
transition: 4'0110 13'----10----10- -> 4'0111 17'01111000000000000
|
|
transition: 4'0110 13'----11----10- -> 4'1100 17'11001000000000000
|
|
transition: 4'0110 13'-----------1- -> 4'0000 17'00001000000000000
|
|
transition: 4'0001 13'-----------0- -> 4'0010 17'00100000001000000
|
|
transition: 4'0001 13'-----------1- -> 4'0000 17'00000000001000000
|
|
transition: 4'1001 13'---------0-0- -> 4'1001 17'10010000000010000
|
|
transition: 4'1001 13'0------0-1-0- -> 4'0011 17'00110000000010000
|
|
transition: 4'1001 13'0------1-1-0- -> 4'0000 17'00000000000010000
|
|
transition: 4'1001 13'1--------1-0- -> 4'1010 17'10100000000010000
|
|
transition: 4'1001 13'-----------1- -> 4'0000 17'00000000000010000
|
|
transition: 4'0101 13'---0-------0- -> 4'0110 17'01100000100000000
|
|
transition: 4'0101 13'---1-------0- -> 4'1100 17'11000000100000000
|
|
transition: 4'0101 13'-----------1- -> 4'0000 17'00000000100000000
|
|
transition: 4'0011 13'-----------0- -> 4'0100 17'01000000010000000
|
|
transition: 4'0011 13'-----------1- -> 4'0000 17'00000000010000000
|
|
transition: 4'1011 13'----------00- -> 4'1011 17'10110000000000100
|
|
transition: 4'1011 13'-------0--10- -> 4'0011 17'00110000000000100
|
|
transition: 4'1011 13'-------1--10- -> 4'0000 17'00000000000000100
|
|
transition: 4'1011 13'-----------1- -> 4'0000 17'00000000000000100
|
|
transition: 4'0111 13'------0----0- -> 4'0101 17'01010010000000000
|
|
transition: 4'0111 13'------1----0- -> 4'1000 17'10000010000000000
|
|
transition: 4'0111 13'-----------1- -> 4'0000 17'00000010000000000
|
|
|
|
17.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\u_graph_engine.state$5748' from module `\spi_neuron_top'.
|
|
Removing unused input signal $flatten\u_graph_engine.$procmux$2942_CTRL.
|
|
Optimizing FSM `$fsm$\u_psram_ctrl.state$5741' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_memory_if.state$5737' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_int8_access.state$5733' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_spi_engine.state$5717' from module `\spi_neuron_top'.
|
|
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5677.
|
|
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5715' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_arbiter.owner$5709' from module `\spi_neuron_top'.
|
|
Removing unused input signal $auto$opt_reduce.cc:137:opt_pmux$5685.
|
|
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5705' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_layer_sequencer.state$5696' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_neuron_memory.state$5688' from module `\spi_neuron_top'.
|
|
|
|
17.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 153 unused cells and 153 unused wires.
|
|
<suppressed ~154 debug messages>
|
|
|
|
17.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
Optimizing FSM `$fsm$\u_psram_ctrl.state$5741' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [0].
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [1].
|
|
Removing unused output signal $flatten\u_psram_ctrl.$0\state[2:0] [2].
|
|
Optimizing FSM `$fsm$\u_graph_engine.state$5748' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_graph_engine.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_neuron_memory.state$5688' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_neuron_memory.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_layer_sequencer.state$5696' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_layer_sequencer.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_neuron_memory.u_mem.state$5705' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_neuron_memory.\u_mem.$0\state[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_arbiter.owner$5709' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [0].
|
|
Removing unused output signal $flatten\u_arbiter.$0\owner[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_spi_engine.resp_len$5715' from module `\spi_neuron_top'.
|
|
Optimizing FSM `$fsm$\u_spi_engine.state$5717' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_spi_engine.$procmux$4146_CMP.
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [0].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [1].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [2].
|
|
Removing unused output signal $flatten\u_spi_engine.$0\state[3:0] [3].
|
|
Optimizing FSM `$fsm$\u_int8_access.state$5733' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_int8_access.$0\state[1:0] [1].
|
|
Optimizing FSM `$fsm$\u_memory_if.state$5737' from module `\spi_neuron_top'.
|
|
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [0].
|
|
Removing unused output signal $flatten\u_memory_if.$0\state[1:0] [1].
|
|
|
|
17.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
Recoding FSM `$fsm$\u_psram_ctrl.state$5741' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
000 -> ----1
|
|
100 -> ---1-
|
|
010 -> --1--
|
|
001 -> -1---
|
|
011 -> 1----
|
|
Recoding FSM `$fsm$\u_graph_engine.state$5748' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> ------------1
|
|
1000 -> -----------1-
|
|
0100 -> ----------1--
|
|
1100 -> ---------1---
|
|
0010 -> --------1----
|
|
1010 -> -------1-----
|
|
0110 -> ------1------
|
|
0001 -> -----1-------
|
|
1001 -> ----1--------
|
|
0101 -> ---1---------
|
|
0011 -> --1----------
|
|
1011 -> -1-----------
|
|
0111 -> 1------------
|
|
Recoding FSM `$fsm$\u_neuron_memory.state$5688' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> -----1
|
|
0100 -> ----1-
|
|
0010 -> ---1--
|
|
0001 -> --1---
|
|
0101 -> -1----
|
|
0011 -> 1-----
|
|
Recoding FSM `$fsm$\u_layer_sequencer.state$5696' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> ------1
|
|
0100 -> -----1-
|
|
0010 -> ----1--
|
|
0110 -> ---1---
|
|
0001 -> --1----
|
|
0101 -> -1-----
|
|
0011 -> 1------
|
|
Recoding FSM `$fsm$\u_neuron_memory.u_mem.state$5705' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
Recoding FSM `$fsm$\u_arbiter.owner$5709' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> ---1
|
|
10 -> --1-
|
|
01 -> -1--
|
|
11 -> 1---
|
|
Recoding FSM `$fsm$\u_spi_engine.resp_len$5715' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> --1
|
|
0001 -> -1-
|
|
1011 -> 1--
|
|
Recoding FSM `$fsm$\u_spi_engine.state$5717' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
0000 -> -------------1
|
|
1000 -> ------------1-
|
|
0100 -> -----------1--
|
|
1100 -> ----------1---
|
|
0010 -> ---------1----
|
|
1010 -> --------1-----
|
|
0110 -> -------1------
|
|
0001 -> ------1-------
|
|
1001 -> -----1--------
|
|
0101 -> ----1---------
|
|
1101 -> ---1----------
|
|
0011 -> --1-----------
|
|
1011 -> -1------------
|
|
0111 -> 1-------------
|
|
Recoding FSM `$fsm$\u_int8_access.state$5733' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
Recoding FSM `$fsm$\u_memory_if.state$5737' from module `\spi_neuron_top' using `auto' encoding:
|
|
mapping auto encoding to `one-hot` for this FSM.
|
|
00 -> -1
|
|
01 -> 1-
|
|
|
|
17.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
FSM `$fsm$\u_psram_ctrl.state$5741' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_psram_ctrl.state$5741 (\u_psram_ctrl.state):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 5
|
|
Number of state bits: 5
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1263_Y
|
|
2: $flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:179$1261_Y
|
|
3: \u_memory_if.mem_wr
|
|
4: \u_memory_if.mem_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_psram_ctrl.$procmux$4862_CMP
|
|
1: $flatten\u_psram_ctrl.$procmux$4832_CMP
|
|
2: $flatten\u_psram_ctrl.$procmux$4762_CMP
|
|
3: $flatten\u_psram_ctrl.$procmux$4743_CMP
|
|
4: $flatten\u_psram_ctrl.$procmux$4737_CMP
|
|
|
|
State encoding:
|
|
0: 5'----1 <RESET STATE>
|
|
1: 5'---1-
|
|
2: 5'--1--
|
|
3: 5'-1---
|
|
4: 5'1----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'--0-0 -> 0 5'00001
|
|
1: 0 5'----1 -> 0 5'00001
|
|
2: 0 5'--1-0 -> 3 5'00001
|
|
3: 1 5'----1 -> 0 5'00010
|
|
4: 1 5'----0 -> 3 5'00010
|
|
5: 2 5'----1 -> 0 5'00100
|
|
6: 2 5'---00 -> 2 5'00100
|
|
7: 2 5'---10 -> 3 5'00100
|
|
8: 3 5'----1 -> 0 5'01000
|
|
9: 3 5'10--0 -> 2 5'01000
|
|
10: 3 5'0---0 -> 3 5'01000
|
|
11: 3 5'11--0 -> 4 5'01000
|
|
12: 4 5'----1 -> 0 5'10000
|
|
13: 4 5'---10 -> 1 5'10000
|
|
14: 4 5'---00 -> 4 5'10000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_graph_engine.state$5748' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_graph_engine.state$5748 (\u_graph_engine.state):
|
|
|
|
Number of input signals: 12
|
|
Number of output signals: 13
|
|
Number of state bits: 13
|
|
|
|
Input signals:
|
|
0: \graph_run_start
|
|
1: \graph_rst
|
|
2: \u_arbiter.c_ready
|
|
3: \u_graph_engine.u_neuron.done
|
|
4: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1059_Y
|
|
5: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1056_Y
|
|
6: $flatten\u_graph_engine.$logic_or$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1053_Y
|
|
7: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:449$1048_Y
|
|
8: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:420$1044_Y
|
|
9: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:389$1039_Y
|
|
10: $flatten\u_graph_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1036_Y
|
|
11: \u_graph_engine.is_output_sink
|
|
|
|
Output signals:
|
|
0: $flatten\u_graph_engine.$procmux$2942_CMP [0]
|
|
1: $flatten\u_graph_engine.$procmux$2942_CMP [1]
|
|
2: $flatten\u_graph_engine.$procmux$2681_CMP
|
|
3: $flatten\u_graph_engine.$procmux$2670_CMP
|
|
4: $flatten\u_graph_engine.$procmux$2667_CMP
|
|
5: $flatten\u_graph_engine.$procmux$2657_CMP
|
|
6: $flatten\u_graph_engine.$procmux$2648_CMP
|
|
7: $flatten\u_graph_engine.$procmux$2647_CMP
|
|
8: $flatten\u_graph_engine.$procmux$2646_CMP
|
|
9: $flatten\u_graph_engine.$procmux$2642_CMP
|
|
10: $flatten\u_graph_engine.$procmux$2400_CMP
|
|
11: $flatten\u_graph_engine.$procmux$2321_CMP
|
|
12: $flatten\u_graph_engine.$procmux$2286_CMP
|
|
|
|
State encoding:
|
|
0: 13'------------1 <RESET STATE>
|
|
1: 13'-----------1-
|
|
2: 13'----------1--
|
|
3: 13'---------1---
|
|
4: 13'--------1----
|
|
5: 13'-------1-----
|
|
6: 13'------1------
|
|
7: 13'-----1-------
|
|
8: 13'----1--------
|
|
9: 13'---1---------
|
|
10: 13'--1----------
|
|
11: 13'-1-----------
|
|
12: 13'1------------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 12'----------00 -> 0 13'0000000000001
|
|
1: 0 12'----------1- -> 0 13'0000000000001
|
|
2: 0 12'----------01 -> 7 13'0000000000001
|
|
3: 1 12'----------1- -> 0 13'0000000100000
|
|
4: 1 12'----------0- -> 8 13'0000000100000
|
|
5: 2 12'----------1- -> 0 13'0100000000000
|
|
6: 2 12'---------00- -> 2 13'0100000000000
|
|
7: 2 12'--1------10- -> 9 13'0100000000000
|
|
8: 2 12'--0------10- -> 10 13'0100000000000
|
|
9: 3 12'----------1- -> 0 13'0000000000010
|
|
10: 3 12'----------00 -> 3 13'0000000000010
|
|
11: 3 12'----------01 -> 7 13'0000000000010
|
|
12: 4 12'----------1- -> 0 13'0000000001000
|
|
13: 4 12'---------00- -> 4 13'0000000001000
|
|
14: 4 12'-0-------10- -> 7 13'0000000001000
|
|
15: 4 12'-1-------10- -> 10 13'0000000001000
|
|
16: 5 12'----------1- -> 0 13'0001000000000
|
|
17: 5 12'----------0- -> 11 13'0001000000000
|
|
18: 6 12'----------1- -> 0 13'1000000000000
|
|
19: 6 12'----11---10- -> 3 13'1000000000000
|
|
20: 6 12'---------00- -> 6 13'1000000000000
|
|
21: 6 12'----0----10- -> 9 13'1000000000000
|
|
22: 6 12'----10---10- -> 12 13'1000000000000
|
|
23: 7 12'----------1- -> 0 13'0000001000000
|
|
24: 7 12'----------0- -> 4 13'0000001000000
|
|
25: 8 12'0------11-0- -> 0 13'0000000010000
|
|
26: 8 12'----------1- -> 0 13'0000000010000
|
|
27: 8 12'1-------1-0- -> 5 13'0000000010000
|
|
28: 8 12'--------0-0- -> 8 13'0000000010000
|
|
29: 8 12'0------01-0- -> 10 13'0000000010000
|
|
30: 9 12'----------1- -> 0 13'0000100000000
|
|
31: 9 12'---1------0- -> 3 13'0000100000000
|
|
32: 9 12'---0------0- -> 6 13'0000100000000
|
|
33: 10 12'----------1- -> 0 13'0000010000000
|
|
34: 10 12'----------0- -> 2 13'0000010000000
|
|
35: 11 12'-------1-10- -> 0 13'0000000000100
|
|
36: 11 12'----------1- -> 0 13'0000000000100
|
|
37: 11 12'-------0-10- -> 10 13'0000000000100
|
|
38: 11 12'---------00- -> 11 13'0000000000100
|
|
39: 12 12'----------1- -> 0 13'0010000000000
|
|
40: 12 12'------1---0- -> 1 13'0010000000000
|
|
41: 12 12'------0---0- -> 9 13'0010000000000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_neuron_memory.state$5688' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_neuron_memory.state$5688 (\u_neuron_memory.state):
|
|
|
|
Number of input signals: 6
|
|
Number of output signals: 6
|
|
Number of state bits: 6
|
|
|
|
Input signals:
|
|
0: \graph_rst
|
|
1: \mux_nm_start
|
|
2: \u_neuron_memory.u_neuron.done
|
|
3: \u_neuron_memory.u_mem.ready
|
|
4: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1186_Y
|
|
5: $flatten\u_neuron_memory.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1170_Y
|
|
|
|
Output signals:
|
|
0: $flatten\u_neuron_memory.$procmux$2217_CMP
|
|
1: $flatten\u_neuron_memory.$procmux$2045_CMP
|
|
2: $flatten\u_neuron_memory.$procmux$2018_CMP
|
|
3: $flatten\u_neuron_memory.$procmux$1892_CMP
|
|
4: $flatten\u_neuron_memory.$procmux$1855_CMP
|
|
5: $flatten\u_neuron_memory.$procmux$1825_CMP
|
|
|
|
State encoding:
|
|
0: 6'-----1 <RESET STATE>
|
|
1: 6'----1-
|
|
2: 6'---1--
|
|
3: 6'--1---
|
|
4: 6'-1----
|
|
5: 6'1-----
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 6'----00 -> 0 6'000010
|
|
1: 0 6'-----1 -> 0 6'000010
|
|
2: 0 6'----10 -> 3 6'000010
|
|
3: 1 6'-----1 -> 0 6'000100
|
|
4: 1 6'-----0 -> 4 6'000100
|
|
5: 2 6'-----1 -> 0 6'010000
|
|
6: 2 6'--0--0 -> 2 6'010000
|
|
7: 2 6'0-1--0 -> 2 6'010000
|
|
8: 2 6'1-1--0 -> 5 6'010000
|
|
9: 3 6'-----1 -> 0 6'001000
|
|
10: 3 6'1-1--0 -> 2 6'001000
|
|
11: 3 6'--0--0 -> 3 6'001000
|
|
12: 3 6'0-1--0 -> 3 6'001000
|
|
13: 4 6'-1-1-0 -> 0 6'100000
|
|
14: 4 6'-----1 -> 0 6'100000
|
|
15: 4 6'-0-1-0 -> 2 6'100000
|
|
16: 4 6'---0-0 -> 4 6'100000
|
|
17: 5 6'-----1 -> 0 6'000001
|
|
18: 5 6'--1--0 -> 1 6'000001
|
|
19: 5 6'--0--0 -> 5 6'000001
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_layer_sequencer.state$5696' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_layer_sequencer.state$5696 (\u_layer_sequencer.state):
|
|
|
|
Number of input signals: 7
|
|
Number of output signals: 7
|
|
Number of state bits: 7
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \seq_run_start
|
|
2: \u_arbiter.c_ready
|
|
3: \u_neuron_memory.done
|
|
4: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$813_Y
|
|
5: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$811_Y
|
|
6: $flatten\u_layer_sequencer.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:235$800_Y
|
|
|
|
Output signals:
|
|
0: $flatten\u_layer_sequencer.$procmux$3350_CMP
|
|
1: $flatten\u_layer_sequencer.$procmux$3333_CMP
|
|
2: $flatten\u_layer_sequencer.$procmux$3330_CMP
|
|
3: $flatten\u_layer_sequencer.$procmux$3319_CMP
|
|
4: $flatten\u_layer_sequencer.$procmux$3310_CMP
|
|
5: $flatten\u_layer_sequencer.$procmux$3309_CMP
|
|
6: $flatten\u_layer_sequencer.$procmux$3186_CMP
|
|
|
|
State encoding:
|
|
0: 7'------1 <RESET STATE>
|
|
1: 7'-----1-
|
|
2: 7'----1--
|
|
3: 7'---1---
|
|
4: 7'--1----
|
|
5: 7'-1-----
|
|
6: 7'1------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 7'-----00 -> 0 7'0000001
|
|
1: 0 7'------1 -> 0 7'0000001
|
|
2: 0 7'-----10 -> 4 7'0000001
|
|
3: 1 7'------1 -> 0 7'0000010
|
|
4: 1 7'---0--0 -> 1 7'0000010
|
|
5: 1 7'---1--0 -> 5 7'0000010
|
|
6: 2 7'------1 -> 0 7'1000000
|
|
7: 2 7'----0-0 -> 2 7'1000000
|
|
8: 2 7'0---1-0 -> 4 7'1000000
|
|
9: 2 7'1---1-0 -> 6 7'1000000
|
|
10: 3 7'-11-1-0 -> 0 7'0000100
|
|
11: 3 7'------1 -> 0 7'0000100
|
|
12: 3 7'----0-0 -> 3 7'0000100
|
|
13: 3 7'-10-1-0 -> 4 7'0000100
|
|
14: 3 7'-0--1-0 -> 5 7'0000100
|
|
15: 4 7'------1 -> 0 7'0010000
|
|
16: 4 7'------0 -> 2 7'0010000
|
|
17: 5 7'------1 -> 0 7'0100000
|
|
18: 5 7'------0 -> 3 7'0100000
|
|
19: 6 7'------1 -> 0 7'0001000
|
|
20: 6 7'------0 -> 1 7'0001000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_neuron_memory.u_mem.state$5705' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_neuron_memory.u_mem.state$5705 (\u_neuron_memory.u_mem.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \graph_rst
|
|
1: \u_arbiter.b_ready
|
|
2: \u_neuron_memory.access_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_neuron_memory.\u_mem.$procmux$4983_CMP
|
|
1: $flatten\u_neuron_memory.\u_mem.$procmux$4991_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'01
|
|
1: 0 3'--1 -> 0 2'01
|
|
2: 0 3'1-0 -> 1 2'01
|
|
3: 1 3'-10 -> 0 2'10
|
|
4: 1 3'--1 -> 0 2'10
|
|
5: 1 3'-00 -> 1 2'10
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_arbiter.owner$5709' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_arbiter.owner$5709 (\u_arbiter.owner):
|
|
|
|
Number of input signals: 5
|
|
Number of output signals: 4
|
|
Number of state bits: 4
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \portc_req
|
|
2: \u_int8_access.ready
|
|
3: \u_neuron_memory.u_mem.mem_req
|
|
4: \u_spi_engine.ram_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_arbiter.$procmux$1722_CMP
|
|
1: $flatten\u_arbiter.$procmux$1706_CMP
|
|
2: $flatten\u_arbiter.$procmux$1697_CMP
|
|
3: $flatten\u_arbiter.$procmux$1689_CMP
|
|
|
|
State encoding:
|
|
0: 4'---1 <RESET STATE>
|
|
1: 4'--1-
|
|
2: 4'-1--
|
|
3: 4'1---
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 5'00-00 -> 0 4'0001
|
|
1: 0 5'----1 -> 0 4'0001
|
|
2: 0 5'-1--0 -> 1 4'0001
|
|
3: 0 5'10-00 -> 2 4'0001
|
|
4: 0 5'-0-10 -> 3 4'0001
|
|
5: 1 5'--1-0 -> 0 4'0100
|
|
6: 1 5'----1 -> 0 4'0100
|
|
7: 1 5'--0-0 -> 1 4'0100
|
|
8: 2 5'--1-0 -> 0 4'0010
|
|
9: 2 5'----1 -> 0 4'0010
|
|
10: 2 5'--0-0 -> 2 4'0010
|
|
11: 3 5'--1-0 -> 0 4'1000
|
|
12: 3 5'----1 -> 0 4'1000
|
|
13: 3 5'--0-0 -> 3 4'1000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_spi_engine.resp_len$5715' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_spi_engine.resp_len$5715 (\u_spi_engine.resp_len):
|
|
|
|
Number of input signals: 6
|
|
Number of output signals: 4
|
|
Number of state bits: 3
|
|
|
|
Input signals:
|
|
0: $auto$opt_reduce.cc:137:opt_pmux$5659
|
|
1: \rst
|
|
2: $flatten\u_spi_engine.$procmux$3906_CMP
|
|
3: $flatten\u_spi_engine.$procmux$3741_CMP
|
|
4: \u_spi_slave.cs_end
|
|
5: \u_spi_slave.rx_valid
|
|
|
|
Output signals:
|
|
0: $flatten\u_spi_engine.$0\resp_len[3:0] [0]
|
|
1: $flatten\u_spi_engine.$0\resp_len[3:0] [1]
|
|
2: $flatten\u_spi_engine.$0\resp_len[3:0] [2]
|
|
3: $flatten\u_spi_engine.$0\resp_len[3:0] [3]
|
|
|
|
State encoding:
|
|
0: 3'--1 <RESET STATE>
|
|
1: 3'-1-
|
|
2: 3'1--
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 6'101000 -> 0 4'0000
|
|
1: 0 6'-00-0- -> 0 4'0000
|
|
2: 0 6'001-0- -> 0 4'0000
|
|
3: 0 6'-1--0- -> 0 4'0000
|
|
4: 0 6'----1- -> 0 4'0000
|
|
5: 0 6'101-01 -> 1 4'0001
|
|
6: 0 6'10110- -> 2 4'1011
|
|
7: 1 6'----1- -> 0 4'0000
|
|
8: 1 6'101000 -> 1 4'0001
|
|
9: 1 6'101-01 -> 1 4'0001
|
|
10: 1 6'-00-0- -> 1 4'0001
|
|
11: 1 6'001-0- -> 1 4'0001
|
|
12: 1 6'-1--0- -> 1 4'0001
|
|
13: 1 6'10110- -> 2 4'1011
|
|
14: 2 6'----1- -> 0 4'0000
|
|
15: 2 6'101-01 -> 1 4'0001
|
|
16: 2 6'101000 -> 2 4'1011
|
|
17: 2 6'10110- -> 2 4'1011
|
|
18: 2 6'-00-0- -> 2 4'1011
|
|
19: 2 6'001-0- -> 2 4'1011
|
|
20: 2 6'-1--0- -> 2 4'1011
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_spi_engine.state$5717' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_spi_engine.state$5717 (\u_spi_engine.state):
|
|
|
|
Number of input signals: 16
|
|
Number of output signals: 13
|
|
Number of state bits: 14
|
|
|
|
Input signals:
|
|
0: $auto$opt_reduce.cc:137:opt_pmux$5661
|
|
1: \rst
|
|
2: \u_arbiter.a_ready
|
|
3: $flatten\u_spi_engine.$procmux$4210_CMP
|
|
4: $flatten\u_spi_engine.$procmux$4209_CMP
|
|
5: $flatten\u_spi_engine.$procmux$4208_CMP
|
|
6: $flatten\u_spi_engine.$procmux$4077_CTRL
|
|
7: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$796_Y
|
|
8: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:619$789_Y
|
|
9: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:567$785_Y
|
|
10: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:563$784_Y
|
|
11: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:558$783_Y
|
|
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:511$781_Y
|
|
13: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:507$780_Y
|
|
14: \u_spi_slave.cs_end
|
|
15: \u_spi_slave.rx_valid
|
|
|
|
Output signals:
|
|
0: $flatten\u_spi_engine.$procmux$4155_CMP
|
|
1: $flatten\u_spi_engine.$procmux$3992_CMP
|
|
2: $flatten\u_spi_engine.$procmux$3989_CMP
|
|
3: $flatten\u_spi_engine.$procmux$3971_CMP
|
|
4: $flatten\u_spi_engine.$procmux$3951_CMP
|
|
5: $flatten\u_spi_engine.$procmux$3842_CMP
|
|
6: $flatten\u_spi_engine.$procmux$3792_CMP
|
|
7: $flatten\u_spi_engine.$procmux$3791_CMP
|
|
8: $flatten\u_spi_engine.$procmux$3741_CMP
|
|
9: $flatten\u_spi_engine.$procmux$3710_CMP
|
|
10: $flatten\u_spi_engine.$procmux$3677_CMP
|
|
11: $flatten\u_spi_engine.$procmux$3668_CMP
|
|
12: $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:236$767_Y
|
|
|
|
State encoding:
|
|
0: 14'-------------1 <RESET STATE>
|
|
1: 14'------------1-
|
|
2: 14'-----------1--
|
|
3: 14'----------1---
|
|
4: 14'---------1----
|
|
5: 14'--------1-----
|
|
6: 14'-------1------
|
|
7: 14'------1-------
|
|
8: 14'-----1--------
|
|
9: 14'----1---------
|
|
10: 14'---1----------
|
|
11: 14'--1-----------
|
|
12: 14'-1------------
|
|
13: 14'1-------------
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 16'00------------0- -> 0 13'0000100000000
|
|
1: 0 16'-1------------0- -> 0 13'0000100000000
|
|
2: 0 16'--------------1- -> 0 13'0000100000000
|
|
3: 0 16'10---------1--0- -> 3 13'0000100000000
|
|
4: 0 16'10-------1----0- -> 4 13'0000100000000
|
|
5: 0 16'10------------01 -> 5 13'0000100000000
|
|
6: 0 16'10----------1-0- -> 7 13'0000100000000
|
|
7: 0 16'10--------1---0- -> 10 13'0000100000000
|
|
8: 0 16'10-------0000-00 -> 12 13'0000100000000
|
|
9: 1 16'-1------------0- -> 0 13'0000000010000
|
|
10: 1 16'--------------1- -> 0 13'0000000010000
|
|
11: 1 16'-0-----------00- -> 1 13'0000000010000
|
|
12: 1 16'-0-----------10- -> 8 13'0000000010000
|
|
13: 2 16'-1------------0- -> 0 13'0000000001000
|
|
14: 2 16'--------------1- -> 0 13'0000000001000
|
|
15: 2 16'00------------0- -> 2 13'0000000001000
|
|
16: 2 16'10------------0- -> 9 13'0000000001000
|
|
17: 3 16'-1------------0- -> 0 13'0000000100000
|
|
18: 3 16'--------------1- -> 0 13'0000000100000
|
|
19: 3 16'00------------0- -> 3 13'0000000100000
|
|
20: 3 16'10------------0- -> 12 13'0000000100000
|
|
21: 4 16'-1------------0- -> 0 13'0010000000000
|
|
22: 4 16'--------------1- -> 0 13'0010000000000
|
|
23: 4 16'100-----------0- -> 4 13'0010000000000
|
|
24: 4 16'00------------0- -> 4 13'0010000000000
|
|
25: 4 16'1010----------0- -> 11 13'0010000000000
|
|
26: 4 16'1011----------0- -> 12 13'0010000000000
|
|
27: 5 16'-1------------0- -> 0 13'1000000000000
|
|
28: 5 16'--------------1- -> 0 13'1000000000000
|
|
29: 5 16'10------0-----0- -> 5 13'1000000000000
|
|
30: 5 16'00------------0- -> 5 13'1000000000000
|
|
31: 5 16'10------1-----0- -> 12 13'1000000000000
|
|
32: 6 16'-1------------0- -> 0 13'0000000000010
|
|
33: 6 16'--------------1- -> 0 13'0000000000010
|
|
34: 6 16'-0-----0-----10- -> 2 13'0000000000010
|
|
35: 6 16'-0-----------00- -> 6 13'0000000000010
|
|
36: 6 16'-0-----1-----10- -> 12 13'0000000000010
|
|
37: 7 16'-1------------0- -> 0 13'0001000000000
|
|
38: 7 16'--------------1- -> 0 13'0001000000000
|
|
39: 7 16'10------------0- -> 4 13'0001000000000
|
|
40: 7 16'00------------0- -> 7 13'0001000000000
|
|
41: 8 16'-1------------0- -> 0 13'0000000000100
|
|
42: 8 16'--------------1- -> 0 13'0000000000100
|
|
43: 8 16'00------------0- -> 8 13'0000000000100
|
|
44: 8 16'10-----1------0- -> 12 13'0000000000100
|
|
45: 8 16'10-----0------0- -> 13 13'0000000000100
|
|
46: 9 16'-1------------0- -> 0 13'0000001000000
|
|
47: 9 16'--------------1- -> 0 13'0000001000000
|
|
48: 9 16'-0------------0- -> 6 13'0000001000000
|
|
49: 10 16'-1------------0- -> 0 13'0000000000001
|
|
50: 10 16'--------------1- -> 0 13'0000000000001
|
|
51: 10 16'00------------0- -> 10 13'0000000000001
|
|
52: 10 16'10------------0- -> 12 13'0000000000001
|
|
53: 11 16'-1------------0- -> 0 13'0100000000000
|
|
54: 11 16'--------------1- -> 0 13'0100000000000
|
|
55: 11 16'10--101-------0- -> 2 13'0100000000000
|
|
56: 11 16'10--0---------0- -> 11 13'0100000000000
|
|
57: 11 16'00------------0- -> 11 13'0100000000000
|
|
58: 11 16'10--11--------0- -> 12 13'0100000000000
|
|
59: 11 16'10--100-------0- -> 13 13'0100000000000
|
|
60: 12 16'-1------------0- -> 0 13'0000000000000
|
|
61: 12 16'--------------1- -> 0 13'0000000000000
|
|
62: 12 16'-0------------0- -> 12 13'0000000000000
|
|
63: 13 16'-1------------0- -> 0 13'0000010000000
|
|
64: 13 16'--------------1- -> 0 13'0000010000000
|
|
65: 13 16'-0------------0- -> 1 13'0000010000000
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_int8_access.state$5733' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_int8_access.state$5733 (\u_int8_access.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \u_memory_if.ready
|
|
2: \u_arbiter.m_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_int8_access.$procmux$4991_CMP
|
|
1: $flatten\u_int8_access.$procmux$4983_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'10
|
|
1: 0 3'--1 -> 0 2'10
|
|
2: 0 3'1-0 -> 1 2'10
|
|
3: 1 3'-10 -> 0 2'01
|
|
4: 1 3'--1 -> 0 2'01
|
|
5: 1 3'-00 -> 1 2'01
|
|
|
|
-------------------------------------
|
|
|
|
FSM `$fsm$\u_memory_if.state$5737' from module `spi_neuron_top':
|
|
-------------------------------------
|
|
|
|
Information on FSM $fsm$\u_memory_if.state$5737 (\u_memory_if.state):
|
|
|
|
Number of input signals: 3
|
|
Number of output signals: 2
|
|
Number of state bits: 2
|
|
|
|
Input signals:
|
|
0: \rst
|
|
1: \u_psram_ctrl.mem_ready
|
|
2: \u_int8_access.mem_req
|
|
|
|
Output signals:
|
|
0: $flatten\u_memory_if.$procmux$1616_CMP
|
|
1: $flatten\u_memory_if.$procmux$1608_CMP
|
|
|
|
State encoding:
|
|
0: 2'-1 <RESET STATE>
|
|
1: 2'1-
|
|
|
|
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
|
|
0: 0 3'0-0 -> 0 2'10
|
|
1: 0 3'--1 -> 0 2'10
|
|
2: 0 3'1-0 -> 1 2'10
|
|
3: 1 3'-10 -> 0 2'01
|
|
4: 1 3'--1 -> 0 2'01
|
|
5: 1 3'-00 -> 1 2'01
|
|
|
|
-------------------------------------
|
|
|
|
17.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
Mapping FSM `$fsm$\u_psram_ctrl.state$5741' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_graph_engine.state$5748' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_neuron_memory.state$5688' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_layer_sequencer.state$5696' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_neuron_memory.u_mem.state$5705' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_arbiter.owner$5709' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_spi_engine.resp_len$5715' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_spi_engine.state$5717' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_int8_access.state$5733' from module `\spi_neuron_top'.
|
|
Mapping FSM `$fsm$\u_memory_if.state$5737' from module `\spi_neuron_top'.
|
|
|
|
17.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~71 debug messages>
|
|
|
|
17.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1786 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1724 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1716 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1714 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~216 debug messages>
|
|
Removed a total of 72 cells.
|
|
|
|
17.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~1112 debug messages>
|
|
|
|
17.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1714 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5542 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4999_Y, Q = \u_int8_access.addr_reg, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6493 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_addr, Q = \u_int8_access.addr_reg).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5503 ($dff) from module spi_neuron_top (D = { $flatten\u_spi_engine.$procmux$3679_Y $flatten\u_spi_engine.$procmux$3712_Y }, Q = \u_spi_engine.len_acc, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6497 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3697_Y, Q = \u_spi_engine.len_acc [7:0]).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6497 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3667_Y, Q = \u_spi_engine.len_acc [15:8]).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5502 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4082_Y, Q = \u_spi_engine.addr_acc, rval = 24'000000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6528 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4062_Y, Q = \u_spi_engine.addr_acc).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5501 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4115_Y, Q = \u_spi_engine.byte_pos, rval = 2'00).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6544 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4103_Y, Q = \u_spi_engine.byte_pos).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5500 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4139_Y, Q = \u_spi_engine.opcode, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6558 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.opcode).
|
|
Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5468 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3509_Y, Q = \u_layer_sequencer.num_layers_reg, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6564 ($sdff) from module spi_neuron_top (D = \u_spi_engine.run_num_layers, Q = \u_layer_sequencer.num_layers_reg).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5498 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4246_Y, Q = \u_spi_engine.n_out, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6568 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_out).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5497 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4277_Y, Q = \u_spi_engine.num_neurons_graph, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6574 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.num_neurons_graph).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5532 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4736_Y, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5531 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4849_Y, Q = \u_psram_ctrl.dq_out, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6581 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_wdata, Q = \u_psram_ctrl.dq_out).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5530 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4855_Y, Q = \u_psram_ctrl.ub_reg, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6585 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4855_Y, Q = \u_psram_ctrl.ub_reg).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5529 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4867_Y, Q = \u_psram_ctrl.lb_reg, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6593 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4867_Y, Q = \u_psram_ctrl.lb_reg).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5525 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4912_Y, Q = \u_psram_ctrl.counter, rval = 14'00000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6601 ($sdff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4912_Y, Q = \u_psram_ctrl.counter).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5523 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4757_Y, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5522 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4771_Y, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5521 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4788_Y, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5520 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4805_Y, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5519 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4818_Y, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5518 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4938_Y, Q = \u_psram_ctrl.psram_a, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6614 ($sdff) from module spi_neuron_top (D = \u_memory_if.mem_addr, Q = \u_psram_ctrl.psram_a).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5517 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4831_Y, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_psram_ctrl.$procdff$5516 ($dff) from module spi_neuron_top (D = $flatten\u_psram_ctrl.$procmux$4949_Y, Q = \u_psram_ctrl.mem_rdata, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6619 ($sdff) from module spi_neuron_top (D = \psram_dq, Q = \u_psram_ctrl.mem_rdata).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5496 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4300_Y, Q = \u_spi_engine.net_type, rval = 8'00000001).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6623 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4287_Y, Q = \u_spi_engine.net_type).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5495 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4316_Y, Q = \u_spi_engine.run_num_layers, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6637 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.run_num_layers).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5494 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3769_Y, Q = \u_spi_engine.run_start, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5493 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4351_Y, Q = \u_spi_engine.buf_b_base, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6652 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_b_base).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5492 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4387_Y, Q = \u_spi_engine.buf_a_base, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6658 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.buf_a_base).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5491 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4424_Y, Q = \u_spi_engine.table_base, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6664 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.table_base).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5490 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3736_Y, Q = \u_spi_engine.nm_soft_rst, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5489 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3769_Y, Q = \u_spi_engine.nm_start, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5488 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4456_Y, Q = \u_spi_engine.n_neurons_real, rval = 16'0000000000000001).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6686 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_neurons_real).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5487 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4489_Y, Q = \u_spi_engine.n_inputs_real, rval = 16'0000000000100000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6692 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [7:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.n_inputs_real).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5486 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4523_Y, Q = \u_spi_engine.activation, rval = 2'01).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6698 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte [1:0], Q = \u_spi_engine.activation).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5485 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4561_Y, Q = \u_spi_engine.bias_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6704 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.bias_addr).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5484 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4600_Y, Q = \u_spi_engine.w_base, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6710 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.w_base).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5483 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4640_Y, Q = \u_spi_engine.x_base, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6716 ($sdff) from module spi_neuron_top (D = { \u_spi_engine.addr_acc [14:0] \u_spi_slave.rx_byte }, Q = \u_spi_engine.x_base).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5482 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4657_Y, Q = \u_spi_engine.ram_wdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6722 ($sdff) from module spi_neuron_top (D = \u_spi_engine.pending_wdata, Q = \u_spi_engine.ram_wdata).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5481 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4673_Y, Q = \u_spi_engine.ram_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6728 ($sdff) from module spi_neuron_top (D = \u_spi_engine.cur_addr, Q = \u_spi_engine.ram_addr).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5480 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4689_Y, Q = \u_spi_engine.ram_wr, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6734 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4685_Y, Q = \u_spi_engine.ram_wr).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5479 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3790_Y, Q = \u_spi_engine.ram_req, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5320 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1624_Y, Q = \u_memory_if.mem_ub_n, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6745 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_ub_n, Q = \u_memory_if.mem_ub_n).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5319 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1633_Y, Q = \u_memory_if.mem_lb_n, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6749 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_lb_n, Q = \u_memory_if.mem_lb_n).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5318 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1613_Y, Q = \u_memory_if.ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5317 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1643_Y, Q = \u_memory_if.rdata, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6758 ($sdff) from module spi_neuron_top (D = \u_psram_ctrl.mem_rdata, Q = \u_memory_if.rdata).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5316 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1652_Y, Q = \u_memory_if.mem_wdata, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6764 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wdata, Q = \u_memory_if.mem_wdata).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5315 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1661_Y, Q = \u_memory_if.mem_addr, rval = 23'00000000000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6768 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_addr, Q = \u_memory_if.mem_addr).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5314 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1670_Y, Q = \u_memory_if.mem_wr, rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6772 ($sdff) from module spi_neuron_top (D = \u_int8_access.mem_wr, Q = \u_memory_if.mem_wr).
|
|
Adding SRST signal on $flatten\u_memory_if.$procdff$5313 ($dff) from module spi_neuron_top (D = $flatten\u_memory_if.$procmux$1605_Y, Q = \u_memory_if.mem_req, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5541 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5005_Y, Q = \u_int8_access.mem_ub_n, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6781 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5005_Y, Q = \u_int8_access.mem_ub_n).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5540 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5017_Y, Q = \u_int8_access.mem_lb_n, rval = 1'1).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6789 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5017_Y, Q = \u_int8_access.mem_lb_n).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5539 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4988_Y, Q = \u_int8_access.ready, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5538 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5034_Y, Q = \u_int8_access.rdata, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6802 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5030_Y, Q = \u_int8_access.rdata).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5537 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5046_Y, Q = \u_int8_access.mem_wdata, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$6806 ($sdff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5042_Y, Q = \u_int8_access.mem_wdata).
|
|
Adding SRST signal on $flatten\u_int8_access.$procdff$5536 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5055_Y, Q = \u_int8_access.mem_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6810 ($sdff) from module spi_neuron_top (D = { 1'0 \u_arbiter.m_addr [22:1] }, Q = \u_int8_access.mem_addr).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5535 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$5064_Y, Q = \u_int8_access.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6814 ($sdff) from module spi_neuron_top (D = \u_arbiter.m_wr, Q = \u_int8_access.mem_wr).
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Adding SRST signal on $flatten\u_int8_access.$procdff$5534 ($dff) from module spi_neuron_top (D = $flatten\u_int8_access.$procmux$4980_Y, Q = \u_int8_access.mem_req, rval = 1'0).
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|
Adding SRST signal on $flatten\u_arbiter.$procdff$5330 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1759_Y, Q = \u_arbiter.m_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6823 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1757_Y, Q = \u_arbiter.m_wdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5329 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1775_Y, Q = \u_arbiter.m_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6829 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1773_Y, Q = \u_arbiter.m_addr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5328 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1791_Y, Q = \u_arbiter.m_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6835 ($sdff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1789_Y, Q = \u_arbiter.m_wr).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5327 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1719_Y, Q = \u_arbiter.m_req, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5326 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1686_Y, Q = \u_arbiter.c_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5325 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1798_Y, Q = \u_arbiter.c_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6851 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.c_rdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5324 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1686_Y, Q = \u_arbiter.b_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5323 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1806_Y, Q = \u_arbiter.b_rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6860 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.b_rdata).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5322 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1686_Y, Q = \u_arbiter.a_ready, rval = 1'0).
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Adding SRST signal on $flatten\u_arbiter.$procdff$5321 ($dff) from module spi_neuron_top (D = $flatten\u_arbiter.$procmux$1815_Y, Q = \u_arbiter.a_rdata, rval = 8'00000000).
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|
Adding EN signal on $auto$ff.cc:337:slice$6869 ($sdff) from module spi_neuron_top (D = \u_int8_access.rdata, Q = \u_arbiter.a_rdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5547 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5155_Y, Q = \u_neuron_memory.u_neuron.y, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6873 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5150_Y, Q = \u_neuron_memory.u_neuron.y).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5548 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5143_Y, Q = \u_neuron_memory.u_neuron.busy, rval = 1'0).
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|
Adding EN signal on $auto$ff.cc:337:slice$6879 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5143_Y, Q = \u_neuron_memory.u_neuron.busy).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5549 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5090_Y, Q = \u_neuron_memory.u_neuron.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5550 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5131_Y, Q = \u_neuron_memory.u_neuron.group_index, rval = 4'0000).
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|
Adding EN signal on $auto$ff.cc:337:slice$6886 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358_Y, Q = \u_neuron_memory.u_neuron.group_index).
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|
Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5551 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5117_Y, Q = \u_neuron_memory.u_neuron.acc, rval = 0).
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|
Adding EN signal on $auto$ff.cc:337:slice$6896 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.acc_next, Q = \u_neuron_memory.u_neuron.acc).
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Adding SRST signal on $flatten\u_neuron_memory.\u_neuron.$procdff$5552 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_neuron.$procmux$5099_Y, Q = \u_neuron_memory.u_neuron.finishing, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5534 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4980_Y, Q = \u_neuron_memory.u_mem.mem_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5535 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5064_Y, Q = \u_neuron_memory.u_mem.mem_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6914 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_wr, Q = \u_neuron_memory.u_mem.mem_wr).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5538 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5034_Y, Q = \u_neuron_memory.u_mem.rdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6918 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$5030_Y, Q = \u_neuron_memory.u_mem.rdata).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5539 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4988_Y, Q = \u_neuron_memory.u_mem.ready, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5553 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5292_Y, Q = \u_spi_slave.miso, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$6927 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5292_Y, Q = \u_spi_slave.miso).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5554 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5273_Y, Q = \u_spi_slave.rx_byte, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6939 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_byte).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5555 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5196_Y, Q = \u_spi_slave.rx_valid, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5558 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5161_Y, Q = \u_spi_slave.cs_end, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5559 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5253_Y, Q = \u_spi_slave.bit_count, rval = 3'000).
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Adding EN signal on $auto$ff.cc:337:slice$6957 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5246_Y, Q = \u_spi_slave.bit_count).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5560 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5239_Y, Q = \u_spi_slave.rx_shift, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6967 ($sdff) from module spi_neuron_top (D = { \u_spi_slave.rx_shift [6:0] \u_spi_slave.mosi_sync [2] }, Q = \u_spi_slave.rx_shift).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5561 ($dff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5225_Y, Q = \u_spi_slave.tx_shift, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$6977 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_slave.$procmux$5225_Y, Q = \u_spi_slave.tx_shift).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5562 ($dff) from module spi_neuron_top (D = \u_spi_slave.sclk_sync [2], Q = \u_spi_slave.sclk_prev, rval = 1'0).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5563 ($dff) from module spi_neuron_top (D = \u_spi_slave.cs_n_sync [2], Q = \u_spi_slave.cs_n_prev, rval = 1'1).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5564 ($dff) from module spi_neuron_top (D = { \u_spi_slave.sclk_sync [1:0] \sclk }, Q = \u_spi_slave.sclk_sync, rval = 3'000).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5565 ($dff) from module spi_neuron_top (D = { \u_spi_slave.mosi_sync [1:0] \mosi }, Q = \u_spi_slave.mosi_sync, rval = 3'000).
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Adding EN signal on $flatten\u_neuron_memory.$procdff$5344 ($dff) from module spi_neuron_top (D = 8'00000000, Q = \u_neuron_memory.access_wdata).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5343 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2086_Y, Q = \u_neuron_memory.access_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$6994 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2086_Y, Q = \u_neuron_memory.access_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5342 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2115_Y, Q = \u_neuron_memory.access_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7010 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2115_Y, Q = \u_neuron_memory.access_wr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5341 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2029_Y, Q = \u_neuron_memory.access_req, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5340 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2144_Y, Q = \u_neuron_memory.bias_group_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7027 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2144_Y, Q = \u_neuron_memory.bias_group_addr).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5339 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2159_Y, Q = \u_neuron_memory.w_group_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7039 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2159_Y, Q = \u_neuron_memory.w_group_base).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5338 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2174_Y, Q = \u_neuron_memory.neuron_index, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7051 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2174_Y, Q = \u_neuron_memory.neuron_index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5337 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2189_Y, Q = \u_neuron_memory.index, rval = 6'000000).
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Adding EN signal on $auto$ff.cc:337:slice$7063 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2189_Y, Q = \u_neuron_memory.index).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5336 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2216_Y, Q = \u_neuron_memory.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7081 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.bias_reg).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5335 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2017_Y, Q = \u_neuron_memory.neuron_start, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5334 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2000_Y, Q = \u_neuron_memory.done, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.$procdff$5333 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2228_Y, Q = \u_neuron_memory.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7093 ($sdff) from module spi_neuron_top (D = $flatten\u_neuron_memory.$procmux$2228_Y, Q = \u_neuron_memory.busy).
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Adding SRST signal on $flatten\u_spi_slave.$procdff$5566 ($dff) from module spi_neuron_top (D = { \u_spi_slave.cs_n_sync [1:0] \cs_n }, Q = \u_spi_slave.cs_n_sync, rval = 3'111).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5467 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3523_Y, Q = \u_layer_sequencer.layer_idx, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7104 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3523_Y, Q = \u_layer_sequencer.layer_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5459 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3449_Y, Q = \u_layer_sequencer.seq_done, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5458 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3623_Y, Q = \u_layer_sequencer.seq_busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7127 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3623_Y, Q = \u_layer_sequencer.seq_busy).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5511 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3885_Y, Q = \u_spi_engine.net_mode, rval = 1'0).
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Adding SRST signal on $flatten\u_neuron_memory.\u_mem.$procdff$5542 ($dff) from module spi_neuron_top (D = $flatten\u_neuron_memory.\u_mem.$procmux$4999_Y, Q = \u_neuron_memory.u_mem.addr_reg, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7142 ($sdff) from module spi_neuron_top (D = \u_neuron_memory.access_addr, Q = \u_neuron_memory.u_mem.addr_reg).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5547 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5155_Y, Q = \u_graph_engine.u_neuron.y, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7146 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5150_Y, Q = \u_graph_engine.u_neuron.y).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5548 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5143_Y, Q = \u_graph_engine.u_neuron.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7152 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5143_Y, Q = \u_graph_engine.u_neuron.busy).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5549 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5090_Y, Q = \u_graph_engine.u_neuron.done, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5550 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5131_Y, Q = \u_graph_engine.u_neuron.group_index, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7159 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358_Y, Q = \u_graph_engine.u_neuron.group_index).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5551 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5117_Y, Q = \u_graph_engine.u_neuron.acc, rval = 0).
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Adding EN signal on $auto$ff.cc:337:slice$7169 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.acc_next, Q = \u_graph_engine.u_neuron.acc).
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Adding SRST signal on $flatten\u_graph_engine.\u_neuron.$procdff$5552 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.\u_neuron.$procmux$5099_Y, Q = \u_graph_engine.u_neuron.finishing, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5381 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2725_Y, Q = \u_graph_engine.n_conn_padded_reg, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7182 ($sdff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040_Y [15:1] 1'0 }, Q = \u_graph_engine.n_conn_padded_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5380 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2743_Y, Q = \u_graph_engine.activation_reg, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$7186 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata [1:0], Q = \u_graph_engine.activation_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5379 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2760_Y, Q = \u_graph_engine.bias_reg, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7190 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.bias_reg).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5378 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2656_Y, Q = \u_graph_engine.neuron_start, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5377 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2770_Y, Q = \u_graph_engine.act_wr_data, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7195 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2770_Y, Q = \u_graph_engine.act_wr_data).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5376 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2783_Y, Q = \u_graph_engine.act_wr_addr, rval = 12'000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7205 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2783_Y, Q = \u_graph_engine.act_wr_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5375 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2666_Y, Q = \u_graph_engine.act_wr_en, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5374 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2801_Y, Q = \u_graph_engine.weight_acc, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7216 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.weight_acc).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5373 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2285_Y $flatten\u_graph_engine.$procmux$2301_Y }, Q = \u_graph_engine.src_id_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7220 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [7:0]).
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Adding EN signal on $auto$ff.cc:337:slice$7220 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.src_id_acc [15:8]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5372 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2837_Y, Q = \u_graph_engine.edge_byte_idx, rval = 2'00).
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Adding EN signal on $auto$ff.cc:337:slice$7227 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2837_Y, Q = \u_graph_engine.edge_byte_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5371 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2856_Y, Q = \u_graph_engine.conn_i, rval = 6'000000).
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Adding EN signal on $auto$ff.cc:337:slice$7239 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2856_Y, Q = \u_graph_engine.conn_i).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5370 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2821_Y $flatten\u_graph_engine.$procmux$2320_Y }, Q = \u_graph_engine.out_id_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7249 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7249 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.out_id_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5369 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2884_Y $flatten\u_graph_engine.$procmux$2341_Y }, Q = \u_graph_engine.n_conn_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7256 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7256 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.n_conn_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5368 ($dff) from module spi_neuron_top (D = { $flatten\u_graph_engine.$procmux$2389_Y $flatten\u_graph_engine.$procmux$2908_Y $flatten\u_graph_engine.$procmux$2364_Y }, Q = \u_graph_engine.conn_ptr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7263 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7263 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7263 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_graph_engine.conn_ptr_acc [7:0]).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5367 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2929_Y, Q = \u_graph_engine.desc_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7273 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2929_Y, Q = \u_graph_engine.desc_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5366 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2952_Y, Q = \u_graph_engine.neuron_idx, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7287 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2952_Y, Q = \u_graph_engine.neuron_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5365 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2984_Y, Q = \u_graph_engine.in_idx, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7301 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2984_Y, Q = \u_graph_engine.in_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5364 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3006_Y, Q = \u_graph_engine.err, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7313 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3006_Y, Q = \u_graph_engine.err).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5363 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2680_Y, Q = \u_graph_engine.done, rval = 1'0).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5362 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3024_Y, Q = \u_graph_engine.busy, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7330 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3024_Y, Q = \u_graph_engine.busy).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5361 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3060_Y, Q = \u_graph_engine.desc_byte_idx, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7352 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3060_Y, Q = \u_graph_engine.desc_byte_idx).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5359 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3144_Y, Q = \u_graph_engine.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7372 ($sdff) from module spi_neuron_top (D = \u_graph_engine.u_neuron.y, Q = \u_graph_engine.ram_wdata).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5358 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3151_Y, Q = \u_graph_engine.ram_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7374 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3151_Y, Q = \u_graph_engine.ram_addr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5357 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3164_Y, Q = \u_graph_engine.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7382 ($sdff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3164_Y, Q = \u_graph_engine.ram_wr).
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Adding SRST signal on $flatten\u_graph_engine.$procdff$5356 ($dff) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2641_Y, Q = \u_graph_engine.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5457 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3318_Y, Q = \u_layer_sequencer.nm_start, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5456 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3633_Y, Q = \u_layer_sequencer.ram_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7392 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$809_Y, Q = \u_layer_sequencer.ram_wdata).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5455 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3640_Y, Q = \u_layer_sequencer.ram_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7394 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3640_Y, Q = \u_layer_sequencer.ram_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5454 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3648_Y, Q = \u_layer_sequencer.ram_wr, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7398 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3648_Y, Q = \u_layer_sequencer.ram_wr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5453 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3308_Y, Q = \u_layer_sequencer.ram_req, rval = 1'0).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5469 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3492_Y, Q = \u_layer_sequencer.desc_table_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7403 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3492_Y, Q = \u_layer_sequencer.desc_table_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5470 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3469_Y, Q = \u_layer_sequencer.desc_byte_idx, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7417 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3469_Y, Q = \u_layer_sequencer.desc_byte_idx).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5509 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3937_Y, Q = \u_spi_engine.resp_index, rval = 4'0000).
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Adding EN signal on $auto$ff.cc:337:slice$7433 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3926_Y, Q = \u_spi_engine.resp_index).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5471 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3301_Y $flatten\u_layer_sequencer.$procmux$3441_Y $flatten\u_layer_sequencer.$procmux$3277_Y }, Q = \u_layer_sequencer.w_base_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7449 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7449 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7449 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.w_base_acc [7:0]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5508 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3953_Y, Q = \u_spi_engine.cur_read_byte, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7459 ($sdff) from module spi_neuron_top (D = \u_arbiter.a_rdata, Q = \u_spi_engine.cur_read_byte).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5507 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3973_Y, Q = \u_spi_engine.pending_wdata, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7465 ($sdff) from module spi_neuron_top (D = \u_spi_slave.rx_byte, Q = \u_spi_engine.pending_wdata).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5472 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3255_Y $flatten\u_layer_sequencer.$procmux$3400_Y $flatten\u_layer_sequencer.$procmux$3234_Y }, Q = \u_layer_sequencer.bias_addr_acc, rval = 24'000000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7471 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7471 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [23:16]).
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Adding EN signal on $auto$ff.cc:337:slice$7471 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.bias_addr_acc [7:0]).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5505 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4003_Y, Q = \u_spi_engine.cur_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7481 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3988_Y, Q = \u_spi_engine.cur_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5473 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3418_Y, Q = \u_layer_sequencer.activation_acc, rval = 8'00000000).
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Adding EN signal on $auto$ff.cc:337:slice$7499 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.activation_acc).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5474 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3380_Y $flatten\u_layer_sequencer.$procmux$3215_Y }, Q = \u_layer_sequencer.n_inputs_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7503 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7503 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_inputs_acc [7:0]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5475 ($dff) from module spi_neuron_top (D = { $flatten\u_layer_sequencer.$procmux$3185_Y $flatten\u_layer_sequencer.$procmux$3199_Y }, Q = \u_layer_sequencer.n_neurons_acc, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7510 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [15:8]).
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Adding EN signal on $auto$ff.cc:337:slice$7510 ($sdff) from module spi_neuron_top (D = \u_arbiter.c_rdata, Q = \u_layer_sequencer.n_neurons_acc [7:0]).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5476 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3363_Y, Q = \u_layer_sequencer.cur_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7517 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.write_sel, Q = \u_layer_sequencer.cur_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5477 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3346_Y, Q = \u_layer_sequencer.write_sel, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7523 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3346_Y, Q = \u_layer_sequencer.write_sel).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5478 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3329_Y, Q = \u_layer_sequencer.copy_idx, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7537 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3329_Y, Q = \u_layer_sequencer.copy_idx).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5461 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3580_Y, Q = \u_layer_sequencer.nm_x_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7549 ($sdff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:259$804_Y, Q = \u_layer_sequencer.nm_x_base).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5462 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3571_Y, Q = \u_layer_sequencer.nm_w_base, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7551 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.w_base_acc [22:0], Q = \u_layer_sequencer.nm_w_base).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5463 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3562_Y, Q = \u_layer_sequencer.nm_bias_addr, rval = 23'00000000000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7553 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.bias_addr_acc [22:0], Q = \u_layer_sequencer.nm_bias_addr).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5464 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3553_Y, Q = \u_layer_sequencer.nm_activation, rval = 2'01).
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Adding EN signal on $auto$ff.cc:337:slice$7555 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.activation_acc [1:0], Q = \u_layer_sequencer.nm_activation).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5465 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3544_Y, Q = \u_layer_sequencer.nm_n_inputs, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7557 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_inputs_acc, Q = \u_layer_sequencer.nm_n_inputs).
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Adding SRST signal on $flatten\u_layer_sequencer.$procdff$5466 ($dff) from module spi_neuron_top (D = $flatten\u_layer_sequencer.$procmux$3535_Y, Q = \u_layer_sequencer.nm_n_neurons, rval = 16'0000000000000000).
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Adding EN signal on $auto$ff.cc:337:slice$7559 ($sdff) from module spi_neuron_top (D = \u_layer_sequencer.n_neurons_acc, Q = \u_layer_sequencer.nm_n_neurons).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5514 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4726_Y, Q = \u_spi_engine.status_done_sticky, rval = 1'0).
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Adding EN signal on $auto$ff.cc:337:slice$7561 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4726_Y, Q = \u_spi_engine.status_done_sticky).
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Adding SRST signal on $flatten\u_spi_engine.$procdff$5513 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3823_Y, Q = \u_spi_engine.status_snapshot, rval = 8'00000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7567 ($sdff) from module spi_neuron_top (D = { 5'00000 \u_graph_engine.err \u_spi_engine.status_done_sticky \u_spi_engine.busy_all }, Q = \u_spi_engine.status_snapshot).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5512 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$3854_Y, Q = \u_spi_engine.graph_mode, rval = 1'0).
|
|
Adding SRST signal on $flatten\u_spi_engine.$procdff$5504 ($dff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4027_Y, Q = \u_spi_engine.len_remaining, rval = 16'0000000000000000).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7574 ($sdff) from module spi_neuron_top (D = $flatten\u_spi_engine.$procmux$4015_Y, Q = \u_spi_engine.len_remaining).
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$7568 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$7568 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$7568 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$7568 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$7568 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7183 ($sdffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$6993 ($dffe) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6811 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 489 unused cells and 639 unused wires.
|
|
<suppressed ~490 debug messages>
|
|
|
|
17.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~48 debug messages>
|
|
|
|
17.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~539 debug messages>
|
|
|
|
17.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1637 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1491 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1479 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~474 debug messages>
|
|
Removed a total of 158 cells.
|
|
|
|
17.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 2 on $flatten\u_spi_engine.$procdff$5510 ($dff) from module spi_neuron_top.
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6769 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 158 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~548 debug messages>
|
|
|
|
17.14.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1479 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.14.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Setting constant 0-bit at position 22 on $auto$ff.cc:337:slice$6615 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.14.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.14.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.14.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~548 debug messages>
|
|
|
|
17.14.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.14.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1479 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.14.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.14.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.14.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.14.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1067 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1068 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1069 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1070 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1071 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1072 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1073 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1074 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1075 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1076 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1077 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1078 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1079 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1080 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1081 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1082 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1083 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1084 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1085 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1086 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1087 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1088 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1089 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1090 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1091 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1092 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1093 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1094 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1095 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1096 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1097 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1098 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1099 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1100 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1101 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1102 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1103 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1104 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1105 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1106 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1107 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1108 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1109 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1110 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1111 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1112 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1113 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1114 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1115 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1116 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1117 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1118 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1119 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1120 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1121 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1122 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1123 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1124 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1125 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1126 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1127 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1128 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:214$1129 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_graph_engine.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:215$1130 (u_graph_engine.w_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5635 (u_graph_engine.x_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5636 (u_graph_engine.w_mem).
|
|
Removed top 28 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_spi_engine.$auto$mem.cc:351:emit$1602 ($flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5571 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5572 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5573 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5574 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5575 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5576 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5577 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5578 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5579 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5580 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5581 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5582 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5583 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5584 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5585 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5586 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5587 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5588 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5589 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5590 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5591 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5592 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5593 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5594 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5595 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5596 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5597 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5598 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5599 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5600 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5601 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5602 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5603 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5604 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5605 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5606 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5607 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5608 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5609 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5610 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5611 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5612 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5613 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5614 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5615 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5616 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5617 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5618 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5619 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5620 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5621 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5622 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5623 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5624 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5625 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5626 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5627 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5628 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5629 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5630 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5631 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5632 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5633 (u_graph_engine.x_mem).
|
|
Removed top 27 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_graph_engine.$auto$proc_memwr.cc:45:proc_memwr$5634 (u_graph_engine.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1191 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1192 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1193 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1194 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1195 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1196 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1197 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1198 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1199 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1200 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1201 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1202 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1203 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1204 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1205 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1206 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1207 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1208 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1209 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1210 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1211 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1212 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1213 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1214 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1215 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1216 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1217 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1218 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1219 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1220 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1221 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1222 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1223 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1224 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1225 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1226 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1227 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1228 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1229 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1230 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1231 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1232 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1233 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1234 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1235 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1236 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1237 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1238 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1239 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1240 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1241 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1242 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1243 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1244 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1245 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1246 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1247 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1248 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1249 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1250 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1251 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1252 (u_neuron_memory.w_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:129$1253 (u_neuron_memory.x_mem).
|
|
Removed top 27 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:130$1254 (u_neuron_memory.w_mem).
|
|
Removed top 32 address bits (of 32) from memory read port spi_neuron_top.$flatten\u_neuron_memory.$memrd$\y_reg$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:140$1255 (u_neuron_memory.y_reg).
|
|
Removed top 32 address bits (of 32) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5567 (u_neuron_memory.y_reg).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5568 (u_neuron_memory.x_mem).
|
|
Removed top 1 address bits (of 6) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5569 (u_neuron_memory.w_mem).
|
|
Removed top 1 address bits (of 1) from memory init port spi_neuron_top.$flatten\u_neuron_memory.$auto$proc_memwr.cc:45:proc_memwr$5570 (u_neuron_memory.y_reg).
|
|
Removed top 1 bits (of 3) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7593 ($dff).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7585 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7583 ($ne).
|
|
Removed top 6 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7500 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7475 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7453 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7444 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7278 ($ne).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7267 ($sdffe).
|
|
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7143 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7017 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$7015 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6980 ($ne).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6978 ($sdffe).
|
|
Removed top 1 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6968 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6784 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6632 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6590 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6539 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6535 ($ne).
|
|
Removed top 8 bits (of 24) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6529 ($sdffe).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6508 ($ne).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$opt_dff.cc:320:make_patterns_logic$6502 ($ne).
|
|
Removed top 22 bits (of 23) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6494 ($sdffe).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6406 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6367 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6297 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6266 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6138 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6066 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$6061 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5988 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5963 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5926 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5918 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5914 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5901 ($eq).
|
|
Removed top 1 bits (of 3) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5887 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5881 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$auto$fsm_map.cc:77:implement_pattern_cache$5826 ($eq).
|
|
Removed top 15 bits (of 16) from mux cell spi_neuron_top.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v:324$631 ($mux).
|
|
Removed top 11 bits (of 14) from port B of cell spi_neuron_top.$flatten\u_psram_ctrl.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:292$1263 ($eq).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$1336 ($shiftx).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$1340 ($shiftx).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341 ($add).
|
|
Converting cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2074 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2065 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$2056 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1992 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1962 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1935 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1876 ($mux).
|
|
Removed cell spi_neuron_top.$flatten\u_neuron_memory.$procmux$1840 ($mux).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$1336 ($shiftx).
|
|
Removed top 23 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$1340 ($shiftx).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341 ($add).
|
|
Converting cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add) from unsigned to signed.
|
|
Removed top 16 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 16 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 15 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2905_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2881_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2818_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2740_CMP0 ($eq).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2701 ($mux).
|
|
Removed top 1 bits (of 6) from mux cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2409 ($mux).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2361_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2338_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2317_CMP0 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$procmux$2298_CMP0 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1060 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1058 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1054 ($add).
|
|
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1052 ($ge).
|
|
Removed top 3 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1050 ($ge).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047 ($add).
|
|
Removed top 9 bits (of 32) from port A of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047 ($add).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1046 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1046 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1043 ($add).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040 ($add).
|
|
Removed top 16 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1037 ($add).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1035 ($sub).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3438_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3415_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3397_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3377_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3274_CMP0 ($eq).
|
|
Removed top 2 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3252_CMP0 ($eq).
|
|
Removed top 1 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$procmux$3231_CMP0 ($eq).
|
|
Removed top 28 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816 ($add).
|
|
Removed top 9 bits (of 32) from port Y of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$815 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$812 ($sub).
|
|
Removed top 27 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$809 ($shiftx).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$801 ($add).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4716_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4708_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4698_CMP0 ($eq).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4590_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4551_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4513_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4479_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4446_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4414_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4377_CMP0 ($eq).
|
|
Removed top 5 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4341_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4267_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4236_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4210_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4209_CMP0 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4208_CMP0 ($eq).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4077_CMP1 ($eq).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4077_CMP0 ($eq).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4062 ($pmux).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4060 ($mux).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3908_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3907_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3906_CMP0 ($eq).
|
|
Removed top 4 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3880_CMP0 ($eq).
|
|
Removed top 2 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$procmux$3772_CMP0 ($eq).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:728$797 ($add).
|
|
Removed top 3 bits (of 4) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$795 ($sub).
|
|
Removed top 6 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:692$794 ($eq).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:662$792 ($eq).
|
|
Removed top 15 bits (of 16) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:660$791 ($sub).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:579$786 ($add).
|
|
Removed top 7 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:567$785 ($eq).
|
|
Removed top 1 bits (of 2) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:558$783 ($eq).
|
|
Removed top 3 bits (of 8) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:511$781 ($eq).
|
|
Removed top 24 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:295$777 ($shiftx).
|
|
Removed top 31 bits (of 32) from port B of cell spi_neuron_top.$flatten\u_spi_engine.$lt$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:294$774 ($lt).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5225 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5222 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5219 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5217 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5214 ($mux).
|
|
Removed top 1 bits (of 8) from mux cell spi_neuron_top.$flatten\u_spi_slave.$procmux$5212 ($mux).
|
|
Removed top 2 bits (of 3) from port B of cell spi_neuron_top.$flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
|
|
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7560 ($sdffe).
|
|
Removed top 7 bits (of 8) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$7514 ($sdffe).
|
|
Removed cell spi_neuron_top.$auto$ff.cc:337:slice$7511 ($sdffe).
|
|
Removed top 15 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6687 ($sdffe).
|
|
Removed top 1 bits (of 16) from FF cell spi_neuron_top.$auto$ff.cc:337:slice$6529 ($sdffe).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4078 ($mux).
|
|
Removed top 8 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4064 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4062 ($pmux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4060 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4078 ($mux).
|
|
Removed top 9 bits (of 24) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4076 ($mux).
|
|
Removed top 1 bits (of 16) from mux cell spi_neuron_top.$flatten\u_spi_engine.$procmux$4064 ($mux).
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_ADDR[5:0]$955.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR[5:0]$1138.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$0$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1141.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\x_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:357$1132_ADDR[5:0]$1157.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1160.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_neuron_memory.$3$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:390$1133_ADDR[5:0]$1174.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4078_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4076_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4064_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4062_Y.
|
|
Removed top 9 bits (of 24) from wire spi_neuron_top.$flatten\u_spi_engine.$procmux$4060_Y.
|
|
Removed top 1 bits (of 6) from wire spi_neuron_top.$flatten\u_graph_engine.$2$memwr$\w_mem$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:496$883_ADDR[5:0]$1031.
|
|
Removed top 16 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1046_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061_Y.
|
|
Removed top 9 bits (of 32) from wire spi_neuron_top.$flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5225_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5222_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5219_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5217_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5214_Y.
|
|
Removed top 1 bits (of 8) from wire spi_neuron_top.$flatten\u_spi_slave.$procmux$5212_Y.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.n_neurons_real.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.seq_nm_n_neurons.
|
|
Removed top 15 bits (of 16) from wire spi_neuron_top.mux_nm_n_neurons.
|
|
Removed top 1 bits (of 23) from wire spi_neuron_top.i8_mem_addr.
|
|
Removed top 1 bits (of 23) from wire spi_neuron_top.psram_mem_addr.
|
|
|
|
17.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$1340, index=\u_graph_engine.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_graph_engine.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$1336, index=\u_graph_engine.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_layer_sequencer.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:291$809, index=\u_layer_sequencer.copy_idx, stride=8, width=8, ways=2
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:107$1340, index=\u_neuron_memory.u_neuron.group_index, stride=16, width=16, ways=16
|
|
shiftpow2 pattern in spi_neuron_top: shift=$flatten\u_neuron_memory.\u_neuron.$shiftx$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:101$1336, index=\u_neuron_memory.u_neuron.group_index, stride=16, width=16, ways=16
|
|
|
|
17.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 2 unused cells and 33 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
17.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
17.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.19.2. Continuing TECHMAP pass.
|
|
Using template $paramod$e284bc47c88f6e32a7d40296f7bdff7bac057394\_90_lut_cmp_ for cells of type $lt.
|
|
No more expansions possible.
|
|
<suppressed ~88 debug messages>
|
|
|
|
17.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.22.2. Continuing TECHMAP pass.
|
|
Using template $paramod$cc733e0dbb038034434917c1e0de96998ec4103f\_80_mul for cells of type $mul.
|
|
No more expansions possible.
|
|
<suppressed ~88 debug messages>
|
|
|
|
17.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.23.2. Continuing TECHMAP pass.
|
|
Using template $paramod$ea686d7c43b0ae12a4f0d39aec4e01bcc4449b23$__MUL18X18 for cells of type $__MUL18X18.
|
|
No more expansions possible.
|
|
<suppressed ~26 debug messages>
|
|
|
|
17.24. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module spi_neuron_top:
|
|
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1060 ($add).
|
|
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061 ($add).
|
|
creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1062 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1043 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1046 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1058 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1057 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1038 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1037 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1035 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1034 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$886 ($sub).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$801 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1055 ($sub).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1054 ($add).
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creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:728$797 ($add).
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creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$795 ($sub).
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creating $macc model for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:660$791 ($sub).
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creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:659$790 ($add).
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creating $macc model for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:579$786 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356 ($sub).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341 ($add).
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creating $macc model for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367 ($add).
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creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1169 ($sub).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1171 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1172 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1173 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1180 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1181 ($add).
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creating $macc model for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1185 ($sub).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1187 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1188 ($add).
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creating $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1189 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$806 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$810 ($sub).
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creating $macc model for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$812 ($sub).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$815 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$817 ($add).
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creating $macc model for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14 ($add).
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creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373 ($add).
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creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358 ($add).
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creating $macc model for $flatten\u_neuron_memory.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356 ($sub).
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creating $macc model for $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341 ($add).
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creating $macc model for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367 ($add).
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creating $macc model for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1262 ($add).
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creating $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047 ($add).
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creating $macc model for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$799 ($add).
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creating $macc model for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$884 ($sub).
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merging $macc model for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1046 into $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047.
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merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1180 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1181.
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merging $macc model for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1172 into $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1173.
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creating $alu model for $macc $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1262.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358.
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creating $alu model for $macc $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373.
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creating $alu model for $macc $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$817.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$815.
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creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$812.
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creating $alu model for $macc $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$810.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$806.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1189.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1188.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1187.
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creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1185.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1181.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$799.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1173.
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creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$884.
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creating $alu model for $macc $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1171.
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creating $alu model for $macc $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1169.
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creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367.
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creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341.
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creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356.
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creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358.
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creating $alu model for $macc $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373.
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creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:579$786.
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creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:659$790.
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creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:660$791.
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creating $alu model for $macc $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$795.
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creating $alu model for $macc $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:728$797.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1054.
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creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1055.
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creating $alu model for $macc $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$801.
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creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$886.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1034.
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creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1035.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1037.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1038.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1057.
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creating $alu model for $macc $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1058.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1043.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1062.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061.
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creating $alu model for $macc $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1060.
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creating $macc cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:430$1047: $auto$alumacc.cc:399:replace_macc$7640
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creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$885 ($ge): merged with $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$886.
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creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1052 ($ge): new $alu
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creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1050 ($ge): new $alu
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creating $alu model for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1049 ($ge): new $alu
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creating $alu model for $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:662$792 ($eq): merged with $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:660$791.
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creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:456$1049: $auto$alumacc.cc:548:replace_alu$7644
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creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:457$1050: $auto$alumacc.cc:548:replace_alu$7657
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creating $alu cell for $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:458$1052: $auto$alumacc.cc:548:replace_alu$7670
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:532$1060: $auto$alumacc.cc:548:replace_alu$7683
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:533$1061: $auto$alumacc.cc:548:replace_alu$7686
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:550$1062: $auto$alumacc.cc:548:replace_alu$7689
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:401$1043: $auto$alumacc.cc:548:replace_alu$7692
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:394$1040: $auto$alumacc.cc:548:replace_alu$7695
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creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:527$1058: $auto$alumacc.cc:548:replace_alu$7698
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:502$1057: $auto$alumacc.cc:548:replace_alu$7701
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:366$1038: $auto$alumacc.cc:548:replace_alu$7704
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creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:350$1037: $auto$alumacc.cc:548:replace_alu$7707
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creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:346$1035: $auto$alumacc.cc:548:replace_alu$7710
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:332$1034: $auto$alumacc.cc:548:replace_alu$7713
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:177$886, $flatten\u_graph_engine.$ge$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:176$885: $auto$alumacc.cc:548:replace_alu$7716
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:239$801: $auto$alumacc.cc:548:replace_alu$7729
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:498$1055: $auto$alumacc.cc:548:replace_alu$7732
|
|
creating $alu cell for $flatten\u_graph_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:478$1054: $auto$alumacc.cc:548:replace_alu$7735
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:728$797: $auto$alumacc.cc:548:replace_alu$7738
|
|
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:725$795: $auto$alumacc.cc:548:replace_alu$7741
|
|
creating $alu cell for $flatten\u_spi_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:660$791, $flatten\u_spi_engine.$eq$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:662$792: $auto$alumacc.cc:548:replace_alu$7744
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:659$790: $auto$alumacc.cc:548:replace_alu$7749
|
|
creating $alu cell for $flatten\u_spi_engine.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:579$786: $auto$alumacc.cc:548:replace_alu$7752
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373: $auto$alumacc.cc:548:replace_alu$7755
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358: $auto$alumacc.cc:548:replace_alu$7758
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356: $auto$alumacc.cc:548:replace_alu$7761
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341: $auto$alumacc.cc:548:replace_alu$7764
|
|
creating $alu cell for $flatten\u_graph_engine.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367: $auto$alumacc.cc:548:replace_alu$7767
|
|
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:359$1169: $auto$alumacc.cc:548:replace_alu$7770
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:371$1171: $auto$alumacc.cc:548:replace_alu$7773
|
|
creating $alu cell for $flatten\u_graph_engine.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/graph_engine.v:175$884: $auto$alumacc.cc:548:replace_alu$7776
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:373$1173: $auto$alumacc.cc:548:replace_alu$7779
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:211$799: $auto$alumacc.cc:548:replace_alu$7782
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:404$1181: $auto$alumacc.cc:548:replace_alu$7785
|
|
creating $alu cell for $flatten\u_neuron_memory.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:451$1185: $auto$alumacc.cc:548:replace_alu$7788
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:464$1187: $auto$alumacc.cc:548:replace_alu$7791
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:465$1188: $auto$alumacc.cc:548:replace_alu$7794
|
|
creating $alu cell for $flatten\u_neuron_memory.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_memory.v:466$1189: $auto$alumacc.cc:548:replace_alu$7797
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:290$806: $auto$alumacc.cc:548:replace_alu$7800
|
|
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:301$810: $auto$alumacc.cc:548:replace_alu$7803
|
|
creating $alu cell for $flatten\u_layer_sequencer.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:303$812: $auto$alumacc.cc:548:replace_alu$7806
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:316$815: $auto$alumacc.cc:548:replace_alu$7809
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:317$816: $auto$alumacc.cc:548:replace_alu$7812
|
|
creating $alu cell for $flatten\u_layer_sequencer.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer_sequencer.v:326$817: $auto$alumacc.cc:548:replace_alu$7815
|
|
creating $alu cell for $flatten\u_spi_slave.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:173$14: $auto$alumacc.cc:548:replace_alu$7818
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101$1373: $auto$alumacc.cc:548:replace_alu$7821
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:240$1358: $auto$alumacc.cc:548:replace_alu$7824
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$sub$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:232$1356: $auto$alumacc.cc:548:replace_alu$7827
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:147$1341: $auto$alumacc.cc:548:replace_alu$7830
|
|
creating $alu cell for $flatten\u_neuron_memory.\u_neuron.\u_mac8.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115$1367: $auto$alumacc.cc:548:replace_alu$7833
|
|
creating $alu cell for $flatten\u_psram_ctrl.$add$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:186$1262: $auto$alumacc.cc:548:replace_alu$7836
|
|
created 51 $alu and 1 $macc cells.
|
|
|
|
17.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1492 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~544 debug messages>
|
|
|
|
17.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 1 changes.
|
|
|
|
17.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1492 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 3 unused cells and 40 unused wires.
|
|
<suppressed ~4 debug messages>
|
|
|
|
17.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.25.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.25.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~546 debug messages>
|
|
|
|
17.25.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.25.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1489 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.25.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.25.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.25.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
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|
|
|
17.25.16. Finished fast OPT passes. (There is nothing left to do.)
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|
|
17.26. Executing MEMORY pass.
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|
17.26.1. Executing OPT_MEM pass (optimize memories).
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600: removing const-0 lane 6
|
|
spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600: removing const-0 lane 7
|
|
Performed a total of 1 transformations.
|
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|
|
17.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 992 transformations.
|
|
|
|
17.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 0.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 1.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 2.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 3.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 4.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 5.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 6.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 7.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 8.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 9.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 10.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 11.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 12.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 13.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 14.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 15.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 16.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 17.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 18.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 19.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 20.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 21.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 22.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 23.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 24.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 25.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 26.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 27.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 28.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 29.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 30.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 31.
|
|
Analyzing spi_neuron_top.u_graph_engine.x_mem write port 32.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 0.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 1.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 2.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 3.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 4.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 5.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 6.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 7.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 8.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 9.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 10.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 11.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 12.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 13.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 14.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 15.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 16.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 17.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 18.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 19.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 20.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 21.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 22.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 23.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 24.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 25.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 26.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 27.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 28.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 29.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 30.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 31.
|
|
Analyzing spi_neuron_top.u_graph_engine.w_mem write port 32.
|
|
Analyzing spi_neuron_top.u_graph_engine.u_act_buffer.mem write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.y_reg write port 1.
|
|
Analyzing spi_neuron_top.u_neuron_memory.x_mem write port 0.
|
|
Analyzing spi_neuron_top.u_neuron_memory.w_mem write port 0.
|
|
|
|
17.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
17.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_graph_engine.u_act_buffer.mem'[0] in module `\spi_neuron_top': merging output FF to cell.
|
|
Write port 0: non-transparent.
|
|
Checking read port `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no output FF found.
|
|
Checking read port address `$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600'[0] in module `\spi_neuron_top': merged address FF to cell.
|
|
Checking read port address `\u_graph_engine.x_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.x_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_graph_engine.w_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.y_reg'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.x_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[0] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[1] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[2] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[3] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[4] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[5] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[6] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[7] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[8] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[9] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[10] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[11] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[12] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[13] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[14] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[15] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[16] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[17] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[18] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[19] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[20] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[21] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[22] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[23] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[24] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[25] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[26] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[27] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[28] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[29] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[30] in module `\spi_neuron_top': no address FF found.
|
|
Checking read port address `\u_neuron_memory.w_mem'[31] in module `\spi_neuron_top': no address FF found.
|
|
|
|
17.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1 unused cells and 9 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 0, 1 (address 5'00000).
|
|
Merging ports 0, 2 (address 5'00000).
|
|
Merging ports 0, 3 (address 5'00000).
|
|
Merging ports 0, 4 (address 5'00000).
|
|
Merging ports 0, 5 (address 5'00000).
|
|
Merging ports 0, 6 (address 5'00000).
|
|
Merging ports 0, 7 (address 5'00000).
|
|
Merging ports 0, 8 (address 5'00000).
|
|
Merging ports 0, 9 (address 5'00000).
|
|
Merging ports 0, 10 (address 5'00000).
|
|
Merging ports 0, 11 (address 5'00000).
|
|
Merging ports 0, 12 (address 5'00000).
|
|
Merging ports 0, 13 (address 5'00000).
|
|
Merging ports 0, 14 (address 5'00000).
|
|
Merging ports 0, 15 (address 5'00000).
|
|
Merging ports 0, 16 (address 5'00000).
|
|
Merging ports 18, 19 (address 5'10010).
|
|
Merging ports 20, 21 (address 5'10100).
|
|
Merging ports 20, 22 (address 5'10100).
|
|
Merging ports 20, 23 (address 5'10100).
|
|
Merging ports 24, 25 (address 5'11000).
|
|
Merging ports 24, 26 (address 5'11000).
|
|
Merging ports 24, 27 (address 5'11000).
|
|
Merging ports 24, 28 (address 5'11000).
|
|
Merging ports 24, 29 (address 5'11000).
|
|
Merging ports 24, 30 (address 5'11000).
|
|
Merging ports 24, 31 (address 5'11000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Merging ports 1, 2 (address 5'10001).
|
|
Merging ports 1, 3 (address 5'10000).
|
|
Merging ports 1, 4 (address 5'10000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 0, 1 (address 5'00000).
|
|
Merging ports 0, 2 (address 5'00000).
|
|
Merging ports 0, 3 (address 5'00000).
|
|
Merging ports 0, 4 (address 5'00000).
|
|
Merging ports 0, 5 (address 5'00000).
|
|
Merging ports 0, 6 (address 5'00000).
|
|
Merging ports 0, 7 (address 5'00000).
|
|
Merging ports 0, 8 (address 5'00000).
|
|
Merging ports 0, 9 (address 5'00000).
|
|
Merging ports 0, 10 (address 5'00000).
|
|
Merging ports 0, 11 (address 5'00000).
|
|
Merging ports 0, 12 (address 5'00000).
|
|
Merging ports 0, 13 (address 5'00000).
|
|
Merging ports 0, 14 (address 5'00000).
|
|
Merging ports 0, 15 (address 5'00000).
|
|
Merging ports 0, 16 (address 5'00000).
|
|
Merging ports 18, 19 (address 5'10010).
|
|
Merging ports 20, 21 (address 5'10100).
|
|
Merging ports 20, 22 (address 5'10100).
|
|
Merging ports 20, 23 (address 5'10100).
|
|
Merging ports 24, 25 (address 5'11000).
|
|
Merging ports 24, 26 (address 5'11000).
|
|
Merging ports 24, 27 (address 5'11000).
|
|
Merging ports 24, 28 (address 5'11000).
|
|
Merging ports 24, 29 (address 5'11000).
|
|
Merging ports 24, 30 (address 5'11000).
|
|
Merging ports 24, 31 (address 5'11000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Merging ports 1, 2 (address 5'10001).
|
|
Merging ports 1, 3 (address 5'10000).
|
|
Merging ports 1, 4 (address 5'10000).
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.x_mem by address:
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 0, 1 (address 5'11111).
|
|
Merging ports 0, 2 (address 5'11110).
|
|
Merging ports 0, 3 (address 5'11100).
|
|
Merging ports 0, 4 (address 5'11100).
|
|
Merging ports 0, 5 (address 5'11000).
|
|
Merging ports 0, 6 (address 5'11000).
|
|
Merging ports 0, 7 (address 5'11000).
|
|
Merging ports 0, 8 (address 5'11000).
|
|
Merging ports 0, 9 (address 5'10000).
|
|
Merging ports 0, 10 (address 5'10000).
|
|
Merging ports 0, 11 (address 5'10000).
|
|
Merging ports 0, 12 (address 5'10000).
|
|
Merging ports 0, 13 (address 5'10000).
|
|
Merging ports 0, 14 (address 5'10000).
|
|
Merging ports 0, 15 (address 5'10000).
|
|
Merging ports 0, 16 (address 5'10000).
|
|
Merging ports 18, 19 (address 5'01101).
|
|
Merging ports 20, 21 (address 5'01011).
|
|
Merging ports 20, 22 (address 5'01010).
|
|
Merging ports 20, 23 (address 5'01000).
|
|
Merging ports 24, 25 (address 5'00111).
|
|
Merging ports 24, 26 (address 5'00110).
|
|
Merging ports 24, 27 (address 5'00100).
|
|
Merging ports 24, 28 (address 5'00100).
|
|
Merging ports 24, 29 (address 5'00000).
|
|
Merging ports 24, 30 (address 5'00000).
|
|
Merging ports 24, 31 (address 5'00000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Merging ports 1, 2 (address 5'01110).
|
|
Merging ports 1, 3 (address 5'01100).
|
|
Merging ports 1, 4 (address 5'01000).
|
|
Consolidating read ports of memory spi_neuron_top.u_neuron_memory.w_mem by address:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.x_mem using sat-based resource sharing:
|
|
Consolidating write ports of memory spi_neuron_top.u_graph_engine.w_mem using sat-based resource sharing:
|
|
Consolidating write ports of memory spi_neuron_top.u_neuron_memory.y_reg using sat-based resource sharing:
|
|
Checking group clocked with posedge \clk, width 8: ports 0, 1.
|
|
Common input cone for all EN signals: 5 cells.
|
|
Size of unconstrained SAT problem: 42 variables, 115 clauses
|
|
Merging port 1 into port 0.
|
|
|
|
17.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
17.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1 unused cells and 113 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
17.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory spi_neuron_top.u_graph_engine.u_act_buffer.mem via $__DP16KD_
|
|
using FF mapping for memory spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600
|
|
using FF mapping for memory spi_neuron_top.u_graph_engine.w_mem
|
|
using FF mapping for memory spi_neuron_top.u_graph_engine.x_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.x_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.w_mem
|
|
using FF mapping for memory spi_neuron_top.u_neuron_memory.y_reg
|
|
<suppressed ~910 debug messages>
|
|
|
|
17.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.29.3. Continuing TECHMAP pass.
|
|
Using template $paramod$c4aea9a221b3d95ca47d9df3d018cdac65e6baac$__DP16KD_ for cells of type $__DP16KD_.
|
|
No more expansions possible.
|
|
<suppressed ~36 debug messages>
|
|
|
|
17.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~354 debug messages>
|
|
|
|
17.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1139 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$8247 ($dffe) from module spi_neuron_top.
|
|
|
|
17.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 264 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.30.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
17.30.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~3 debug messages>
|
|
|
|
17.30.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1136 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.30.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 3 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.30.10. Finished fast OPT passes.
|
|
|
|
17.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
Mapping memory $flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600 in module \spi_neuron_top:
|
|
created 16 $dff cells and 0 static cells of width 6.
|
|
Extracted data FF from read port 0 of spi_neuron_top.$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600: $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdreg[0]
|
|
read interface: 1 $dff and 15 $mux cells.
|
|
write interface: 0 write mux blocks.
|
|
Mapping memory \u_graph_engine.w_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 96 write mux blocks.
|
|
Mapping memory \u_graph_engine.x_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 96 write mux blocks.
|
|
Mapping memory \u_neuron_memory.x_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
Mapping memory \u_neuron_memory.w_mem in module \spi_neuron_top:
|
|
created 32 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 1 $mux cells.
|
|
write interface: 32 write mux blocks.
|
|
Mapping memory \u_neuron_memory.y_reg in module \spi_neuron_top:
|
|
created 1 $dff cells and 0 static cells of width 8.
|
|
read interface: 0 $dff and 0 $mux cells.
|
|
write interface: 1 write mux blocks.
|
|
|
|
17.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~223 debug messages>
|
|
|
|
17.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1699 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1667 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~96 debug messages>
|
|
Removed a total of 32 cells.
|
|
|
|
17.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $auto$memory_share.cc:454:consolidate_wr_using_sat$8239: $auto$rtlil.cc:3271:ReduceOr$8233 -> 1'1
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~651 debug messages>
|
|
|
|
17.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][5]$8549:
|
|
Old ports: A=6'000001, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$b$8530
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$b$8530 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$b$8530 [5:1] = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][4]$8546:
|
|
Old ports: A=6'010000, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529 [4]
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529 [3:0] } = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][3]$8543:
|
|
Old ports: A=6'000000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$b$8527
|
|
New ports: A=1'0, B=1'1, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$b$8527 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$b$8527 [5:1] = 5'00000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][2]$8540:
|
|
Old ports: A=6'000010, B=6'001000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526
|
|
New ports: A=2'01, B=2'10, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [1] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [2] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [0] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][1]$8537:
|
|
Old ports: A=6'100000, B=6'000001, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524
|
|
New ports: A=2'10, B=2'01, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [4:1] = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][3][0]$8534:
|
|
Old ports: A=6'010111, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523
|
|
New ports: A=1'1, B=1'0, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0]
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [5:1] = { 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0] }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2929: $auto$opt_reduce.cc:137:opt_pmux$10095
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$2952: $auto$opt_reduce.cc:137:opt_pmux$10097
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3006: $auto$opt_reduce.cc:137:opt_pmux$10099
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3024: { $auto$opt_reduce.cc:137:opt_pmux$10103 $auto$opt_reduce.cc:137:opt_pmux$10101 }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3060: { $auto$opt_reduce.cc:137:opt_pmux$10105 \u_graph_engine.state [2] }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3164: $auto$opt_reduce.cc:137:opt_pmux$10107
|
|
Consolidated identical input bits for $mux cell $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349:
|
|
Old ports: A=8'01111111, B=8'10000000, Y=$flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [7] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] }
|
|
New connections: $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [6:1] = { $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_graph_engine.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4015: $auto$opt_reduce.cc:137:opt_pmux$10109
|
|
Consolidated identical input bits for $pmux cell $flatten\u_neuron_memory.$procmux$2115:
|
|
Old ports: A=1'0, B=2'00, Y=$flatten\u_neuron_memory.$procmux$2115_Y
|
|
New connections: $flatten\u_neuron_memory.$procmux$2115_Y = 1'0
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2189: { \u_neuron_memory.state [2] \u_neuron_memory.state [3] }
|
|
New ctrl vector for $pmux cell $flatten\u_neuron_memory.$procmux$2228: \u_neuron_memory.state [0]
|
|
Consolidated identical input bits for $mux cell $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349:
|
|
Old ports: A=8'01111111, B=8'10000000, Y=$flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y
|
|
New ports: A=2'01, B=2'10, Y={ $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [7] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] }
|
|
New connections: $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [6:1] = { $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] $flatten\u_neuron_memory.\u_neuron.$ternary$/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:178$1349_Y [0] }
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$4062: \u_spi_engine.state [4]
|
|
New ctrl vector for $pmux cell $flatten\u_spi_engine.$procmux$3988: $auto$opt_reduce.cc:137:opt_pmux$10111
|
|
New ctrl vector for $pmux cell $flatten\u_layer_sequencer.$procmux$3469: \u_layer_sequencer.state [2]
|
|
New ctrl vector for $pmux cell $flatten\u_psram_ctrl.$procmux$4912: { \u_psram_ctrl.state [0] $auto$opt_reduce.cc:137:opt_pmux$5687 }
|
|
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10106: { \u_graph_engine.state [10:9] \u_graph_engine.state [7] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$8528:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$b$8530, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$a$8529 [4] 1'0 }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][2]$b$8530 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [3:1] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$8525:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$b$8527, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [1] 1'0 }, B={ 2'00 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$b$8527 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [3] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [1:0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [5:4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [2] } = 3'000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$8522:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517
|
|
New ports: A={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$a$8523 [0] }, B={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [1:0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [4:2] = { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [1] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [1] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$8519:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520, B=6'000000, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$b$8515
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][1]$a$8520 [0] }, B=2'00, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$b$8515 [4] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$b$8515 [0] }
|
|
New connections: { $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$b$8515 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$b$8515 [3:1] } = 4'0000
|
|
Consolidated identical input bits for $mux cell $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$8516:
|
|
Old ports: A=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517, B=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518, Y=$memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514
|
|
New ports: A={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [5] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [1] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$a$8517 [1:0] }, B={ 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [3] 1'0 $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][1][0]$b$8518 [1:0] }, Y={ $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514 [5] $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514 [3:0] }
|
|
New connections: $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514 [4] = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514 [2]
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 28 changes.
|
|
|
|
17.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1675 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1668 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
17.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7274 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2929_Y, Q = \u_graph_engine.desc_addr).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7288 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$2952_Y, Q = \u_graph_engine.neuron_idx).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7331 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3024_Y, Q = \u_graph_engine.busy).
|
|
Adding EN signal on $auto$ff.cc:337:slice$7353 ($sdffe) from module spi_neuron_top (D = $flatten\u_graph_engine.$procmux$3060_Y, Q = \u_graph_engine.desc_byte_idx).
|
|
|
|
17.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 410 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~6 debug messages>
|
|
|
|
17.32.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~632 debug messages>
|
|
|
|
17.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10131: { $auto$opt_dff.cc:319:make_patterns_logic$7197 $auto$opt_dff.cc:319:make_patterns_logic$7199 $auto$opt_dff.cc:319:make_patterns_logic$7229 $auto$opt_dff.cc:319:make_patterns_logic$7279 $auto$opt_dff.cc:319:make_patterns_logic$7283 $auto$opt_dff.cc:319:make_patterns_logic$7362 $auto$opt_dff.cc:319:make_patterns_logic$7364 $auto$opt_dff.cc:319:make_patterns_logic$7368 $auto$opt_dff.cc:319:make_patterns_logic$10128 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10126: { $auto$opt_dff.cc:319:make_patterns_logic$7199 $auto$opt_dff.cc:319:make_patterns_logic$7231 $auto$opt_dff.cc:319:make_patterns_logic$7277 $auto$opt_dff.cc:319:make_patterns_logic$7279 $auto$opt_dff.cc:319:make_patterns_logic$7283 $auto$opt_dff.cc:319:make_patterns_logic$7321 $auto$opt_dff.cc:319:make_patterns_logic$7323 $auto$opt_dff.cc:319:make_patterns_logic$7325 $auto$opt_dff.cc:319:make_patterns_logic$7332 $auto$opt_dff.cc:319:make_patterns_logic$10123 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10121: { $auto$opt_dff.cc:319:make_patterns_logic$7199 $auto$opt_dff.cc:319:make_patterns_logic$7275 $auto$opt_dff.cc:319:make_patterns_logic$7277 $auto$opt_dff.cc:319:make_patterns_logic$7279 $auto$opt_dff.cc:319:make_patterns_logic$7283 $auto$opt_dff.cc:319:make_patterns_logic$10118 }
|
|
New input vector for $reduce_and cell $auto$opt_dff.cc:337:make_patterns_logic$10116: { $auto$opt_dff.cc:319:make_patterns_logic$7199 $auto$opt_dff.cc:319:make_patterns_logic$7275 $auto$opt_dff.cc:319:make_patterns_logic$7277 $auto$opt_dff.cc:319:make_patterns_logic$7279 $auto$opt_dff.cc:319:make_patterns_logic$7283 $auto$opt_dff.cc:319:make_patterns_logic$10113 }
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3024: $auto$opt_reduce.cc:137:opt_pmux$10133
|
|
New ctrl vector for $pmux cell $flatten\u_graph_engine.$procmux$3060: \u_graph_engine.state [2]
|
|
New input vector for $reduce_or cell $auto$opt_reduce.cc:131:opt_pmux$10132: { \u_graph_engine.state [11] \u_graph_engine.state [9:8] \u_graph_engine.state [6] }
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 7 changes.
|
|
|
|
17.32.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1671 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1669 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1668 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~9 debug messages>
|
|
Removed a total of 3 cells.
|
|
|
|
17.32.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][0]$b$8524 [5], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [5], rval = 1'0).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][2][1]$a$8526 [3], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [3], rval = 1'0).
|
|
Adding SRST signal on $$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdreg[0] ($dff) from module spi_neuron_top (D = $memory$flatten\u_spi_engine.$auto$proc_rom.cc:155:do_switch$1600$rdmux[0][0][0]$a$8514 [2:1], Q = $flatten\u_spi_engine.$4\tx_byte_comb[7:0] [2:1], rval = 2'00).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[0]$8558 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[0][2][0]$y$8658, Q = \u_graph_engine.w_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[1]$8560 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[1][2][0]$y$8676, Q = \u_graph_engine.w_mem[1]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[2]$8562 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[2][2][0]$y$8694, Q = \u_graph_engine.w_mem[2]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[3]$8564 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[3][2][0]$y$8710, Q = \u_graph_engine.w_mem[3]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[4]$8566 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[4][2][0]$y$8728, Q = \u_graph_engine.w_mem[4]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[5]$8568 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[5][2][0]$y$8742, Q = \u_graph_engine.w_mem[5]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[6]$8570 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[6][2][0]$y$8756, Q = \u_graph_engine.w_mem[6]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[7]$8572 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[7][2][0]$y$8770, Q = \u_graph_engine.w_mem[7]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[8]$8574 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[8][2][0]$y$8790, Q = \u_graph_engine.w_mem[8]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[9]$8576 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[9][2][0]$y$8804, Q = \u_graph_engine.w_mem[9]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[10]$8578 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[10][2][0]$y$8818, Q = \u_graph_engine.w_mem[10]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[11]$8580 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[11][2][0]$y$8832, Q = \u_graph_engine.w_mem[11]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[12]$8582 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[12][2][0]$y$8848, Q = \u_graph_engine.w_mem[12]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[13]$8584 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[13][2][0]$y$8862, Q = \u_graph_engine.w_mem[13]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[14]$8586 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[14][2][0]$y$8876, Q = \u_graph_engine.w_mem[14]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[15]$8588 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[15][2][0]$y$8890, Q = \u_graph_engine.w_mem[15]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[16]$8590 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[16][2][0]$y$8912, Q = \u_graph_engine.w_mem[16]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[17]$8592 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[17][2][0]$y$8926, Q = \u_graph_engine.w_mem[17]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[18]$8594 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[18][2][0]$y$8940, Q = \u_graph_engine.w_mem[18]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[19]$8596 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[19][2][0]$y$8954, Q = \u_graph_engine.w_mem[19]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[20]$8598 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[20][2][0]$y$8970, Q = \u_graph_engine.w_mem[20]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[21]$8600 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[21][2][0]$y$8984, Q = \u_graph_engine.w_mem[21]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[22]$8602 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[22][2][0]$y$8998, Q = \u_graph_engine.w_mem[22]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[23]$8604 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[23][2][0]$y$9012, Q = \u_graph_engine.w_mem[23]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[24]$8606 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[24][2][0]$y$9030, Q = \u_graph_engine.w_mem[24]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[25]$8608 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[25][2][0]$y$9044, Q = \u_graph_engine.w_mem[25]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[26]$8610 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[26][2][0]$y$9058, Q = \u_graph_engine.w_mem[26]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[27]$8612 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[27][2][0]$y$9072, Q = \u_graph_engine.w_mem[27]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[28]$8614 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[28][2][0]$y$9088, Q = \u_graph_engine.w_mem[28]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[29]$8616 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[29][2][0]$y$9102, Q = \u_graph_engine.w_mem[29]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[30]$8618 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[30][2][0]$y$9116, Q = \u_graph_engine.w_mem[30]).
|
|
Adding EN signal on $memory\u_graph_engine.w_mem[31]$8620 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.w_mem$wrmux[31][2][0]$y$9130, Q = \u_graph_engine.w_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[7]$9596 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[7]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[8]$9598 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[8]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[9]$9600 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[9]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[10]$9602 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[10]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[11]$9604 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[11]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[12]$9606 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[12]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[13]$9608 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[13]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[14]$9610 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[14]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[15]$9612 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[15]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[16]$9614 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[16]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[17]$9616 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[17]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[18]$9618 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[18]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[19]$9620 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[19]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[20]$9622 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[20]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[21]$9624 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[21]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[31]$9955 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[30]$9953 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[30]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[22]$9626 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[22]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[29]$9951 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[29]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[28]$9949 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[28]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[27]$9947 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[27]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[23]$9628 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[23]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[26]$9945 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[26]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[25]$9943 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[25]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[24]$9941 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[24]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[24]$9630 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[24]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[23]$9939 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[23]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[22]$9937 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[22]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[21]$9935 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[21]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[25]$9632 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[25]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[20]$9933 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[20]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[19]$9931 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[19]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[18]$9929 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[18]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[26]$9634 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[26]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[17]$9927 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[17]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[16]$9925 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[16]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[15]$9923 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[15]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[27]$9636 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[27]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[14]$9921 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[14]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[13]$9919 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[13]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[12]$9917 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[12]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[28]$9638 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[28]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[11]$9915 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[11]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[10]$9913 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[10]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[9]$9911 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[9]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[29]$9640 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[29]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[8]$9909 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[8]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[7]$9907 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[7]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[6]$9905 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[6]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[30]$9642 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[30]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[5]$9903 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[5]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[4]$9901 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[4]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[3]$9899 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[3]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[31]$9644 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[2]$9897 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[2]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[1]$9895 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[1]).
|
|
Adding EN signal on $memory\u_neuron_memory.w_mem[0]$9893 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.w_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[0]$9131 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[0][2][0]$y$9209, Q = \u_graph_engine.x_mem[0]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[1]$9133 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[1][2][0]$y$9221, Q = \u_graph_engine.x_mem[1]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[2]$9135 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[2][2][0]$y$9233, Q = \u_graph_engine.x_mem[2]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[3]$9137 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[3][2][0]$y$9245, Q = \u_graph_engine.x_mem[3]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[4]$9139 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[4][2][0]$y$9257, Q = \u_graph_engine.x_mem[4]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[5]$9141 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[5][2][0]$y$9269, Q = \u_graph_engine.x_mem[5]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[6]$9143 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[6][2][0]$y$9281, Q = \u_graph_engine.x_mem[6]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[7]$9145 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[7][2][0]$y$9293, Q = \u_graph_engine.x_mem[7]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[8]$9147 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[8][2][0]$y$9305, Q = \u_graph_engine.x_mem[8]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[9]$9149 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[9][2][0]$y$9317, Q = \u_graph_engine.x_mem[9]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[10]$9151 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[10][2][0]$y$9329, Q = \u_graph_engine.x_mem[10]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[11]$9153 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[11][2][0]$y$9341, Q = \u_graph_engine.x_mem[11]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[12]$9155 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[12][2][0]$y$9353, Q = \u_graph_engine.x_mem[12]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[13]$9157 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[13][2][0]$y$9365, Q = \u_graph_engine.x_mem[13]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[14]$9159 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[14][2][0]$y$9377, Q = \u_graph_engine.x_mem[14]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[15]$9161 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[15][2][0]$y$9389, Q = \u_graph_engine.x_mem[15]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[16]$9163 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[16][2][0]$y$9401, Q = \u_graph_engine.x_mem[16]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[17]$9165 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[17][2][0]$y$9413, Q = \u_graph_engine.x_mem[17]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[18]$9167 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[18][2][0]$y$9425, Q = \u_graph_engine.x_mem[18]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[19]$9169 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[19][2][0]$y$9437, Q = \u_graph_engine.x_mem[19]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[20]$9171 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[20][2][0]$y$9449, Q = \u_graph_engine.x_mem[20]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[21]$9173 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[21][2][0]$y$9461, Q = \u_graph_engine.x_mem[21]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[22]$9175 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[22][2][0]$y$9473, Q = \u_graph_engine.x_mem[22]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[23]$9177 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[23][2][0]$y$9485, Q = \u_graph_engine.x_mem[23]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[24]$9179 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[24][2][0]$y$9497, Q = \u_graph_engine.x_mem[24]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[25]$9181 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[25][2][0]$y$9509, Q = \u_graph_engine.x_mem[25]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[26]$9183 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[26][2][0]$y$9521, Q = \u_graph_engine.x_mem[26]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[27]$9185 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[27][2][0]$y$9533, Q = \u_graph_engine.x_mem[27]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[28]$9187 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[28][2][0]$y$9545, Q = \u_graph_engine.x_mem[28]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[29]$9189 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[29][2][0]$y$9557, Q = \u_graph_engine.x_mem[29]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[30]$9191 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[30][2][0]$y$9569, Q = \u_graph_engine.x_mem[30]).
|
|
Adding EN signal on $memory\u_graph_engine.x_mem[31]$9193 ($dff) from module spi_neuron_top (D = $memory\u_graph_engine.x_mem$wrmux[31][2][0]$y$9581, Q = \u_graph_engine.x_mem[31]).
|
|
Adding EN signal on $memory\u_neuron_memory.y_reg[0]$10088 ($dff) from module spi_neuron_top (D = $auto$rtlil.cc:3402:Mux$8237, Q = \u_neuron_memory.y_reg[0]).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10395 ($dffe) from module spi_neuron_top (D = \u_neuron_memory.u_neuron.y, Q = \u_neuron_memory.y_reg[0], rval = 8'00000000).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[0]$9582 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[0]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[1]$9584 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[1]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[2]$9586 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[2]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[3]$9588 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[3]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[4]$9590 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[4]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[5]$9592 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[5]).
|
|
Adding EN signal on $memory\u_neuron_memory.x_mem[6]$9594 ($dff) from module spi_neuron_top (D = \u_neuron_memory.u_mem.rdata, Q = \u_neuron_memory.x_mem[6]).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$7011 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 73 unused cells and 82 unused wires.
|
|
<suppressed ~74 debug messages>
|
|
|
|
17.32.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~128 debug messages>
|
|
|
|
17.32.16. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~440 debug messages>
|
|
|
|
17.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.32.19. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1601 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 1569 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~96 debug messages>
|
|
Removed a total of 32 cells.
|
|
|
|
17.32.20. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10146 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[0], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10149 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[1], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10152 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[2], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10155 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[3], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10158 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[4], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10161 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[5], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10164 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[6], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10167 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[7], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10170 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[8], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10173 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[9], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10176 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[10], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10179 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[11], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10182 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[12], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10185 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[13], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10188 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[14], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10191 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[15], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10194 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[16], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10197 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[17], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10200 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[18], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10203 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[19], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10206 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[20], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10209 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[21], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10212 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[22], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10215 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[23], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10218 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[24], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10221 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[25], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10224 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[26], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10227 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[27], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10230 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[28], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10233 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[29], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10236 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[30], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10239 ($dffe) from module spi_neuron_top (D = \u_graph_engine.weight_acc, Q = \u_graph_engine.w_mem[31], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10299 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[0], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10302 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[1], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10305 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[2], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10308 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[3], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10311 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[4], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10314 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[5], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10317 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[6], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10320 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[7], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10323 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[8], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10326 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[9], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10329 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[10], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10332 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[11], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10335 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[12], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10338 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[13], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10341 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[14], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10344 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[15], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10347 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[16], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10350 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[17], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10353 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[18], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10356 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[19], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10359 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[20], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10362 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[21], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10365 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[22], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10368 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[23], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10371 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[24], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10374 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[25], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10377 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[26], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10380 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[27], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10383 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[28], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10386 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[29], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10389 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[30], rval = 8'00000000).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$10392 ($dffe) from module spi_neuron_top (D = \u_graph_engine.u_act_buffer.rd_data, Q = \u_graph_engine.x_mem[31], rval = 8'00000000).
|
|
Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$6915 ($sdffe) from module spi_neuron_top.
|
|
|
|
17.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 64 unused cells and 160 unused wires.
|
|
<suppressed ~65 debug messages>
|
|
|
|
17.32.22. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.32.23. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.32.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~280 debug messages>
|
|
|
|
17.32.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.32.26. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 1504 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.32.27. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.32.28. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.32.29. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.32.30. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdffce.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using extmapper simplemap for cells of type $reduce_bool.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $reduce_and.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $ne.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using template $paramod$713617589782cfade849bb573b5c36106c4b708f\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2470b7ea32c975a55c3ab8b283381b72d09e16d3\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8fdcfe020be5e507ba05385ffd706e02b549d39d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
|
|
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
|
|
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
|
|
Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$7bdc7d89ea9376c9c454fd05d9b64ca6288b61c9\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$bb2d74554e7f3344a65c51a9d0fb34626611aac9\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ccu2c_alu for cells of type $alu.
|
|
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
|
|
Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper maccmap for cells of type $macc_v2.
|
|
add \u_graph_engine.conn_ptr_acc [22:0] (23 bits, unsigned)
|
|
add \u_graph_engine.edge_byte_idx (2 bits, unsigned)
|
|
add { \u_graph_engine.conn_i 2'00 } (8 bits, unsigned)
|
|
Using extmapper simplemap for cells of type $bmux.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using extmapper simplemap for cells of type $pmux.
|
|
Using extmapper simplemap for cells of type $tribuf.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using template $paramod$constmap:1c62fa0501c71c523e718f52047352464d16f12e$paramod$a50ae57e8afac966c737391c51ad88342606b747\_90_shift_shiftx for cells of type $shiftx.
|
|
Using extmapper simplemap for cells of type $lut.
|
|
Using template $paramod$448756c9a9dfaa49080ce4b90c6cc182883e181f\_80_ccu2c_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
|
|
No more expansions possible.
|
|
<suppressed ~4626 debug messages>
|
|
|
|
17.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~3162 debug messages>
|
|
|
|
17.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 9282 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8810 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8713 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 8702 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~1740 debug messages>
|
|
Removed a total of 580 cells.
|
|
|
|
17.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15815 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17771, Q = \u_psram_ctrl.dq_oe, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15765 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17761, Q = \u_psram_ctrl.psram_ub_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15764 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17744, Q = \u_psram_ctrl.psram_lb_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15763 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17727, Q = \u_psram_ctrl.psram_we_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15762 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17716, Q = \u_psram_ctrl.psram_oe_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15761 ($_SDFF_PP1_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17706, Q = \u_psram_ctrl.psram_ce_n, rval = 1'1).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$15758 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$17690, Q = \u_psram_ctrl.mem_ready, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14967 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$18533, Q = \u_neuron_memory.access_req, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14652 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19194, Q = \u_graph_engine.act_wr_en, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14401 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19184, Q = \u_graph_engine.done, rval = 1'0).
|
|
Adding SRST signal on $auto$ff.cc:337:slice$14322 ($_SDFF_PP0_) from module spi_neuron_top (D = $auto$simplemap.cc:189:logic_reduce$19204, Q = \u_graph_engine.ram_req, rval = 1'0).
|
|
|
|
17.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 1585 unused cells and 3909 unused wires.
|
|
<suppressed ~1586 debug messages>
|
|
|
|
17.34.5. Rerunning OPT passes. (Removed registers in this run.)
|
|
|
|
17.34.6. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.34.7. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 7137 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7133 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7130 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~21 debug messages>
|
|
Removed a total of 7 cells.
|
|
|
|
17.34.8. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.34.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 7 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.34.10. Finished fast OPT passes.
|
|
|
|
17.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
17.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 8170 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7683 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 7196 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~2922 debug messages>
|
|
Removed a total of 974 cells.
|
|
|
|
17.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.38.2. Continuing TECHMAP pass.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
Using template $_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
No more expansions possible.
|
|
<suppressed ~2501 debug messages>
|
|
|
|
17.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~18 debug messages>
|
|
|
|
17.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
17.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in spi_neuron_top.
|
|
|
|
17.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
17.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 14680 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
17.46. Executing ABC9 pass.
|
|
|
|
17.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.3. Executing SCC pass (detecting logic loops).
|
|
Found an SCC: $auto$ff.cc:337:slice$14722 $auto$simplemap.cc:157:simplemap_reduce$14720 $auto$simplemap.cc:157:simplemap_reduce$14718
|
|
Found an SCC: $auto$ff.cc:337:slice$15155 $auto$simplemap.cc:157:simplemap_reduce$15153 $auto$simplemap.cc:157:simplemap_reduce$15151
|
|
Found 2 SCCs in module spi_neuron_top.
|
|
Found 2 SCCs.
|
|
|
|
17.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.5. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.5.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~166 debug messages>
|
|
|
|
17.46.6. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.46.6.1. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
17.46.6.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.6.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
|
|
17.46.6.8. Executing OPT_EXPR pass (perform const folding).
|
|
|
|
17.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.46.7. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.7.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
17.46.12. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.12.2. Continuing TECHMAP pass.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
|
|
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
No more expansions possible.
|
|
<suppressed ~205 debug messages>
|
|
|
|
17.46.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
17.46.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
<suppressed ~18 debug messages>
|
|
|
|
17.46.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 59 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
<suppressed ~6 debug messages>
|
|
Removed a total of 2 cells.
|
|
|
|
17.46.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
Removed 0 unused cells and 55 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
17.46.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.46.13.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
17.46.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \spi_neuron_top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
17.46.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \spi_neuron_top.
|
|
Performed a total of 0 changes.
|
|
|
|
17.46.13.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\spi_neuron_top'.
|
|
Computing hashes of 57 cells of `\spi_neuron_top'.
|
|
Finding duplicate cells in `\spi_neuron_top'.
|
|
Removed a total of 0 cells.
|
|
|
|
17.46.13.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
17.46.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \spi_neuron_top..
|
|
|
|
17.46.13.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module spi_neuron_top.
|
|
|
|
17.46.13.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
17.46.14. Executing AIGMAP pass (map logic to AIG).
|
|
Module spi_neuron_top: replaced 18 cells with 120 new cells, skipped 39 cells.
|
|
replaced 3 cell types:
|
|
14 $_MUX_
|
|
2 $_OR_
|
|
2 $_XOR_
|
|
not replaced 3 cell types:
|
|
4 $_AND_
|
|
4 $_NOT_
|
|
31 $specify2
|
|
|
|
17.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
Module spi_neuron_top: replaced 3016 cells with 18064 new cells, skipped 4165 cells.
|
|
replaced 4 cell types:
|
|
1875 $_MUX_
|
|
33 $_ORNOT_
|
|
972 $_OR_
|
|
136 $_XOR_
|
|
not replaced 9 cell types:
|
|
947 $_AND_
|
|
431 $_NOT_
|
|
16 $_TBUF_
|
|
1 $__ABC9_SCC_BREAKER
|
|
19 $scopeinfo
|
|
2408 TRELLIS_FF
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
337 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
|
|
|
|
17.46.15.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.15.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
17.46.15.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 7985 AND gates and 24070 wires from module `spi_neuron_top' to a netlist network with 2503 inputs and 1437 outputs.
|
|
|
|
17.46.15.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
17.46.15.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 2503/ 1437 and = 7305 lev = 21 (1.02) mem = 0.21 MB box = 337 bb = 0
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 2503/ 1437 and = 10225 lev = 36 (0.90) mem = 0.24 MB ch = 1411 box = 337 bb = 0
|
|
ABC: cst = 0 cls = 1168 lit = 1411 unused = 11160 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 10225. Ch = 1168. Total mem = 2.99 MB. Peak cut mem = 0.18 MB.
|
|
ABC: P: Del = 3554.00. Ar = 6009.0. Edge = 8234. Cut = 100769. T = 0.01 sec
|
|
ABC: P: Del = 3554.00. Ar = 5878.0. Edge = 8264. Cut = 100570. T = 0.01 sec
|
|
ABC: P: Del = 3554.00. Ar = 3373.0. Edge = 9686. Cut = 145808. T = 0.02 sec
|
|
ABC: F: Del = 3554.00. Ar = 2664.0. Edge = 8332. Cut = 145884. T = 0.02 sec
|
|
ABC: A: Del = 3554.00. Ar = 2496.0. Edge = 7503. Cut = 139535. T = 0.02 sec
|
|
ABC: A: Del = 3554.00. Ar = 2479.0. Edge = 7442. Cut = 140605. T = 0.02 sec
|
|
ABC: Total time = 0.10 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 2503/ 1437 and = 6793 lev = 22 (0.97) mem = 0.20 MB box = 337 bb = 0
|
|
ABC: Mapping (K=6) : lut = 1940 edge = 7319 lev = 7 (0.51) levB = 20 mem = 0.10 MB
|
|
ABC: LUT = 1940 : 2=235 12.1 % 3=400 20.6 % 4=883 45.5 % 5=415 21.4 % 6=7 0.4 % Ave = 3.77
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.07 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.66 seconds, total: 0.66 seconds
|
|
|
|
17.46.15.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 10761 unused cells and 18250 unused wires.
|
|
|
|
17.46.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 1949
|
|
ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 337
|
|
ABC RESULTS: input signals: 163
|
|
ABC RESULTS: output signals: 447
|
|
<suppressed ~7880 debug messages>
|
|
Removing temp directory.
|
|
|
|
17.46.16. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.46.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.46.16.2. Continuing TECHMAP pass.
|
|
Using template $paramod$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000010 for cells of type $__ABC9_SCC_BREAKER.
|
|
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
|
|
No more expansions possible.
|
|
<suppressed ~355 debug messages>
|
|
Removed 270 unused cells and 28388 unused wires.
|
|
|
|
17.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
17.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
17.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
|
|
Using template $paramod$3c64762f56d2dfc9226156923515f492b69b41a9$lut for cells of type $lut.
|
|
Using template $paramod$fa8852d442134efa381df9456239cde7cc3e31ff$lut for cells of type $lut.
|
|
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut.
|
|
Using template $paramod$7a600c7c913555de59730b8f5bcedb67064faf1d$lut for cells of type $lut.
|
|
Using template $paramod$6ed7ed61521c2ee3ec4e86802248d93207c213e1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
|
|
Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut.
|
|
Using template $paramod$2014354416722209de7d48370ab008bc2278a034$lut for cells of type $lut.
|
|
Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
|
|
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
|
|
Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$fbeae4d13c6561566bb87c819d405873ec370e64$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221$lut for cells of type $lut.
|
|
Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32$lut for cells of type $lut.
|
|
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
|
|
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
|
|
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
|
|
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
|
|
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
|
|
Using template $paramod$a76326805bbb30a33bf46239f93b537676c24ad2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101011 for cells of type $lut.
|
|
Using template $paramod$fee012b92df74541b277e340e6596737f818902d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
|
|
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
|
|
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
|
|
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
|
|
Using template $paramod$a82a699dba54b8465366aeb90aba90d3d29adde0$lut for cells of type $lut.
|
|
Using template $paramod$5f3abb125a0361a143f12eec230ed33f6f988a00$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
|
|
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
|
|
Using template $paramod$3937959babea1e01a60de47d9733889fc1994f6b$lut for cells of type $lut.
|
|
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut.
|
|
Using template $paramod$5cde1509d5af7b31c38525fe119f8286ad8e474a$lut for cells of type $lut.
|
|
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
|
|
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a$lut for cells of type $lut.
|
|
Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut.
|
|
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
|
|
Using template $paramod$1a36cdd01c31a8831aa99b9e16c9846e7b0b4244$lut for cells of type $lut.
|
|
Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457$lut for cells of type $lut.
|
|
Using template $paramod$6036593eb6f7d1618fdaa514fe11339bec63f433$lut for cells of type $lut.
|
|
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
|
|
Using template $paramod$e8ed3122d39260aca8a6cf0a3f6bedd6d4a55c1c$lut for cells of type $lut.
|
|
Using template $paramod$0f28f6a8fd20b6590010dae0d0b075a4900ef2e8$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
|
|
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54$lut for cells of type $lut.
|
|
Using template $paramod$531bd6df6335d16c70c0928f2e46cf731b8632e1$lut for cells of type $lut.
|
|
Using template $paramod$98a9970df30a64e873b3a211ed4991e1d5a9df62$lut for cells of type $lut.
|
|
Using template $paramod$dbbe0ea5aadf61e5da6ebbf1f47442d5facdca4e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110111 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
|
|
Using template $paramod$d9bb8a5ad37488281c0a8124fa86886fb1fb5a26$lut for cells of type $lut.
|
|
Using template $paramod$17d4fb2077cb7df6fab11c907c67b6f08f6e17ae$lut for cells of type $lut.
|
|
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut.
|
|
Using template $paramod$af4bc2a77e08a2bcfb751a0b02b8f9398359979b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
|
|
Using template $paramod$b009a0fae8aa5fc053a3b4418ccbf60a5eb404de$lut for cells of type $lut.
|
|
Using template $paramod$106b4d877d926f41bd5171be21de0765aec0f89c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$335de092ac977e67dfc6a726b48f2c00b6134ff7$lut for cells of type $lut.
|
|
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
|
|
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa$lut for cells of type $lut.
|
|
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5$lut for cells of type $lut.
|
|
Using template $paramod$11426815751623871d46bc9f1667ef33eaf7eced$lut for cells of type $lut.
|
|
Using template $paramod$78690c1692b93b4a0082cdeddbe8f5cfc4a8578a$lut for cells of type $lut.
|
|
Using template $paramod$ba018320c09b6ecbdc95fc97480f4fe931c8f33f$lut for cells of type $lut.
|
|
Using template $paramod$e3a75b2081c6a7009d08311bf36359c39658675e$lut for cells of type $lut.
|
|
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625$lut for cells of type $lut.
|
|
Using template $paramod$5ce0414f30742591cfbc3ba73903b522793ddcd1$lut for cells of type $lut.
|
|
Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957$lut for cells of type $lut.
|
|
Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36$lut for cells of type $lut.
|
|
Using template $paramod$dc7fe7b055198a3ffe2a80dbf766f8cd0a3967fb$lut for cells of type $lut.
|
|
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
|
|
Using template $paramod$1d37fad81d5c3a064596f39fb11fa0c240200089$lut for cells of type $lut.
|
|
Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$f4e3e92a4c91ccc38cbcadd03ed0b5769fbf8483$lut for cells of type $lut.
|
|
Using template $paramod$26582a7543f385ddf0816d466b3062a20d272771$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
|
|
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4$lut for cells of type $lut.
|
|
Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66$lut for cells of type $lut.
|
|
Using template $paramod$7f1c32e84a484762a42537f3470f578565adc487$lut for cells of type $lut.
|
|
Using template $paramod$c804510587673ea9effea3633f70afe50850f176$lut for cells of type $lut.
|
|
Using template $paramod$25f748a39f13f638a0dd44b265e145242e43bbc5$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
|
|
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
|
|
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
|
|
Using template $paramod$b384dc73c0775b5f6f92a9b94aaf5890a74d4097$lut for cells of type $lut.
|
|
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut.
|
|
Using template $paramod$81df3b5b0c68f16cd64a76012a4213a1b5a86efa$lut for cells of type $lut.
|
|
Using template $paramod$1cabbe2f17ea824b0f9f091fd1dc13fff0b3a362$lut for cells of type $lut.
|
|
Using template $paramod$bf60f6ec407ee294958b6566514fc3125ec42258$lut for cells of type $lut.
|
|
Using template $paramod$8fb7c2a4174bbb0f9870bcb831d0cc7f5057f41f$lut for cells of type $lut.
|
|
Using template $paramod$05388f6cdb1572017f337ba60c14834d386356de$lut for cells of type $lut.
|
|
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288$lut for cells of type $lut.
|
|
Using template $paramod$ae847b3caa0d009b4b5d7e5047ef425662ce7a78$lut for cells of type $lut.
|
|
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut.
|
|
Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a$lut for cells of type $lut.
|
|
Using template $paramod$777f8c6c5912804953e2e0af9194699e173126cb$lut for cells of type $lut.
|
|
Using template $paramod$f5b8268b2e9222869d8eb8fa3606231b8d88f53c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
|
|
Using template $paramod$8e7b1ec7df4c8852d827365421a6d41e55bd7752$lut for cells of type $lut.
|
|
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
|
|
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
|
|
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab$lut for cells of type $lut.
|
|
Using template $paramod$586c733dbc02946b45f42f2c47b72245f8e1ca79$lut for cells of type $lut.
|
|
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882$lut for cells of type $lut.
|
|
Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut.
|
|
Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe$lut for cells of type $lut.
|
|
Using template $paramod$9df5a7460fc82bf83284092438a969af70687bc1$lut for cells of type $lut.
|
|
Using template $paramod$b1ad129c42aaca4070b325f0c13303eb3b71a97f$lut for cells of type $lut.
|
|
Using template $paramod$5f892cbccc8e0b846db30004f6a576906c92120c$lut for cells of type $lut.
|
|
Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut.
|
|
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa$lut for cells of type $lut.
|
|
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae$lut for cells of type $lut.
|
|
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut.
|
|
Using template $paramod$3bbb1d881728ec3cbdf98daa7cd6d7f9983b91cf$lut for cells of type $lut.
|
|
Using template $paramod$01f38dafe767eff3b774c3e1f729826d7239b804$lut for cells of type $lut.
|
|
Using template $paramod$bb7be8bae5c143932e2a0774e60657333fd7fa30$lut for cells of type $lut.
|
|
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
|
|
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a$lut for cells of type $lut.
|
|
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
|
|
Using template $paramod$50ae037bea16070af222263fc6c06efd57346ae1$lut for cells of type $lut.
|
|
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5$lut for cells of type $lut.
|
|
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut.
|
|
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288$lut for cells of type $lut.
|
|
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7$lut for cells of type $lut.
|
|
Using template $paramod$fedcddf7a4357754b8c2c1b3c873f3560b924a39$lut for cells of type $lut.
|
|
Using template $paramod$e6049326c8634f79a905c381bb150ca718b543fa$lut for cells of type $lut.
|
|
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut.
|
|
Using template $paramod$64e1675646af51b8b9f3d2c775231ae6d3d93c28$lut for cells of type $lut.
|
|
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e$lut for cells of type $lut.
|
|
Using template $paramod$8c6086e5ec3e9c40cf78aa00b56d8032c461f06e$lut for cells of type $lut.
|
|
Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a$lut for cells of type $lut.
|
|
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
|
|
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e$lut for cells of type $lut.
|
|
Using template $paramod$c95600c22d16130655f2a86bbcbf5f6580781063$lut for cells of type $lut.
|
|
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d$lut for cells of type $lut.
|
|
Using template $paramod$01efcb95fbb77a39361bfe0d84053cbb9d694b4d$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
|
|
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae$lut for cells of type $lut.
|
|
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
|
|
Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593$lut for cells of type $lut.
|
|
Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca$lut for cells of type $lut.
|
|
Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99$lut for cells of type $lut.
|
|
Using template $paramod$b1c1fcc81573437ec158d7c629938862148f7151$lut for cells of type $lut.
|
|
Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844$lut for cells of type $lut.
|
|
Using template $paramod$81906bba7c7bc0c001a9126392aee02e4576c282$lut for cells of type $lut.
|
|
Using template $paramod$29442795ef2e10dd90e3826e90a6d7a832893bba$lut for cells of type $lut.
|
|
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6$lut for cells of type $lut.
|
|
Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3$lut for cells of type $lut.
|
|
Using template $paramod$3fd3cd243a8b2f71b0ffe04bdaebf6ad83bcc78e$lut for cells of type $lut.
|
|
Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a$lut for cells of type $lut.
|
|
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut.
|
|
Using template $paramod$f09f8b6cd4e5ceeddd06811b7669f05eb21b8588$lut for cells of type $lut.
|
|
Using template $paramod$8702d826849a5d8af6dd5fde2d287a6443f7d076$lut for cells of type $lut.
|
|
Using template $paramod$210534b73e432a1d89abd2ae048c31c7f92e6092$lut for cells of type $lut.
|
|
Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
|
|
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe$lut for cells of type $lut.
|
|
Using template $paramod$4e79aa6839e287ee36e65fa83c13a532a028e9cd$lut for cells of type $lut.
|
|
Using template $paramod$053427f7f5ea07d59a8194fc808f0dbdb8dee48b$lut for cells of type $lut.
|
|
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a$lut for cells of type $lut.
|
|
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut.
|
|
Using template $paramod$b2b81edcc33c34b1742d2b2203de8702a40e7379$lut for cells of type $lut.
|
|
Using template $paramod$1a95e0da14fff355d7b4438b7358c951bbb08ccd$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000010 for cells of type $lut.
|
|
Using template $paramod$636489ee6fd9daecee952e374b74ebd4427c62b5$lut for cells of type $lut.
|
|
Using template $paramod$a06aa83841491819ea0cf939b57a7ccfb595b114$lut for cells of type $lut.
|
|
Using template $paramod$9d12c15405e25608417ce779d7fe1b86619365f9$lut for cells of type $lut.
|
|
Using template $paramod$3a75385b1beb239786b9fcdc898b53110e63595f$lut for cells of type $lut.
|
|
Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a$lut for cells of type $lut.
|
|
Using template $paramod$1c754ba6cd627f95a67755b75121c1464d98e70e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
|
|
Using template $paramod$45d35c067ded9854bad436d064758afc38659286$lut for cells of type $lut.
|
|
Using template $paramod$3830fbfbec2ed4d6e3e957e17e4fca97b7adef1f$lut for cells of type $lut.
|
|
Using template $paramod$c68110307ed3a83d1f1d050a34218c458bce2221$lut for cells of type $lut.
|
|
Using template $paramod$6e1e2bf7f29cfe416c0ceb4dc5c676edd2a3b996$lut for cells of type $lut.
|
|
Using template $paramod$d4eb44f3690efb0690fba5d80d7c0d2451788719$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
|
|
Using template $paramod$af763bca85949884aefa417266a961f9c91132de$lut for cells of type $lut.
|
|
Using template $paramod$52adc4306ced619ca2f6304c7a7bbf71ea42dfec$lut for cells of type $lut.
|
|
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0$lut for cells of type $lut.
|
|
Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
|
|
Using template $paramod$e4b9bd705416a24da0fb7793aacf194000cd6ca6$lut for cells of type $lut.
|
|
Using template $paramod$1e47b2c82141d6a54f09852fad33b92b9763040f$lut for cells of type $lut.
|
|
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut.
|
|
Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70$lut for cells of type $lut.
|
|
Using template $paramod$0fa351d24d2713ce0a93e46f5deedd65d95d22b8$lut for cells of type $lut.
|
|
Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut.
|
|
Using template $paramod$88a379586ab99d22384fb6ffdcafb4a7aae8da78$lut for cells of type $lut.
|
|
Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd$lut for cells of type $lut.
|
|
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4$lut for cells of type $lut.
|
|
Using template $paramod$9e1fa2a48cac7b80d58300c7804ce9961cdcaf51$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
|
|
Using template $paramod$b5d3eaa79e8ae5fc4f942c81743f0f041feba584$lut for cells of type $lut.
|
|
Using template $paramod$69cd07689187c617289e4eda75b267345c09f795$lut for cells of type $lut.
|
|
Using template $paramod$b0b3d981c9cc41298f8aa80b0631edc9e96e9ee1$lut for cells of type $lut.
|
|
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
|
|
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut.
|
|
Using template $paramod$f34ee2b561b7f8245a58821fcd23f3045c85a295$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
|
|
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf$lut for cells of type $lut.
|
|
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f$lut for cells of type $lut.
|
|
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut.
|
|
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f$lut for cells of type $lut.
|
|
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf$lut for cells of type $lut.
|
|
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e$lut for cells of type $lut.
|
|
Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
|
|
Using template $paramod$ce02e2afa3256c1c2c45460d429171d794707fae$lut for cells of type $lut.
|
|
Using template $paramod$691e5d89fa42ac31086ffa9583f01739cd14cecd$lut for cells of type $lut.
|
|
Using template $paramod$e5477ee47846ce208224b9029657ffd8771566cb$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut.
|
|
Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe$lut for cells of type $lut.
|
|
Using template $paramod$98ffdcdc6435d75b86474998a7f5724549d66b95$lut for cells of type $lut.
|
|
Using template $paramod$45ba34223bc477fab03658827a2250be76f4b28a$lut for cells of type $lut.
|
|
Using template $paramod$2c246cd08c72c8cf6aea47f63b2e084e20fb0c9f$lut for cells of type $lut.
|
|
Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335$lut for cells of type $lut.
|
|
Using template $paramod$6d5ed6b0f166a223a987cdae0f9a10556ce66e78$lut for cells of type $lut.
|
|
Using template $paramod$0857f03ebe0e8d4abd6c55e5543fde44f1f71c8e$lut for cells of type $lut.
|
|
Using template $paramod$b68652ca9b7474a10a2fedc6d524fe681d4b7aad$lut for cells of type $lut.
|
|
Using template $paramod$8a77a4b825e7cd0e2a0cbe1bb8ec99794d7f5906$lut for cells of type $lut.
|
|
Using template $paramod$f969aefcb5fdd29444244ce17e4806b1ebc6f568$lut for cells of type $lut.
|
|
Using template $paramod$9c20013182155af3d3efdd49fa8397638e437d7d$lut for cells of type $lut.
|
|
Using template $paramod$0498819220bb36cfd5ba6facabe8eab892920bd6$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
|
|
Using template $paramod$97208951e215f90b4f6395abe0e3212702ec5317$lut for cells of type $lut.
|
|
Using template $paramod$4c062300547baeb0db28d20d7e66bbb462805fa5$lut for cells of type $lut.
|
|
Using template $paramod$612412a04fc41e3dc386343f81ddab13974190c3$lut for cells of type $lut.
|
|
Using template $paramod$2179d3bc72bf0dec4b560f3c7f432f7901bacb58$lut for cells of type $lut.
|
|
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
|
|
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~5570 debug messages>
|
|
|
|
17.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in spi_neuron_top.
|
|
Optimizing lut $abc$67003$lut$aiger$o4392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o4296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9152.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4608.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9858.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9424.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8547.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9369.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$10010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7268.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3435.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o4298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7201.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7625.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8796.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4420.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o3922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4479.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o3260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9142.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger$o4020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6862.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7205.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9033.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$6081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o4113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger$o4113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$4747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$5586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger$o3525.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
|
|
Optimizing lut $abc$67003$lut$aiger67002$7448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$8604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $abc$67003$lut$aiger67002$9007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger67002$3645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $abc$67003$lut$aiger$o3059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$67010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Removed 0 unused cells and 4554 unused wires.
|
|
|
|
17.49. Executing AUTONAME pass.
|
|
Renamed 8187 objects in module spi_neuron_top.
|
|
<suppressed ~8187 debug messages>
|
|
|
|
17.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `spi_neuron_top'. Setting top module to spi_neuron_top.
|
|
|
|
17.50.1. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
|
|
17.50.2. Analyzing design hierarchy..
|
|
Top module: \spi_neuron_top
|
|
Removed 0 unused modules.
|
|
|
|
17.51. Printing statistics.
|
|
|
|
=== spi_neuron_top ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
3199 wires
|
|
13323 wire bits
|
|
3199 public wires
|
|
13323 public wire bits
|
|
16 ports
|
|
53 port bits
|
|
41 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
5566 submodules
|
|
337 CCU2C
|
|
7 L6MUX21
|
|
2385 LUT4
|
|
429 PFUMX
|
|
2408 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
41 spi_neuron_top
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
3199 wires
|
|
13323 wire bits
|
|
3199 public wires
|
|
13323 public wire bits
|
|
16 ports
|
|
53 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
41 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
2 DP16KD
|
|
4 MULT18X18D
|
|
5566 submodules
|
|
337 CCU2C
|
|
7 L6MUX21
|
|
2385 LUT4
|
|
429 PFUMX
|
|
2408 TRELLIS_FF
|
|
|
|
17.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module spi_neuron_top...
|
|
Found and reported 0 problems.
|
|
|
|
17.53. Executing JSON backend.
|
|
|
|
18. Printing statistics.
|
|
|
|
=== spi_neuron_top ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
3199 wires
|
|
13323 wire bits
|
|
3199 public wires
|
|
13323 public wire bits
|
|
16 ports
|
|
53 port bits
|
|
5607 cells
|
|
16 $_TBUF_
|
|
19 $scopeinfo
|
|
337 CCU2C
|
|
2 DP16KD
|
|
7 L6MUX21
|
|
2385 LUT4
|
|
4 MULT18X18D
|
|
429 PFUMX
|
|
2408 TRELLIS_FF
|
|
|
|
Warnings: 1 unique messages, 1 total
|
|
End of script. Logfile hash: fa9b0ee137, time: 2.33s, user: 1.71s, system: 0.07s, MEM: 163.53 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 27% 1x abc9_exe (0 sec), 12% 12x techmap (0 sec), ...
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