micheleandClaude Sonnet 5
27cf5f36da
Before building N=4/8/16 core scaling, did the requested full analysis. Real finding: using measured DDR3 throughput (1.24 GB/s, from the actual EXP-0079 JEDEC trace) against calculated compute-side need (4.96 GB/s for one core at peak DSP throughput, given the current activation memory layout's 2x byte overhead), the system is memory-bandwidth-bound already at N=1/N=2, not DSP-bound (only 6.67% DSP used). Scaling core count today would show no real throughput gain. docs/ARCHITECTURE_ANALYSIS.md: full module review + ranked interventions -- result-writeback engine (blocker), denser activation packing (highest-leverage bandwidth fix), then the user's own proposed DDRManager/orchestrator-prefetch idea (design-sketched, grounded in neural_director_packed.v's existing job queue, explicitly scoped as complementary to denser packing, not a substitute for it), THEN N-scaling with real per-N P&R signoff. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC