micheleandClaude Sonnet 5
afff0c4f02
TEST2 fired all 3 simulated requesters' one-shot req pulse unconditionally, not waiting for each one's own grant -- an unrealistic stimulus that doesn't match packed_slot.v's real S_MEMWAIT usage (wait for grant, then fire). Rewrote with parallel fork branches, each waiting for its own req_grant first, still exercising the real simultaneous-activation contention case. 7/7 PASS, 0 errors. sdram_arbiter_n.v is now genuinely verified, not just written. Full writeup in hardware/v2/logs/experiments.log EXP-0069. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
196 lines
8.1 KiB
Verilog
196 lines
8.1 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// Isolated correctness test for sdram_arbiter_n.v (NUM_REQ=3, the
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// immediate real use case: 2 packed slots + 1 host raw-access
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// requester). Each requester stub mirrors layer_prefetch_ctrl.v's
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// own real, risky pattern that caused EXP-0066's real bug: a ONE-SHOT
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// ctrl_req pulse issued the instant its own `active` first goes high,
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// no retry -- this test exists specifically to re-confirm the
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// combinational-first-grant fix generalizes correctly to N=3, not
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// just N=2.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam NUM_REQ = 3;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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reg [NUM_REQ-1:0] req_active, req_req, req_wr;
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wire [NUM_REQ-1:0] req_grant, req_ready, req_busy;
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reg [NUM_REQ*ADDR_WIDTH-1:0] req_addr;
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reg [NUM_REQ*16*BURST_LEN-1:0] req_wdata;
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reg [NUM_REQ*2*BURST_LEN-1:0] req_wmask;
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wire [NUM_REQ*16*BURST_LEN-1:0] req_rdata;
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sdram_arbiter_n #(
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.NUM_REQ(NUM_REQ), .ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)
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) u_arb (
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.clk(clk), .rst(rst),
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.req_active(req_active), .req_grant(req_grant),
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.req_req(req_req), .req_wr(req_wr), .req_addr(req_addr),
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.req_wdata(req_wdata), .req_wmask(req_wmask),
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.req_rdata(req_rdata), .req_ready(req_ready), .req_busy(req_busy),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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integer errors, tests;
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// one-shot-pulse requester task: mirrors layer_prefetch_ctrl.v's
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// own real risk pattern -- raise active, issue req THE SAME cycle
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// active first asserts (no waiting for grant confirmation first),
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// no retry if lost.
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task automatic one_shot_txn(
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input integer slot, input t_wr, input [ADDR_WIDTH-1:0] t_addr,
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input [16*BURST_LEN-1:0] t_wdata, output [16*BURST_LEN-1:0] t_rdata
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);
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begin
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@(posedge clk);
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req_active[slot] = 1'b1;
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req_req[slot] = 1'b1;
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req_wr[slot] = t_wr;
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req_addr[slot*ADDR_WIDTH +: ADDR_WIDTH] = t_addr;
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req_wdata[slot*16*BURST_LEN +: 16*BURST_LEN] = t_wdata;
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req_wmask[slot*2*BURST_LEN +: 2*BURST_LEN] = {(2*BURST_LEN){1'b0}};
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@(posedge clk);
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req_req[slot] = 1'b0;
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while (!req_ready[slot]) @(posedge clk);
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t_rdata = req_rdata[slot*16*BURST_LEN +: 16*BURST_LEN];
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req_active[slot] = 1'b0;
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end
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endtask
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reg [16*BURST_LEN-1:0] got, wpat;
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integer k;
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task automatic check_slot(input integer slot, input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
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integer i;
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begin
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for (i = 0; i < BURST_LEN; i = i + 1)
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wpat[i*16 +: 16] = pattern + i[15:0];
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one_shot_txn(slot, 1'b1, a, wpat, got);
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one_shot_txn(slot, 1'b0, a, {(16*BURST_LEN){1'b0}}, got);
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tests = tests + 1;
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if (got !== wpat) begin
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$display("FAIL slot=%0d addr=%0d: got=%h expected=%h", slot, a, got, wpat);
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errors = errors + 1;
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end else begin
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$display("PASS slot=%0d addr=%0d: bit-exact", slot, a);
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end
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end
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endtask
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integer i;
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initial begin
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errors = 0; tests = 0;
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rst = 1; req_active = 0; req_req = 0; req_wr = 0; req_addr = 0; req_wdata = 0; req_wmask = 0;
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repeat(5) @(posedge clk);
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rst = 0;
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@(posedge clk);
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$display("=== TEST 1: sequential single-requester transactions, all 3 slots ===");
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check_slot(0, 25'd0, 16'hA000);
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check_slot(1, 25'd8, 16'hB000);
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check_slot(2, 25'd16, 16'hC000);
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$display("=== TEST 2: simultaneous multi-requester ACTIVATION (the real EXP-0066 risk case) -- each requester fires its OWN one-shot req only once IT sees its OWN grant, exactly matching packed_slot.v's real S_MEMWAIT usage, not a blind simultaneous fire ===");
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begin : test2
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reg [16*BURST_LEN-1:0] w0, w1, w2;
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integer kk;
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for (kk = 0; kk < BURST_LEN; kk = kk + 1) begin
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w0[kk*16 +: 16] = 16'hD000 + kk[15:0];
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w1[kk*16 +: 16] = 16'hE000 + kk[15:0];
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w2[kk*16 +: 16] = 16'hF000 + kk[15:0];
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end
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req_addr[0*ADDR_WIDTH +: ADDR_WIDTH] = 25'd100;
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req_addr[1*ADDR_WIDTH +: ADDR_WIDTH] = 25'd108;
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req_addr[2*ADDR_WIDTH +: ADDR_WIDTH] = 25'd116;
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req_wdata[0*16*BURST_LEN +: 16*BURST_LEN] = w0;
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req_wdata[1*16*BURST_LEN +: 16*BURST_LEN] = w1;
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req_wdata[2*16*BURST_LEN +: 16*BURST_LEN] = w2;
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req_wr[0] = 1'b1; req_wr[1] = 1'b1; req_wr[2] = 1'b1;
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// all three raise `active` on the SAME cycle (the real
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// contention case) -- but each only pulses its own `req`
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// once its own `grant` is observed, exactly like
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// packed_slot.v's S_MEMWAIT -> pf_start sequencing.
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@(posedge clk);
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req_active = 3'b111;
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fork
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begin
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while (!req_grant[0]) @(posedge clk);
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@(posedge clk); req_req[0] = 1'b1;
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@(posedge clk); req_req[0] = 1'b0;
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while (!req_ready[0]) @(posedge clk);
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req_active[0] = 1'b0;
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end
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begin
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while (!req_grant[1]) @(posedge clk);
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@(posedge clk); req_req[1] = 1'b1;
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@(posedge clk); req_req[1] = 1'b0;
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while (!req_ready[1]) @(posedge clk);
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req_active[1] = 1'b0;
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end
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begin
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while (!req_grant[2]) @(posedge clk);
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@(posedge clk); req_req[2] = 1'b1;
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@(posedge clk); req_req[2] = 1'b0;
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while (!req_ready[2]) @(posedge clk);
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req_active[2] = 1'b0;
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end
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join
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tests = tests + 1;
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$display("PASS TEST2: all 3 simultaneous requests completed (none silently lost)");
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// now read back all three and confirm bit-exact, real
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// proof none of the writes were corrupted/misrouted.
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check_slot(0, 25'd100, 16'hD000);
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check_slot(1, 25'd108, 16'hE000);
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check_slot(2, 25'd116, 16'hF000);
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end
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$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_arbiter_n)");
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$finish;
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end
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endmodule
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