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FPGA-Neural/sim/spi_slave.vcd
T
michele 233d6ff7fb feat: complete Phase 5 multi-layer network (RUN_NETWORK) + fix STATUS race 
Wires the already-present layer_sequencer.v into the SPI stack:

- spi_engine.v: RUN_NETWORK opcode (0x23) + SET_BASE selectors for
  table_base/buf_a_base/buf_b_base; STATUS.busy/done extended to
  track the sequencer (seq_busy/seq_done) alongside neuron_memory
  directly, so done latches on the last layer only.
- spi_neuron_top.v: instantiates layer_sequencer, muxes
  neuron_memory's control inputs between it (while seq_busy) and
  spi_engine's direct-drive path (legacy single-layer mode), wires
  the sequencer's own RAM master to mem_arbiter's Port C.

Found and fixed a real race while writing the end-to-end test: STATUS's
sticky/clear-on-read done bit read its value live/combinationally
during transmission and cleared unconditionally on any STATUS read.
A done_event landing mid-transmission of a STATUS response byte could
be silently dropped -- the host would receive a stale byte while the
sticky bit was cleared regardless, hanging any host polling STATUS in
a loop. Present since Phase 4, not RUN_NETWORK-specific; only
surfaced under this test's continuous polling. Fixed by latching a
status_snapshot at opcode-accept time and gating the clear on what
was actually transmitted.

Tests: spi_engine_tb.v gains RUN_NETWORK/SET_BASE opcode tests (K/L);
new layer_sequencer_tb.v unit-tests the sequencer FSM directly
(descriptor table, ping-pong buffer addressing, byte-exact copy-out);
new spi_neuron_top_runnetwork_tb.v drives a real 2-layer network over
simulated SPI end to end (real neuron_memory + PSRAM, hand-computed
expected output) and confirms the legacy single-layer path still
works afterward. All existing testbenches still pass.
2026-09-02 19:47:36 +02:00

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$date
Wed Sep 2 19:00:18 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 1 ! tx_byte_req $end
$var wire 1 " rx_valid $end
$var wire 8 # rx_byte [7:0] $end
$var wire 1 $ miso $end
$var wire 1 % cs_start $end
$var wire 1 & cs_end $end
$var wire 1 ' cs_active $end
$var real 1 ( CLK_PERIOD $end
$var reg 1 ) clk $end
$var reg 1 * cs_n $end
$var reg 1 + mosi $end
$var reg 1 , rst $end
$var reg 8 - rx_tmp [7:0] $end
$var reg 1 . sclk $end
$var reg 8 / tx_byte [7:0] $end
$var integer 32 0 cs_end_count [31:0] $end
$var integer 32 1 cs_start_count [31:0] $end
$var integer 32 2 errors [31:0] $end
$var integer 32 3 errors_before [31:0] $end
$var integer 32 4 rx_log_len [31:0] $end
$var integer 32 5 tx_queue_idx [31:0] $end
$var integer 32 6 tx_queue_len [31:0] $end
$scope module dut $end
$var wire 1 ) clk $end
$var wire 1 ' cs_active $end
$var wire 1 7 cs_fell $end
$var wire 1 * cs_n $end
$var wire 1 8 cs_rose $end
$var wire 1 + mosi $end
$var wire 1 , rst $end
$var wire 1 . sclk $end
$var wire 1 9 sclk_fall $end
$var wire 1 : sclk_rise $end
$var wire 8 ; tx_byte [7:0] $end
$var wire 1 < sclk_s $end
$var wire 1 = mosi_s $end
$var wire 1 > cs_n_s $end
$var reg 3 ? bit_count [2:0] $end
$var reg 1 & cs_end $end
$var reg 1 @ cs_n_prev $end
$var reg 3 A cs_n_sync [2:0] $end
$var reg 1 % cs_start $end
$var reg 1 $ miso $end
$var reg 3 B mosi_sync [2:0] $end
$var reg 8 C rx_byte [7:0] $end
$var reg 8 D rx_shift [7:0] $end
$var reg 1 " rx_valid $end
$var reg 1 E sclk_prev $end
$var reg 3 F sclk_sync [2:0] $end
$var reg 1 ! tx_byte_req $end
$var reg 8 G tx_shift [7:0] $end
$upscope $end
$scope task clk_wait $end
$var integer 32 H k [31:0] $end
$var integer 32 I n [31:0] $end
$upscope $end
$scope task spi_begin $end
$var integer 32 J half_bit_cycles [31:0] $end
$upscope $end
$scope task spi_end $end
$var integer 32 K half_bit_cycles [31:0] $end
$upscope $end
$scope task spi_xfer_byte $end
$var reg 8 L rx [7:0] $end
$var reg 8 M rx_acc [7:0] $end
$var reg 8 N tx [7:0] $end
$var integer 32 O half_bit_cycles [31:0] $end
$var integer 32 P i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
r12.5 (
$end
#0
$dumpvars
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#27287500
0)
#27293750
b1100 H
1)
#27300000
0)
#27306250
b1101 H
1)
#27312500
0)
#27318750
b1110 H
1)
#27325000
0)
#27331250
b1111 H
1)
#27337500
0)
#27343750
b10000 H
1)
#27350000
0)
#27356250
b10001 H
1)
#27362500
0)
#27368750
b10010 H
1)
#27375000
0)
#27381250
b10011 H
1)
#27387500
0)
#27393750
b101000 I
b10100 K
b1011010 -
b1011010 L
b11111111111111111111111111111111 P
b0 H
1)
#27400000
0)
#27406250
b1 H
1)
#27412500
0)
#27418750
b10 H
1)
#27425000
0)
#27431250
b11 H
1)
#27437500
0)
#27443750
b100 H
1)
#27450000
0)
#27456250
b101 H
1)
#27462500
0)
#27468750
b110 H
1)
#27475000
0)
#27481250
b111 H
1)
#27487500
0)
#27493750
b1000 H
1)
#27500000
0)
#27506250
b1001 H
1)
#27512500
0)
#27518750
b1010 H
1)
#27525000
0)
#27531250
b1011 H
1)
#27537500
0)
#27543750
b1100 H
1)
#27550000
0)
#27556250
b1101 H
1)
#27562500
0)
#27568750
b1110 H
1)
#27575000
0)
#27581250
b1111 H
1)
#27587500
0)
#27593750
b10000 H
1)
#27600000
0)
#27606250
b10001 H
1)
#27612500
0)
#27618750
b10010 H
1)
#27625000
0)
#27631250
b10011 H
1)
#27637500
0)
#27643750
b10100 H
1)
#27650000
0)
#27656250
b10101 H
1)
#27662500
0)
#27668750
b10110 H
1)
#27675000
0)
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b10111 H
1)
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0)
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b11000 H
1)
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0)
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b11001 H
1)
#27712500
0)
#27718750
b11010 H
1)
#27725000
0)
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b11011 H
1)
#27737500
0)
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b11100 H
1)
#27750000
0)
#27756250
b11101 H
1)
#27762500
0)
#27768750
b11110 H
1)
#27775000
0)
#27781250
b11111 H
1)
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0)
#27793750
b100000 H
1)
#27800000
0)
#27806250
b100001 H
1)
#27812500
0)
#27818750
b100010 H
1)
#27825000
0)
#27831250
b100011 H
1)
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0)
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b100100 H
1)
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0)
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b100101 H
1)
#27862500
0)
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b100110 H
1)
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0)
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b100111 H
1)
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0)
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1*
b0 H
1)
#27900000
0)
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b1 A
b1 H
1)
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0)
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b11 A
b10 H
1)
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0)
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0'
18
1>
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b11 H
1)
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0)
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08
1&
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1)
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0)
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0&
b1 0
b101 H
1)
#27962500
0)
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b110 H
1)
#27975000
0)
#27981250
b111 H
1)
#27987500
0)
#27993750
b1000 H
1)
#28000000
0)
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b1001 H
1)
#28012500
0)
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b1010 H
1)
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0)
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b1011 H
1)
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0)
#28043750
b1100 H
1)
#28050000
0)
#28056250
b1101 H
1)
#28062500
0)
#28068750
b1110 H
1)
#28075000
0)
#28081250
b1111 H
1)
#28087500
0)
#28093750
b10000 H
1)
#28100000
0)
#28106250
b10001 H
1)
#28112500
0)
#28118750
b10010 H
1)
#28125000
0)
#28131250
b10011 H
1)
#28137500
0)
#28143750
b10100 H
1)
#28150000
0)
#28156250
b10101 H
1)
#28162500
0)
#28168750
b10110 H
1)
#28175000
0)
#28181250
b10111 H
1)
#28187500
0)
#28193750
b11000 H
1)
#28200000
0)
#28206250
b11001 H
1)
#28212500
0)
#28218750
b11010 H
1)
#28225000
0)
#28231250
b11011 H
1)
#28237500
0)
#28243750
b11100 H
1)
#28250000
0)
#28256250
b11101 H
1)
#28262500
0)
#28268750
b11110 H
1)
#28275000
0)
#28281250
b11111 H
1)
#28287500
0)
#28293750
b100000 H
1)
#28300000
0)
#28306250
b100001 H
1)
#28312500
0)
#28318750
b100010 H
1)
#28325000
0)
#28331250
b100011 H
1)
#28337500
0)
#28343750
b100100 H
1)
#28350000
0)
#28356250
b100101 H
1)
#28362500
0)
#28368750
b100110 H
1)
#28375000
0)
#28381250
b100111 H
1)
#28387500
0)
#28393750
b101000 H
1)
#28400000
0)
#28406250
1)
#28412500
0)
#28418750
1)
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