michele
233d6ff7fb
Wires the already-present layer_sequencer.v into the SPI stack: - spi_engine.v: RUN_NETWORK opcode (0x23) + SET_BASE selectors for table_base/buf_a_base/buf_b_base; STATUS.busy/done extended to track the sequencer (seq_busy/seq_done) alongside neuron_memory directly, so done latches on the last layer only. - spi_neuron_top.v: instantiates layer_sequencer, muxes neuron_memory's control inputs between it (while seq_busy) and spi_engine's direct-drive path (legacy single-layer mode), wires the sequencer's own RAM master to mem_arbiter's Port C. Found and fixed a real race while writing the end-to-end test: STATUS's sticky/clear-on-read done bit read its value live/combinationally during transmission and cleared unconditionally on any STATUS read. A done_event landing mid-transmission of a STATUS response byte could be silently dropped -- the host would receive a stale byte while the sticky bit was cleared regardless, hanging any host polling STATUS in a loop. Present since Phase 4, not RUN_NETWORK-specific; only surfaced under this test's continuous polling. Fixed by latching a status_snapshot at opcode-accept time and gating the clear on what was actually transmitted. Tests: spi_engine_tb.v gains RUN_NETWORK/SET_BASE opcode tests (K/L); new layer_sequencer_tb.v unit-tests the sequencer FSM directly (descriptor table, ping-pong buffer addressing, byte-exact copy-out); new spi_neuron_top_runnetwork_tb.v drives a real 2-layer network over simulated SPI end to end (real neuron_memory + PSRAM, hand-computed expected output) and confirms the legacy single-layer path still works afterward. All existing testbenches still pass.
1465 lines
13 KiB
Plaintext
1465 lines
13 KiB
Plaintext
$date
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Wed Sep 2 19:00:18 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 1 ! seq_done $end
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$var wire 1 " seq_busy $end
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$var wire 1 # ram_wr $end
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$var wire 8 $ ram_wdata [7:0] $end
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$var wire 1 % ram_req $end
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$var wire 22 & ram_addr [21:0] $end
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$var wire 22 ' nm_x_base [21:0] $end
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$var wire 22 ( nm_w_base [21:0] $end
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$var wire 1 ) nm_start $end
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$var wire 22 * nm_bias_addr [21:0] $end
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$var parameter 32 + ADDR_WIDTH $end
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$var parameter 22 , BUF_A_BASE $end
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$var parameter 22 - BUF_B_BASE $end
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$var real 1 . CLK_PERIOD $end
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$var parameter 32 / DATA_WIDTH $end
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$var parameter 22 0 L0_BIAS_ADDR $end
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$var parameter 22 1 L0_W_BASE $end
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$var parameter 22 2 L1_BIAS_ADDR $end
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$var parameter 22 3 L1_W_BASE $end
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$var parameter 32 4 N_LAYERS $end
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$var parameter 32 5 N_WIDTH $end
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$var parameter 1 6 RAM_IDLE $end
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$var parameter 1 7 RAM_WAIT $end
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$var parameter 22 8 TABLE_BASE $end
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$var parameter 22 9 X_BASE $end
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$var reg 22 : buf_a_base [21:0] $end
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$var reg 22 ; buf_b_base [21:0] $end
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$var reg 1 < clk $end
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$var reg 1 = nm_busy $end
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$var reg 1 > nm_done $end
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$var reg 22 ? ram_addr_latched [21:0] $end
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$var reg 8 @ ram_rdata [7:0] $end
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$var reg 1 A ram_ready $end
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$var reg 1 B ram_state $end
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$var reg 8 C ram_wdata_latched [7:0] $end
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$var reg 1 D ram_wr_latched $end
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$var reg 1 E rst $end
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$var reg 8 F run_num_layers [7:0] $end
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$var reg 1 G run_start $end
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$var reg 1 H seq_busy_dropped_early $end
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$var reg 32 I staged_y [31:0] $end
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$var reg 22 J table_base [21:0] $end
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$var reg 22 K x_base [21:0] $end
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$var reg 32 L y_bus [31:0] $end
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$var integer 32 M errors [31:0] $end
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$var integer 32 N errors_before [31:0] $end
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$var integer 32 O i [31:0] $end
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$var integer 32 P nm_delay [31:0] $end
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$var integer 32 Q seq_done_count [31:0] $end
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$scope module u_dut $end
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$var wire 22 R buf_a_base [21:0] $end
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$var wire 22 S buf_b_base [21:0] $end
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$var wire 1 < clk $end
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$var wire 1 = nm_busy $end
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$var wire 1 > nm_done $end
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$var wire 8 T ram_rdata [7:0] $end
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$var wire 1 A ram_ready $end
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$var wire 1 E rst $end
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$var wire 8 U run_num_layers [7:0] $end
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$var wire 1 G run_start $end
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$var wire 22 V table_base [21:0] $end
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$var wire 22 W x_base [21:0] $end
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$var wire 32 X y_bus [31:0] $end
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$var parameter 32 Y ADDR_WIDTH $end
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$var parameter 32 Z DATA_WIDTH $end
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$var parameter 32 [ N_LAYERS $end
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$var parameter 32 \ N_WIDTH $end
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$var parameter 4 ] ST_COPY_ISSUE $end
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$var parameter 4 ^ ST_COPY_WAIT $end
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$var parameter 4 _ ST_IDLE $end
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$var parameter 4 ` ST_READ_DESC $end
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$var parameter 4 a ST_READ_WAIT $end
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$var parameter 4 b ST_START_LAYER $end
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$var parameter 4 c ST_WAIT_LAYER $end
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$var reg 24 d bias_addr_acc [23:0] $end
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$var reg 3 e copy_idx [2:0] $end
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$var reg 1 f cur_sel $end
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$var reg 3 g desc_byte_idx [2:0] $end
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$var reg 22 h desc_table_addr [21:0] $end
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$var reg 8 i layer_idx [7:0] $end
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$var reg 22 j nm_bias_addr [21:0] $end
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$var reg 1 ) nm_start $end
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$var reg 22 k nm_w_base [21:0] $end
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$var reg 22 l nm_x_base [21:0] $end
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$var reg 8 m num_layers_reg [7:0] $end
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$var reg 22 n ram_addr [21:0] $end
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$var reg 1 % ram_req $end
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$var reg 8 o ram_wdata [7:0] $end
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$var reg 1 # ram_wr $end
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$var reg 1 " seq_busy $end
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$var reg 1 ! seq_done $end
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$var reg 4 p state [3:0] $end
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$var reg 24 q w_base_acc [23:0] $end
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$var reg 1 r write_sel $end
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$upscope $end
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$scope task clk_wait $end
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$var integer 32 s k [31:0] $end
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$var integer 32 t n [31:0] $end
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$upscope $end
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$scope task report $end
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$var reg 512 u label [511:0] $end
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$upscope $end
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$scope task stage_layer_output $end
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$var reg 32 v val [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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