micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
106 lines
3.4 KiB
Markdown
106 lines
3.4 KiB
Markdown
# netasm
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Host-side assembler for the FPGA-Neural network engine. Compiles a
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small pseudo-assembly description of a network (dense Type #1 or
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sparse-graph Type #2, see the project spec §9) into:
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- the exact on-disk byte layout (descriptor table + edge blocks,
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spec §4), and
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- the SPI command sequence (`SET_NET_TYPE` / `SET_BASE` / `WRITE_RAM`
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/ `RUN_NETWORK`) needed to load and start it.
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This is **host tooling only**. Nothing here runs on the FPGA — see
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`rtl/graph_engine.v` and `rtl/spi_engine.v` for the hardware side of
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this protocol.
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## Grammar
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```
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; Tipo #1 (dense)
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NET dense
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INPUTS 256
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LAYER 64 relu
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LAYER 16 relu
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LAYER 4 none
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END
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```
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```
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; Tipo #2 (graph)
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NET graph
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INPUTS 4 ; id 0..3
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NEURON n4 relu bias=2
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CONN 0 w=5
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CONN 1 w=-3
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NEURON n5 none bias=0
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CONN n4 w=2 ; symbolic reference to n4's output
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CONN 2 w=7
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OUTPUT n5
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END
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```
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`;` starts a comment that runs to end of line. A `CONN <src> w=<int>`
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source is either a bare decimal id (typically one of the network's
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inputs) or the name of a previously declared `NEURON`.
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For `NET dense`, only layer **sizes** and activations are declared —
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weight/bias **values** come from a trained model and are loaded by
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the host separately (unchanged `WRITE_RAM` flow); netasm's job there
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is layout (address allocation, PARALLEL-alignment validation,
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descriptor table, load/run commands).
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For `NET graph`, netasm assigns every neuron's signal id (inputs get
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0..N_in-1; every `OUTPUT` neuron is guaranteed the highest ids, as
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required by spec §4.4 — reordering non-output neurons is never
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needed for correctness since the grammar already forces
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before-you-use declaration order), resolves symbolic `CONN`
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references, pads each neuron's edge list to a `PARALLEL` multiple
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with zero-weight edges (spec §2.6 — this is a full, physical
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edge block, not a hint: hardware just streams `n_conn_padded` real
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bytes from PSRAM), and emits the descriptor table + edge blocks +
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load/run command sequence.
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## Compile-time validation
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Catches these before the runtime load-time guard in
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`rtl/graph_engine.v` ever would (spec §9's whole point):
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- `src_id < out_id` (no cycles / forward references)
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- `src_id`, `out_id` < `N_TOTAL`
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- an `OUTPUT` neuron is never used as another neuron's source
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- every `CONN` reference (symbolic or literal) resolves to a real id
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- a neuron's *padded* connection count fits the hardware's
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build-time `MAX_CONN`
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- (dense) every layer's real input count is a `PARALLEL` multiple
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## Usage
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```
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python3 tools/netasm/cli.py <input.netasm> -o <out_prefix> \
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[--parallel 8] [--max-conn 32] [--n-total 4096] \
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[--table-base 0x...] [--edges-base 0x...] [--x-base 0x...] \
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[--out-base 0x...] [--buf-b-base 0x...] [--weights-base 0x...]
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```
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Produces:
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- `<out_prefix>.frames.bin` — length-prefixed SPI transaction bytes
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(2-byte big-endian length + that many payload bytes, repeated); a
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host driver replays each record by asserting CS, shifting the
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bytes out, then deasserting CS.
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- `<out_prefix>.debug.txt` — human-readable id/address/byte dump for
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review before flashing real hardware.
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See `examples/graph_example.netasm` and `examples/dense_example.netasm`.
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## Tests
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```
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python3 tools/netasm/tests/test_netasm.py -v
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```
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Includes a byte-exact test against the same worked graph example
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used throughout the RTL testbenches (`sim/graph_format_tb.v`,
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`sim/graph_engine_tb.v`, `sim/spi_neuron_top_graph_tb.v`), plus one
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test per compile-time guard above.
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