micheleandClaude Sonnet 5
20b0b1f4c0
mac_unit.v: exhaustive unit test (all 65536 (x,w) combinations at DATA_WIDTH=8, plus 486 boundary acc_in vectors) against an independent Python oracle (tools/validation/mac_oracle.py). 66022/66022 match, 0 reserves. mac8.v: first-ever dedicated unit test (previously only indirect coverage at whatever single PARALLEL neuron_parallel_tb.v happens to use). Verified at PARALLEL=2/8/32 with structural adversarial vectors (catches swapped/duplicated tree wiring), 300 random INT8 pairs per PARALLEL with realistic accumulating acc_in, and worst-case magnitude adversarial vectors. 939/939 match. Confirms BUG-002 (N_INPUTS=0 bypasses the N_INPUTS%PARALLEL elaboration guard) is real, on both simulation and real Yosys synthesis -- root cause: [DATA_WIDTH*N_INPUTS-1:0] becomes [-1:0] for N_INPUTS=0, which both tools treat as a genuine 2-bit undriven vector rather than collapsing to zero width. Includes a documented self-correction: the first verification attempt produced a false "hang" using an invalid one-shot late check of a single-cycle done pulse -- caught by reproducing the same false result on a known-good sanity config before trusting it. Full regression re-run clean after adding 3 new testbenches: 36/36 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1585 lines
28 KiB
Plaintext
1585 lines
28 KiB
Plaintext
$date
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Fri Sep 4 13:40:25 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 8 ! y [7:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 2 % ACT_NONE $end
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$var parameter 2 & ACT_RELU $end
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$var parameter 32 ' DATA_WIDTH $end
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$var parameter 32 ( N_INPUTS $end
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$var parameter 32 ) PARALLEL $end
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$var reg 2 * activation [1:0] $end
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$var reg 8 + bias [7:0] $end
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$var reg 1 , clk $end
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$var reg 16 - n_inputs_real [15:0] $end
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$var reg 1 . rst $end
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$var reg 1 / start $end
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$var reg 256 0 w_bus [255:0] $end
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$var reg 256 1 x_bus [255:0] $end
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$var integer 32 2 cycles_full [31:0] $end
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$var integer 32 3 cycles_reduced [31:0] $end
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$var integer 32 4 errors [31:0] $end
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$var integer 32 5 i [31:0] $end
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$var integer 32 6 t_done [31:0] $end
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$var integer 32 7 t_start [31:0] $end
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$scope module dut $end
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$var wire 2 8 activation [1:0] $end
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$var wire 8 9 bias [7:0] $end
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$var wire 1 , clk $end
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$var wire 1 : final_acc_in_range $end
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$var wire 1 ; final_acc_le_zero $end
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$var wire 1 < final_acc_upper_all0 $end
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$var wire 16 = n_inputs_real [15:0] $end
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$var wire 1 . rst $end
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$var wire 1 / start $end
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$var wire 256 > w_bus [255:0] $end
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$var wire 256 ? x_bus [255:0] $end
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$var wire 8 @ y_relu [7:0] $end
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$var wire 8 A y_none [7:0] $end
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$var wire 64 B x_group [63:0] $end
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$var wire 64 C w_group [63:0] $end
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$var wire 16 D groups_real [15:0] $end
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$var wire 1 E final_acc_upper_all1 $end
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$var wire 1 F final_acc_sign $end
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$var wire 32 G final_acc [31:0] $end
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$var wire 32 H bias_ext [31:0] $end
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$var wire 32 I acc_next [31:0] $end
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$var parameter 32 J ACC_WIDTH $end
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$var parameter 2 K ACT_NONE $end
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$var parameter 2 L ACT_RELU $end
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$var parameter 32 M DATA_WIDTH $end
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$var parameter 32 N GROUPS $end
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$var parameter 32 O GROUP_INDEX_WIDTH $end
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$var parameter 32 P N_INPUTS $end
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$var parameter 32 Q PARALLEL $end
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$var reg 32 R acc [31:0] $end
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$var reg 1 # busy $end
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$var reg 1 " done $end
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$var reg 1 S finishing $end
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$var reg 2 T group_index [1:0] $end
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$var reg 8 U y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 V acc_in [31:0] $end
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$var wire 64 W w_bus [63:0] $end
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$var wire 64 X x_bus [63:0] $end
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$var wire 32 Y acc_out [31:0] $end
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$var parameter 32 Z ACC_WIDTH $end
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$var parameter 32 [ DATA_WIDTH $end
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$var parameter 32 \ PARALLEL $end
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$var parameter 32 ] TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 ^ i $end
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$scope module u_mac $end
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$var wire 32 _ acc_in [31:0] $end
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$var wire 8 ` w [7:0] $end
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$var wire 8 a x [7:0] $end
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$var wire 32 b product_ext [31:0] $end
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$var wire 16 c product [15:0] $end
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$var wire 32 d acc_out [31:0] $end
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$var parameter 32 e ACC_WIDTH $end
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$var parameter 32 f DATA_WIDTH $end
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$var parameter 64 g PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 h i $end
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$scope module u_mac $end
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$var wire 32 i acc_in [31:0] $end
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$var wire 8 j w [7:0] $end
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$var wire 8 k x [7:0] $end
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$var wire 32 l product_ext [31:0] $end
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$var wire 16 m product [15:0] $end
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$var wire 32 n acc_out [31:0] $end
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$var parameter 32 o ACC_WIDTH $end
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$var parameter 32 p DATA_WIDTH $end
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$var parameter 64 q PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 r i $end
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$scope module u_mac $end
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$var wire 32 s acc_in [31:0] $end
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$var wire 8 t w [7:0] $end
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$var wire 8 u x [7:0] $end
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$var wire 32 v product_ext [31:0] $end
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$var wire 16 w product [15:0] $end
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$var wire 32 x acc_out [31:0] $end
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$var parameter 32 y ACC_WIDTH $end
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$var parameter 32 z DATA_WIDTH $end
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$var parameter 64 { PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 | i $end
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$scope module u_mac $end
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$var wire 32 } acc_in [31:0] $end
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$var wire 8 ~ w [7:0] $end
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$var wire 8 !" x [7:0] $end
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$var wire 32 "" product_ext [31:0] $end
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$var wire 16 #" product [15:0] $end
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$var wire 32 $" acc_out [31:0] $end
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$var parameter 32 %" ACC_WIDTH $end
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$var parameter 32 &" DATA_WIDTH $end
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$var parameter 64 '" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 (" i $end
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$scope module u_mac $end
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$var wire 32 )" acc_in [31:0] $end
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$var wire 8 *" w [7:0] $end
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$var wire 8 +" x [7:0] $end
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$var wire 32 ," product_ext [31:0] $end
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$var wire 16 -" product [15:0] $end
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$var wire 32 ." acc_out [31:0] $end
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$var parameter 32 /" ACC_WIDTH $end
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$var parameter 32 0" DATA_WIDTH $end
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$var parameter 64 1" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 2" i $end
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$scope module u_mac $end
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$var wire 32 3" acc_in [31:0] $end
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$var wire 8 4" w [7:0] $end
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$var wire 8 5" x [7:0] $end
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$var wire 32 6" product_ext [31:0] $end
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$var wire 16 7" product [15:0] $end
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$var wire 32 8" acc_out [31:0] $end
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$var parameter 32 9" ACC_WIDTH $end
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$var parameter 32 :" DATA_WIDTH $end
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$var parameter 64 ;" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 <" i $end
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$scope module u_mac $end
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$var wire 32 =" acc_in [31:0] $end
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$var wire 8 >" w [7:0] $end
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$var wire 8 ?" x [7:0] $end
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$var wire 32 @" product_ext [31:0] $end
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$var wire 16 A" product [15:0] $end
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$var wire 32 B" acc_out [31:0] $end
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$var parameter 32 C" ACC_WIDTH $end
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$var parameter 32 D" DATA_WIDTH $end
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$var parameter 64 E" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 F" i $end
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$scope module u_mac $end
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$var wire 32 G" acc_in [31:0] $end
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$var wire 8 H" w [7:0] $end
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$var wire 8 I" x [7:0] $end
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$var wire 32 J" product_ext [31:0] $end
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$var wire 16 K" product [15:0] $end
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$var wire 32 L" acc_out [31:0] $end
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$var parameter 32 M" ACC_WIDTH $end
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$var parameter 32 N" DATA_WIDTH $end
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$var parameter 64 O" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 P" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 Q" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 R" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 S" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 T" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[5] $end
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$var parameter 4 U" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[6] $end
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$var parameter 4 V" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[7] $end
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$var parameter 4 W" i $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[0] $end
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$var parameter 2 X" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 Y" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 Z" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 [" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 \" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[1] $end
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$var parameter 2 ]" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 ^" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 _" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[2] $end
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$var parameter 3 `" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 a" node $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope task run_neuron $end
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$upscope $end
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$scope task test_1 $end
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$upscope $end
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$scope task test_2 $end
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$upscope $end
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$scope task test_3 $end
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$upscope $end
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$scope task test_4 $end
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$upscope $end
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$scope task test_5 $end
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$upscope $end
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$scope task test_6 $end
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$upscope $end
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$scope task test_7 $end
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$var reg 1 b" pass_7 $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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b0 a"
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b1 Z"
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b111 W"
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b110 V"
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b11 S"
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b100000 M"
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$end
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#0
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$dumpvars
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bx I"
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$end
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#5000
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b11111111111111111111111111111100 l
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b100 I
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b100 Y
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b110 b
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b1111111111111100 m
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b11111111 j
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b110 c
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b10 `
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b11 a
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b1 G
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b1 H
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b11111111100000010 C
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b11111111100000010 W
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b11111111100000010 0
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b11111111100000010 >
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b100000010000000011 B
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