micheleandClaude Sonnet 5
20b0b1f4c0
mac_unit.v: exhaustive unit test (all 65536 (x,w) combinations at DATA_WIDTH=8, plus 486 boundary acc_in vectors) against an independent Python oracle (tools/validation/mac_oracle.py). 66022/66022 match, 0 reserves. mac8.v: first-ever dedicated unit test (previously only indirect coverage at whatever single PARALLEL neuron_parallel_tb.v happens to use). Verified at PARALLEL=2/8/32 with structural adversarial vectors (catches swapped/duplicated tree wiring), 300 random INT8 pairs per PARALLEL with realistic accumulating acc_in, and worst-case magnitude adversarial vectors. 939/939 match. Confirms BUG-002 (N_INPUTS=0 bypasses the N_INPUTS%PARALLEL elaboration guard) is real, on both simulation and real Yosys synthesis -- root cause: [DATA_WIDTH*N_INPUTS-1:0] becomes [-1:0] for N_INPUTS=0, which both tools treat as a genuine 2-bit undriven vector rather than collapsing to zero width. Includes a documented self-correction: the first verification attempt produced a false "hang" using an invalid one-shot late check of a single-cycle done pulse -- caught by reproducing the same false result on a known-good sanity config before trusting it. Full regression re-run clean after adding 3 new testbenches: 36/36 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
4080 lines
77 KiB
Plaintext
4080 lines
77 KiB
Plaintext
$date
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Fri Sep 4 13:40:17 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 64 ! y_bus [63:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 32 % DATA_WIDTH $end
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$var parameter 32 & N_INPUTS $end
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$var parameter 32 ' N_NEURONS $end
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$var parameter 32 ( PARALLEL $end
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$var reg 64 ) bias_bus [63:0] $end
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$var reg 1 * clk $end
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$var reg 1 + rst $end
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$var reg 1 , start $end
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$var reg 2048 - weights_bus [2047:0] $end
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$var reg 256 . x_bus [255:0] $end
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$var integer 32 / errors [31:0] $end
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$var integer 32 0 i [31:0] $end
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$scope module dut $end
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$var wire 64 1 bias_bus [63:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 2048 2 weights_bus [2047:0] $end
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$var wire 256 3 x_bus [255:0] $end
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$var wire 64 4 y_bus [63:0] $end
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$var wire 8 5 neuron_done [7:0] $end
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$var wire 8 6 neuron_busy [7:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 7 ACC_WIDTH $end
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$var parameter 32 8 DATA_WIDTH $end
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$var parameter 32 9 N_INPUTS $end
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$var parameter 32 : N_NEURONS $end
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$var parameter 32 ; PARALLEL $end
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$scope begin GEN_NEURON[0] $end
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$var parameter 2 < n $end
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$scope module u_neuron $end
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$var wire 2 = activation [1:0] $end
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$var wire 8 > bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 ? final_acc_in_range $end
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$var wire 1 @ final_acc_le_zero $end
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$var wire 1 A final_acc_upper_all0 $end
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$var wire 16 B n_inputs_real [15:0] $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 256 C w_bus [255:0] $end
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$var wire 256 D x_bus [255:0] $end
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$var wire 8 E y_relu [7:0] $end
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$var wire 8 F y_none [7:0] $end
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$var wire 64 G x_group [63:0] $end
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$var wire 64 H w_group [63:0] $end
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$var wire 16 I groups_real [15:0] $end
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$var wire 1 J final_acc_upper_all1 $end
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$var wire 1 K final_acc_sign $end
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$var wire 32 L final_acc [31:0] $end
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$var wire 32 M bias_ext [31:0] $end
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$var wire 32 N acc_next [31:0] $end
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$var parameter 32 O ACC_WIDTH $end
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$var parameter 2 P ACT_NONE $end
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$var parameter 2 Q ACT_RELU $end
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$var parameter 32 R DATA_WIDTH $end
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$var parameter 32 S GROUPS $end
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$var parameter 32 T GROUP_INDEX_WIDTH $end
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$var parameter 32 U N_INPUTS $end
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$var parameter 32 V PARALLEL $end
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$var reg 32 W acc [31:0] $end
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$var reg 1 X busy $end
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$var reg 1 Y done $end
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$var reg 1 Z finishing $end
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$var reg 2 [ group_index [1:0] $end
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$var reg 8 \ y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 ] acc_in [31:0] $end
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$var wire 64 ^ w_bus [63:0] $end
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$var wire 64 _ x_bus [63:0] $end
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$var wire 32 ` acc_out [31:0] $end
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$var parameter 32 a ACC_WIDTH $end
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$var parameter 32 b DATA_WIDTH $end
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$var parameter 32 c PARALLEL $end
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$var parameter 32 d TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 e i $end
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$scope module u_mac $end
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$var wire 32 f acc_in [31:0] $end
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$var wire 8 g w [7:0] $end
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$var wire 8 h x [7:0] $end
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$var wire 32 i product_ext [31:0] $end
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$var wire 16 j product [15:0] $end
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$var wire 32 k acc_out [31:0] $end
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$var parameter 32 l ACC_WIDTH $end
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$var parameter 32 m DATA_WIDTH $end
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$var parameter 64 n PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 o i $end
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$scope module u_mac $end
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$var wire 32 p acc_in [31:0] $end
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$var wire 8 q w [7:0] $end
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$var wire 8 r x [7:0] $end
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$var wire 32 s product_ext [31:0] $end
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$var wire 16 t product [15:0] $end
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$var wire 32 u acc_out [31:0] $end
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$var parameter 32 v ACC_WIDTH $end
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$var parameter 32 w DATA_WIDTH $end
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$var parameter 64 x PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 y i $end
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$scope module u_mac $end
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$var wire 32 z acc_in [31:0] $end
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$var wire 8 { w [7:0] $end
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$var wire 8 | x [7:0] $end
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$var wire 32 } product_ext [31:0] $end
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$var wire 16 ~ product [15:0] $end
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$var wire 32 !" acc_out [31:0] $end
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$var parameter 32 "" ACC_WIDTH $end
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$var parameter 32 #" DATA_WIDTH $end
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$var parameter 64 $" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 %" i $end
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$scope module u_mac $end
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$var wire 32 &" acc_in [31:0] $end
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$var wire 8 '" w [7:0] $end
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$var wire 8 (" x [7:0] $end
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$var wire 32 )" product_ext [31:0] $end
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$var wire 16 *" product [15:0] $end
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$var wire 32 +" acc_out [31:0] $end
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$var parameter 32 ," ACC_WIDTH $end
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$var parameter 32 -" DATA_WIDTH $end
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$var parameter 64 ." PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 /" i $end
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$scope module u_mac $end
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$var wire 32 0" acc_in [31:0] $end
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$var wire 8 1" w [7:0] $end
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$var wire 8 2" x [7:0] $end
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$var wire 32 3" product_ext [31:0] $end
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$var wire 16 4" product [15:0] $end
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$var wire 32 5" acc_out [31:0] $end
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$var parameter 32 6" ACC_WIDTH $end
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$var parameter 32 7" DATA_WIDTH $end
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$var parameter 64 8" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 9" i $end
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$scope module u_mac $end
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$var wire 32 :" acc_in [31:0] $end
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$var wire 8 ;" w [7:0] $end
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$var wire 8 <" x [7:0] $end
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$var wire 32 =" product_ext [31:0] $end
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$var wire 16 >" product [15:0] $end
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$var wire 32 ?" acc_out [31:0] $end
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$var parameter 32 @" ACC_WIDTH $end
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$var parameter 32 A" DATA_WIDTH $end
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$var parameter 64 B" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 C" i $end
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$scope module u_mac $end
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$var wire 32 D" acc_in [31:0] $end
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$var wire 8 E" w [7:0] $end
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$var wire 8 F" x [7:0] $end
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$var wire 32 G" product_ext [31:0] $end
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$var wire 16 H" product [15:0] $end
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$var wire 32 I" acc_out [31:0] $end
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$var parameter 32 J" ACC_WIDTH $end
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$var parameter 32 K" DATA_WIDTH $end
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$var parameter 64 L" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 M" i $end
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$scope module u_mac $end
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$var wire 32 N" acc_in [31:0] $end
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$var wire 8 O" w [7:0] $end
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$var wire 8 P" x [7:0] $end
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$var wire 32 Q" product_ext [31:0] $end
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$var wire 16 R" product [15:0] $end
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$var wire 32 S" acc_out [31:0] $end
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$var parameter 32 T" ACC_WIDTH $end
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$var parameter 32 U" DATA_WIDTH $end
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$var parameter 64 V" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 W" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 X" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 Y" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 Z" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 [" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[5] $end
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$var parameter 4 \" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[6] $end
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$var parameter 4 ]" i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[7] $end
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$var parameter 4 ^" i $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[0] $end
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$var parameter 2 _" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 `" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 a" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 b" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 c" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[1] $end
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$var parameter 2 d" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 e" node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 f" node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[2] $end
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$var parameter 3 g" level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 h" node $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin GEN_NEURON[1] $end
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$var parameter 2 i" n $end
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$scope module u_neuron $end
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$var wire 2 j" activation [1:0] $end
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$var wire 8 k" bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 l" final_acc_in_range $end
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$var wire 1 m" final_acc_le_zero $end
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$var wire 1 n" final_acc_upper_all0 $end
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$var wire 16 o" n_inputs_real [15:0] $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 256 p" w_bus [255:0] $end
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$var wire 256 q" x_bus [255:0] $end
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$var wire 8 r" y_relu [7:0] $end
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$var wire 8 s" y_none [7:0] $end
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$var wire 64 t" x_group [63:0] $end
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$var wire 64 u" w_group [63:0] $end
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$var wire 16 v" groups_real [15:0] $end
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$var wire 1 w" final_acc_upper_all1 $end
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$var wire 1 x" final_acc_sign $end
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$var wire 32 y" final_acc [31:0] $end
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$var wire 32 z" bias_ext [31:0] $end
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$var wire 32 {" acc_next [31:0] $end
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$var parameter 32 |" ACC_WIDTH $end
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$var parameter 2 }" ACT_NONE $end
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$var parameter 2 ~" ACT_RELU $end
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$var parameter 32 !# DATA_WIDTH $end
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$var parameter 32 "# GROUPS $end
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$var parameter 32 ## GROUP_INDEX_WIDTH $end
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$var parameter 32 $# N_INPUTS $end
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$var parameter 32 %# PARALLEL $end
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$var reg 32 &# acc [31:0] $end
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$var reg 1 '# busy $end
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$var reg 1 (# done $end
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$var reg 1 )# finishing $end
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$var reg 2 *# group_index [1:0] $end
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$var reg 8 +# y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 ,# acc_in [31:0] $end
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$var wire 64 -# w_bus [63:0] $end
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$var wire 64 .# x_bus [63:0] $end
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$var wire 32 /# acc_out [31:0] $end
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$var parameter 32 0# ACC_WIDTH $end
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$var parameter 32 1# DATA_WIDTH $end
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$var parameter 32 2# PARALLEL $end
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$var parameter 32 3# TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 4# i $end
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$scope module u_mac $end
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$var wire 32 5# acc_in [31:0] $end
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$var wire 8 6# w [7:0] $end
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$var wire 8 7# x [7:0] $end
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$var wire 32 8# product_ext [31:0] $end
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$var wire 16 9# product [15:0] $end
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$var wire 32 :# acc_out [31:0] $end
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$var parameter 32 ;# ACC_WIDTH $end
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$var parameter 32 <# DATA_WIDTH $end
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$var parameter 64 =# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 ># i $end
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$scope module u_mac $end
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$var wire 32 ?# acc_in [31:0] $end
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$var wire 8 @# w [7:0] $end
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$var wire 8 A# x [7:0] $end
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$var wire 32 B# product_ext [31:0] $end
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$var wire 16 C# product [15:0] $end
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$var wire 32 D# acc_out [31:0] $end
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$var parameter 32 E# ACC_WIDTH $end
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$var parameter 32 F# DATA_WIDTH $end
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$var parameter 64 G# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 H# i $end
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$scope module u_mac $end
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$var wire 32 I# acc_in [31:0] $end
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$var wire 8 J# w [7:0] $end
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$var wire 8 K# x [7:0] $end
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$var wire 32 L# product_ext [31:0] $end
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$var wire 16 M# product [15:0] $end
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$var wire 32 N# acc_out [31:0] $end
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$var parameter 32 O# ACC_WIDTH $end
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$var parameter 32 P# DATA_WIDTH $end
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$var parameter 64 Q# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 R# i $end
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$scope module u_mac $end
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$var wire 32 S# acc_in [31:0] $end
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$var wire 8 T# w [7:0] $end
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$var wire 8 U# x [7:0] $end
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$var wire 32 V# product_ext [31:0] $end
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$var wire 16 W# product [15:0] $end
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$var wire 32 X# acc_out [31:0] $end
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$var parameter 32 Y# ACC_WIDTH $end
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$var parameter 32 Z# DATA_WIDTH $end
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$var parameter 64 [# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 \# i $end
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$scope module u_mac $end
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$var wire 32 ]# acc_in [31:0] $end
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$var wire 8 ^# w [7:0] $end
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$var wire 8 _# x [7:0] $end
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$var wire 32 `# product_ext [31:0] $end
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$var wire 16 a# product [15:0] $end
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$var wire 32 b# acc_out [31:0] $end
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$var parameter 32 c# ACC_WIDTH $end
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$var parameter 32 d# DATA_WIDTH $end
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$var parameter 64 e# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 f# i $end
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$scope module u_mac $end
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$var wire 32 g# acc_in [31:0] $end
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$var wire 8 h# w [7:0] $end
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$var wire 8 i# x [7:0] $end
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$var wire 32 j# product_ext [31:0] $end
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$var wire 16 k# product [15:0] $end
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$var wire 32 l# acc_out [31:0] $end
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$var parameter 32 m# ACC_WIDTH $end
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$var parameter 32 n# DATA_WIDTH $end
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$var parameter 64 o# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 p# i $end
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$scope module u_mac $end
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$var wire 32 q# acc_in [31:0] $end
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$var wire 8 r# w [7:0] $end
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$var wire 8 s# x [7:0] $end
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$var wire 32 t# product_ext [31:0] $end
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$var wire 16 u# product [15:0] $end
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$var wire 32 v# acc_out [31:0] $end
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$var parameter 32 w# ACC_WIDTH $end
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$var parameter 32 x# DATA_WIDTH $end
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$var parameter 64 y# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 z# i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 {# acc_in [31:0] $end
|
|
$var wire 8 |# w [7:0] $end
|
|
$var wire 8 }# x [7:0] $end
|
|
$var wire 32 ~# product_ext [31:0] $end
|
|
$var wire 16 !$ product [15:0] $end
|
|
$var wire 32 "$ acc_out [31:0] $end
|
|
$var parameter 32 #$ ACC_WIDTH $end
|
|
$var parameter 32 $$ DATA_WIDTH $end
|
|
$var parameter 64 %$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 &$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 '$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 ($ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 )$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 *$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 +$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 ,$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 -$ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 .$ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 /$ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 0$ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 1$ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 2$ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 3$ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 4$ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 5$ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 6$ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 7$ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[2] $end
|
|
$var parameter 3 8$ n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 9$ activation [1:0] $end
|
|
$var wire 8 :$ bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 ;$ final_acc_in_range $end
|
|
$var wire 1 <$ final_acc_le_zero $end
|
|
$var wire 1 =$ final_acc_upper_all0 $end
|
|
$var wire 16 >$ n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 ?$ w_bus [255:0] $end
|
|
$var wire 256 @$ x_bus [255:0] $end
|
|
$var wire 8 A$ y_relu [7:0] $end
|
|
$var wire 8 B$ y_none [7:0] $end
|
|
$var wire 64 C$ x_group [63:0] $end
|
|
$var wire 64 D$ w_group [63:0] $end
|
|
$var wire 16 E$ groups_real [15:0] $end
|
|
$var wire 1 F$ final_acc_upper_all1 $end
|
|
$var wire 1 G$ final_acc_sign $end
|
|
$var wire 32 H$ final_acc [31:0] $end
|
|
$var wire 32 I$ bias_ext [31:0] $end
|
|
$var wire 32 J$ acc_next [31:0] $end
|
|
$var parameter 32 K$ ACC_WIDTH $end
|
|
$var parameter 2 L$ ACT_NONE $end
|
|
$var parameter 2 M$ ACT_RELU $end
|
|
$var parameter 32 N$ DATA_WIDTH $end
|
|
$var parameter 32 O$ GROUPS $end
|
|
$var parameter 32 P$ GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 Q$ N_INPUTS $end
|
|
$var parameter 32 R$ PARALLEL $end
|
|
$var reg 32 S$ acc [31:0] $end
|
|
$var reg 1 T$ busy $end
|
|
$var reg 1 U$ done $end
|
|
$var reg 1 V$ finishing $end
|
|
$var reg 2 W$ group_index [1:0] $end
|
|
$var reg 8 X$ y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 Y$ acc_in [31:0] $end
|
|
$var wire 64 Z$ w_bus [63:0] $end
|
|
$var wire 64 [$ x_bus [63:0] $end
|
|
$var wire 32 \$ acc_out [31:0] $end
|
|
$var parameter 32 ]$ ACC_WIDTH $end
|
|
$var parameter 32 ^$ DATA_WIDTH $end
|
|
$var parameter 32 _$ PARALLEL $end
|
|
$var parameter 32 `$ TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 a$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 b$ acc_in [31:0] $end
|
|
$var wire 8 c$ w [7:0] $end
|
|
$var wire 8 d$ x [7:0] $end
|
|
$var wire 32 e$ product_ext [31:0] $end
|
|
$var wire 16 f$ product [15:0] $end
|
|
$var wire 32 g$ acc_out [31:0] $end
|
|
$var parameter 32 h$ ACC_WIDTH $end
|
|
$var parameter 32 i$ DATA_WIDTH $end
|
|
$var parameter 64 j$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 k$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 l$ acc_in [31:0] $end
|
|
$var wire 8 m$ w [7:0] $end
|
|
$var wire 8 n$ x [7:0] $end
|
|
$var wire 32 o$ product_ext [31:0] $end
|
|
$var wire 16 p$ product [15:0] $end
|
|
$var wire 32 q$ acc_out [31:0] $end
|
|
$var parameter 32 r$ ACC_WIDTH $end
|
|
$var parameter 32 s$ DATA_WIDTH $end
|
|
$var parameter 64 t$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 u$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 v$ acc_in [31:0] $end
|
|
$var wire 8 w$ w [7:0] $end
|
|
$var wire 8 x$ x [7:0] $end
|
|
$var wire 32 y$ product_ext [31:0] $end
|
|
$var wire 16 z$ product [15:0] $end
|
|
$var wire 32 {$ acc_out [31:0] $end
|
|
$var parameter 32 |$ ACC_WIDTH $end
|
|
$var parameter 32 }$ DATA_WIDTH $end
|
|
$var parameter 64 ~$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 !% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 "% acc_in [31:0] $end
|
|
$var wire 8 #% w [7:0] $end
|
|
$var wire 8 $% x [7:0] $end
|
|
$var wire 32 %% product_ext [31:0] $end
|
|
$var wire 16 &% product [15:0] $end
|
|
$var wire 32 '% acc_out [31:0] $end
|
|
$var parameter 32 (% ACC_WIDTH $end
|
|
$var parameter 32 )% DATA_WIDTH $end
|
|
$var parameter 64 *% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 +% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ,% acc_in [31:0] $end
|
|
$var wire 8 -% w [7:0] $end
|
|
$var wire 8 .% x [7:0] $end
|
|
$var wire 32 /% product_ext [31:0] $end
|
|
$var wire 16 0% product [15:0] $end
|
|
$var wire 32 1% acc_out [31:0] $end
|
|
$var parameter 32 2% ACC_WIDTH $end
|
|
$var parameter 32 3% DATA_WIDTH $end
|
|
$var parameter 64 4% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 5% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 6% acc_in [31:0] $end
|
|
$var wire 8 7% w [7:0] $end
|
|
$var wire 8 8% x [7:0] $end
|
|
$var wire 32 9% product_ext [31:0] $end
|
|
$var wire 16 :% product [15:0] $end
|
|
$var wire 32 ;% acc_out [31:0] $end
|
|
$var parameter 32 <% ACC_WIDTH $end
|
|
$var parameter 32 =% DATA_WIDTH $end
|
|
$var parameter 64 >% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 ?% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 @% acc_in [31:0] $end
|
|
$var wire 8 A% w [7:0] $end
|
|
$var wire 8 B% x [7:0] $end
|
|
$var wire 32 C% product_ext [31:0] $end
|
|
$var wire 16 D% product [15:0] $end
|
|
$var wire 32 E% acc_out [31:0] $end
|
|
$var parameter 32 F% ACC_WIDTH $end
|
|
$var parameter 32 G% DATA_WIDTH $end
|
|
$var parameter 64 H% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 I% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 J% acc_in [31:0] $end
|
|
$var wire 8 K% w [7:0] $end
|
|
$var wire 8 L% x [7:0] $end
|
|
$var wire 32 M% product_ext [31:0] $end
|
|
$var wire 16 N% product [15:0] $end
|
|
$var wire 32 O% acc_out [31:0] $end
|
|
$var parameter 32 P% ACC_WIDTH $end
|
|
$var parameter 32 Q% DATA_WIDTH $end
|
|
$var parameter 64 R% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 S% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 T% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 U% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 V% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 W% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 X% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 Y% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 Z% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 [% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 \% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 ]% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 ^% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 _% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 `% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 a% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 b% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 c% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 d% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[3] $end
|
|
$var parameter 3 e% n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 f% activation [1:0] $end
|
|
$var wire 8 g% bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 h% final_acc_in_range $end
|
|
$var wire 1 i% final_acc_le_zero $end
|
|
$var wire 1 j% final_acc_upper_all0 $end
|
|
$var wire 16 k% n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 l% w_bus [255:0] $end
|
|
$var wire 256 m% x_bus [255:0] $end
|
|
$var wire 8 n% y_relu [7:0] $end
|
|
$var wire 8 o% y_none [7:0] $end
|
|
$var wire 64 p% x_group [63:0] $end
|
|
$var wire 64 q% w_group [63:0] $end
|
|
$var wire 16 r% groups_real [15:0] $end
|
|
$var wire 1 s% final_acc_upper_all1 $end
|
|
$var wire 1 t% final_acc_sign $end
|
|
$var wire 32 u% final_acc [31:0] $end
|
|
$var wire 32 v% bias_ext [31:0] $end
|
|
$var wire 32 w% acc_next [31:0] $end
|
|
$var parameter 32 x% ACC_WIDTH $end
|
|
$var parameter 2 y% ACT_NONE $end
|
|
$var parameter 2 z% ACT_RELU $end
|
|
$var parameter 32 {% DATA_WIDTH $end
|
|
$var parameter 32 |% GROUPS $end
|
|
$var parameter 32 }% GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 ~% N_INPUTS $end
|
|
$var parameter 32 !& PARALLEL $end
|
|
$var reg 32 "& acc [31:0] $end
|
|
$var reg 1 #& busy $end
|
|
$var reg 1 $& done $end
|
|
$var reg 1 %& finishing $end
|
|
$var reg 2 && group_index [1:0] $end
|
|
$var reg 8 '& y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 (& acc_in [31:0] $end
|
|
$var wire 64 )& w_bus [63:0] $end
|
|
$var wire 64 *& x_bus [63:0] $end
|
|
$var wire 32 +& acc_out [31:0] $end
|
|
$var parameter 32 ,& ACC_WIDTH $end
|
|
$var parameter 32 -& DATA_WIDTH $end
|
|
$var parameter 32 .& PARALLEL $end
|
|
$var parameter 32 /& TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 0& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 1& acc_in [31:0] $end
|
|
$var wire 8 2& w [7:0] $end
|
|
$var wire 8 3& x [7:0] $end
|
|
$var wire 32 4& product_ext [31:0] $end
|
|
$var wire 16 5& product [15:0] $end
|
|
$var wire 32 6& acc_out [31:0] $end
|
|
$var parameter 32 7& ACC_WIDTH $end
|
|
$var parameter 32 8& DATA_WIDTH $end
|
|
$var parameter 64 9& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 :& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ;& acc_in [31:0] $end
|
|
$var wire 8 <& w [7:0] $end
|
|
$var wire 8 =& x [7:0] $end
|
|
$var wire 32 >& product_ext [31:0] $end
|
|
$var wire 16 ?& product [15:0] $end
|
|
$var wire 32 @& acc_out [31:0] $end
|
|
$var parameter 32 A& ACC_WIDTH $end
|
|
$var parameter 32 B& DATA_WIDTH $end
|
|
$var parameter 64 C& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 D& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 E& acc_in [31:0] $end
|
|
$var wire 8 F& w [7:0] $end
|
|
$var wire 8 G& x [7:0] $end
|
|
$var wire 32 H& product_ext [31:0] $end
|
|
$var wire 16 I& product [15:0] $end
|
|
$var wire 32 J& acc_out [31:0] $end
|
|
$var parameter 32 K& ACC_WIDTH $end
|
|
$var parameter 32 L& DATA_WIDTH $end
|
|
$var parameter 64 M& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 N& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 O& acc_in [31:0] $end
|
|
$var wire 8 P& w [7:0] $end
|
|
$var wire 8 Q& x [7:0] $end
|
|
$var wire 32 R& product_ext [31:0] $end
|
|
$var wire 16 S& product [15:0] $end
|
|
$var wire 32 T& acc_out [31:0] $end
|
|
$var parameter 32 U& ACC_WIDTH $end
|
|
$var parameter 32 V& DATA_WIDTH $end
|
|
$var parameter 64 W& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 X& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Y& acc_in [31:0] $end
|
|
$var wire 8 Z& w [7:0] $end
|
|
$var wire 8 [& x [7:0] $end
|
|
$var wire 32 \& product_ext [31:0] $end
|
|
$var wire 16 ]& product [15:0] $end
|
|
$var wire 32 ^& acc_out [31:0] $end
|
|
$var parameter 32 _& ACC_WIDTH $end
|
|
$var parameter 32 `& DATA_WIDTH $end
|
|
$var parameter 64 a& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 b& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 c& acc_in [31:0] $end
|
|
$var wire 8 d& w [7:0] $end
|
|
$var wire 8 e& x [7:0] $end
|
|
$var wire 32 f& product_ext [31:0] $end
|
|
$var wire 16 g& product [15:0] $end
|
|
$var wire 32 h& acc_out [31:0] $end
|
|
$var parameter 32 i& ACC_WIDTH $end
|
|
$var parameter 32 j& DATA_WIDTH $end
|
|
$var parameter 64 k& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 l& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 m& acc_in [31:0] $end
|
|
$var wire 8 n& w [7:0] $end
|
|
$var wire 8 o& x [7:0] $end
|
|
$var wire 32 p& product_ext [31:0] $end
|
|
$var wire 16 q& product [15:0] $end
|
|
$var wire 32 r& acc_out [31:0] $end
|
|
$var parameter 32 s& ACC_WIDTH $end
|
|
$var parameter 32 t& DATA_WIDTH $end
|
|
$var parameter 64 u& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 v& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 w& acc_in [31:0] $end
|
|
$var wire 8 x& w [7:0] $end
|
|
$var wire 8 y& x [7:0] $end
|
|
$var wire 32 z& product_ext [31:0] $end
|
|
$var wire 16 {& product [15:0] $end
|
|
$var wire 32 |& acc_out [31:0] $end
|
|
$var parameter 32 }& ACC_WIDTH $end
|
|
$var parameter 32 ~& DATA_WIDTH $end
|
|
$var parameter 64 !' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 "' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 #' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 $' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 %' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 &' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 '' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 (' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 )' i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 *' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 +' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 ,' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 -' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 .' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 /' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 0' node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 1' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 2' level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 3' node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[4] $end
|
|
$var parameter 4 4' n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 5' activation [1:0] $end
|
|
$var wire 8 6' bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 7' final_acc_in_range $end
|
|
$var wire 1 8' final_acc_le_zero $end
|
|
$var wire 1 9' final_acc_upper_all0 $end
|
|
$var wire 16 :' n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 ;' w_bus [255:0] $end
|
|
$var wire 256 <' x_bus [255:0] $end
|
|
$var wire 8 =' y_relu [7:0] $end
|
|
$var wire 8 >' y_none [7:0] $end
|
|
$var wire 64 ?' x_group [63:0] $end
|
|
$var wire 64 @' w_group [63:0] $end
|
|
$var wire 16 A' groups_real [15:0] $end
|
|
$var wire 1 B' final_acc_upper_all1 $end
|
|
$var wire 1 C' final_acc_sign $end
|
|
$var wire 32 D' final_acc [31:0] $end
|
|
$var wire 32 E' bias_ext [31:0] $end
|
|
$var wire 32 F' acc_next [31:0] $end
|
|
$var parameter 32 G' ACC_WIDTH $end
|
|
$var parameter 2 H' ACT_NONE $end
|
|
$var parameter 2 I' ACT_RELU $end
|
|
$var parameter 32 J' DATA_WIDTH $end
|
|
$var parameter 32 K' GROUPS $end
|
|
$var parameter 32 L' GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 M' N_INPUTS $end
|
|
$var parameter 32 N' PARALLEL $end
|
|
$var reg 32 O' acc [31:0] $end
|
|
$var reg 1 P' busy $end
|
|
$var reg 1 Q' done $end
|
|
$var reg 1 R' finishing $end
|
|
$var reg 2 S' group_index [1:0] $end
|
|
$var reg 8 T' y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 U' acc_in [31:0] $end
|
|
$var wire 64 V' w_bus [63:0] $end
|
|
$var wire 64 W' x_bus [63:0] $end
|
|
$var wire 32 X' acc_out [31:0] $end
|
|
$var parameter 32 Y' ACC_WIDTH $end
|
|
$var parameter 32 Z' DATA_WIDTH $end
|
|
$var parameter 32 [' PARALLEL $end
|
|
$var parameter 32 \' TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 ]' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ^' acc_in [31:0] $end
|
|
$var wire 8 _' w [7:0] $end
|
|
$var wire 8 `' x [7:0] $end
|
|
$var wire 32 a' product_ext [31:0] $end
|
|
$var wire 16 b' product [15:0] $end
|
|
$var wire 32 c' acc_out [31:0] $end
|
|
$var parameter 32 d' ACC_WIDTH $end
|
|
$var parameter 32 e' DATA_WIDTH $end
|
|
$var parameter 64 f' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 g' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 h' acc_in [31:0] $end
|
|
$var wire 8 i' w [7:0] $end
|
|
$var wire 8 j' x [7:0] $end
|
|
$var wire 32 k' product_ext [31:0] $end
|
|
$var wire 16 l' product [15:0] $end
|
|
$var wire 32 m' acc_out [31:0] $end
|
|
$var parameter 32 n' ACC_WIDTH $end
|
|
$var parameter 32 o' DATA_WIDTH $end
|
|
$var parameter 64 p' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 q' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 r' acc_in [31:0] $end
|
|
$var wire 8 s' w [7:0] $end
|
|
$var wire 8 t' x [7:0] $end
|
|
$var wire 32 u' product_ext [31:0] $end
|
|
$var wire 16 v' product [15:0] $end
|
|
$var wire 32 w' acc_out [31:0] $end
|
|
$var parameter 32 x' ACC_WIDTH $end
|
|
$var parameter 32 y' DATA_WIDTH $end
|
|
$var parameter 64 z' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 {' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 |' acc_in [31:0] $end
|
|
$var wire 8 }' w [7:0] $end
|
|
$var wire 8 ~' x [7:0] $end
|
|
$var wire 32 !( product_ext [31:0] $end
|
|
$var wire 16 "( product [15:0] $end
|
|
$var wire 32 #( acc_out [31:0] $end
|
|
$var parameter 32 $( ACC_WIDTH $end
|
|
$var parameter 32 %( DATA_WIDTH $end
|
|
$var parameter 64 &( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 '( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 (( acc_in [31:0] $end
|
|
$var wire 8 )( w [7:0] $end
|
|
$var wire 8 *( x [7:0] $end
|
|
$var wire 32 +( product_ext [31:0] $end
|
|
$var wire 16 ,( product [15:0] $end
|
|
$var wire 32 -( acc_out [31:0] $end
|
|
$var parameter 32 .( ACC_WIDTH $end
|
|
$var parameter 32 /( DATA_WIDTH $end
|
|
$var parameter 64 0( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 1( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 2( acc_in [31:0] $end
|
|
$var wire 8 3( w [7:0] $end
|
|
$var wire 8 4( x [7:0] $end
|
|
$var wire 32 5( product_ext [31:0] $end
|
|
$var wire 16 6( product [15:0] $end
|
|
$var wire 32 7( acc_out [31:0] $end
|
|
$var parameter 32 8( ACC_WIDTH $end
|
|
$var parameter 32 9( DATA_WIDTH $end
|
|
$var parameter 64 :( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 ;( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 <( acc_in [31:0] $end
|
|
$var wire 8 =( w [7:0] $end
|
|
$var wire 8 >( x [7:0] $end
|
|
$var wire 32 ?( product_ext [31:0] $end
|
|
$var wire 16 @( product [15:0] $end
|
|
$var wire 32 A( acc_out [31:0] $end
|
|
$var parameter 32 B( ACC_WIDTH $end
|
|
$var parameter 32 C( DATA_WIDTH $end
|
|
$var parameter 64 D( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 E( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 F( acc_in [31:0] $end
|
|
$var wire 8 G( w [7:0] $end
|
|
$var wire 8 H( x [7:0] $end
|
|
$var wire 32 I( product_ext [31:0] $end
|
|
$var wire 16 J( product [15:0] $end
|
|
$var wire 32 K( acc_out [31:0] $end
|
|
$var parameter 32 L( ACC_WIDTH $end
|
|
$var parameter 32 M( DATA_WIDTH $end
|
|
$var parameter 64 N( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 O( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 P( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 Q( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 R( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 S( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 T( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 U( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 V( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 W( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 X( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 Y( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 Z( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 [( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 \( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 ]( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 ^( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 _( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 `( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[5] $end
|
|
$var parameter 4 a( n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 b( activation [1:0] $end
|
|
$var wire 8 c( bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 d( final_acc_in_range $end
|
|
$var wire 1 e( final_acc_le_zero $end
|
|
$var wire 1 f( final_acc_upper_all0 $end
|
|
$var wire 16 g( n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 h( w_bus [255:0] $end
|
|
$var wire 256 i( x_bus [255:0] $end
|
|
$var wire 8 j( y_relu [7:0] $end
|
|
$var wire 8 k( y_none [7:0] $end
|
|
$var wire 64 l( x_group [63:0] $end
|
|
$var wire 64 m( w_group [63:0] $end
|
|
$var wire 16 n( groups_real [15:0] $end
|
|
$var wire 1 o( final_acc_upper_all1 $end
|
|
$var wire 1 p( final_acc_sign $end
|
|
$var wire 32 q( final_acc [31:0] $end
|
|
$var wire 32 r( bias_ext [31:0] $end
|
|
$var wire 32 s( acc_next [31:0] $end
|
|
$var parameter 32 t( ACC_WIDTH $end
|
|
$var parameter 2 u( ACT_NONE $end
|
|
$var parameter 2 v( ACT_RELU $end
|
|
$var parameter 32 w( DATA_WIDTH $end
|
|
$var parameter 32 x( GROUPS $end
|
|
$var parameter 32 y( GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 z( N_INPUTS $end
|
|
$var parameter 32 {( PARALLEL $end
|
|
$var reg 32 |( acc [31:0] $end
|
|
$var reg 1 }( busy $end
|
|
$var reg 1 ~( done $end
|
|
$var reg 1 !) finishing $end
|
|
$var reg 2 ") group_index [1:0] $end
|
|
$var reg 8 #) y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 $) acc_in [31:0] $end
|
|
$var wire 64 %) w_bus [63:0] $end
|
|
$var wire 64 &) x_bus [63:0] $end
|
|
$var wire 32 ') acc_out [31:0] $end
|
|
$var parameter 32 () ACC_WIDTH $end
|
|
$var parameter 32 )) DATA_WIDTH $end
|
|
$var parameter 32 *) PARALLEL $end
|
|
$var parameter 32 +) TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 ,) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 -) acc_in [31:0] $end
|
|
$var wire 8 .) w [7:0] $end
|
|
$var wire 8 /) x [7:0] $end
|
|
$var wire 32 0) product_ext [31:0] $end
|
|
$var wire 16 1) product [15:0] $end
|
|
$var wire 32 2) acc_out [31:0] $end
|
|
$var parameter 32 3) ACC_WIDTH $end
|
|
$var parameter 32 4) DATA_WIDTH $end
|
|
$var parameter 64 5) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 6) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 7) acc_in [31:0] $end
|
|
$var wire 8 8) w [7:0] $end
|
|
$var wire 8 9) x [7:0] $end
|
|
$var wire 32 :) product_ext [31:0] $end
|
|
$var wire 16 ;) product [15:0] $end
|
|
$var wire 32 <) acc_out [31:0] $end
|
|
$var parameter 32 =) ACC_WIDTH $end
|
|
$var parameter 32 >) DATA_WIDTH $end
|
|
$var parameter 64 ?) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 @) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 A) acc_in [31:0] $end
|
|
$var wire 8 B) w [7:0] $end
|
|
$var wire 8 C) x [7:0] $end
|
|
$var wire 32 D) product_ext [31:0] $end
|
|
$var wire 16 E) product [15:0] $end
|
|
$var wire 32 F) acc_out [31:0] $end
|
|
$var parameter 32 G) ACC_WIDTH $end
|
|
$var parameter 32 H) DATA_WIDTH $end
|
|
$var parameter 64 I) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 J) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 K) acc_in [31:0] $end
|
|
$var wire 8 L) w [7:0] $end
|
|
$var wire 8 M) x [7:0] $end
|
|
$var wire 32 N) product_ext [31:0] $end
|
|
$var wire 16 O) product [15:0] $end
|
|
$var wire 32 P) acc_out [31:0] $end
|
|
$var parameter 32 Q) ACC_WIDTH $end
|
|
$var parameter 32 R) DATA_WIDTH $end
|
|
$var parameter 64 S) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 T) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 U) acc_in [31:0] $end
|
|
$var wire 8 V) w [7:0] $end
|
|
$var wire 8 W) x [7:0] $end
|
|
$var wire 32 X) product_ext [31:0] $end
|
|
$var wire 16 Y) product [15:0] $end
|
|
$var wire 32 Z) acc_out [31:0] $end
|
|
$var parameter 32 [) ACC_WIDTH $end
|
|
$var parameter 32 \) DATA_WIDTH $end
|
|
$var parameter 64 ]) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 ^) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 _) acc_in [31:0] $end
|
|
$var wire 8 `) w [7:0] $end
|
|
$var wire 8 a) x [7:0] $end
|
|
$var wire 32 b) product_ext [31:0] $end
|
|
$var wire 16 c) product [15:0] $end
|
|
$var wire 32 d) acc_out [31:0] $end
|
|
$var parameter 32 e) ACC_WIDTH $end
|
|
$var parameter 32 f) DATA_WIDTH $end
|
|
$var parameter 64 g) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 h) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 i) acc_in [31:0] $end
|
|
$var wire 8 j) w [7:0] $end
|
|
$var wire 8 k) x [7:0] $end
|
|
$var wire 32 l) product_ext [31:0] $end
|
|
$var wire 16 m) product [15:0] $end
|
|
$var wire 32 n) acc_out [31:0] $end
|
|
$var parameter 32 o) ACC_WIDTH $end
|
|
$var parameter 32 p) DATA_WIDTH $end
|
|
$var parameter 64 q) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 r) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 s) acc_in [31:0] $end
|
|
$var wire 8 t) w [7:0] $end
|
|
$var wire 8 u) x [7:0] $end
|
|
$var wire 32 v) product_ext [31:0] $end
|
|
$var wire 16 w) product [15:0] $end
|
|
$var wire 32 x) acc_out [31:0] $end
|
|
$var parameter 32 y) ACC_WIDTH $end
|
|
$var parameter 32 z) DATA_WIDTH $end
|
|
$var parameter 64 {) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 |) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 }) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 ~) i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 !* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 "* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 #* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 $* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 %* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 &* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 '* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 (* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 )* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 ** node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 +* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 ,* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 -* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 .* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 /* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[6] $end
|
|
$var parameter 4 0* n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 1* activation [1:0] $end
|
|
$var wire 8 2* bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 3* final_acc_in_range $end
|
|
$var wire 1 4* final_acc_le_zero $end
|
|
$var wire 1 5* final_acc_upper_all0 $end
|
|
$var wire 16 6* n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 7* w_bus [255:0] $end
|
|
$var wire 256 8* x_bus [255:0] $end
|
|
$var wire 8 9* y_relu [7:0] $end
|
|
$var wire 8 :* y_none [7:0] $end
|
|
$var wire 64 ;* x_group [63:0] $end
|
|
$var wire 64 <* w_group [63:0] $end
|
|
$var wire 16 =* groups_real [15:0] $end
|
|
$var wire 1 >* final_acc_upper_all1 $end
|
|
$var wire 1 ?* final_acc_sign $end
|
|
$var wire 32 @* final_acc [31:0] $end
|
|
$var wire 32 A* bias_ext [31:0] $end
|
|
$var wire 32 B* acc_next [31:0] $end
|
|
$var parameter 32 C* ACC_WIDTH $end
|
|
$var parameter 2 D* ACT_NONE $end
|
|
$var parameter 2 E* ACT_RELU $end
|
|
$var parameter 32 F* DATA_WIDTH $end
|
|
$var parameter 32 G* GROUPS $end
|
|
$var parameter 32 H* GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 I* N_INPUTS $end
|
|
$var parameter 32 J* PARALLEL $end
|
|
$var reg 32 K* acc [31:0] $end
|
|
$var reg 1 L* busy $end
|
|
$var reg 1 M* done $end
|
|
$var reg 1 N* finishing $end
|
|
$var reg 2 O* group_index [1:0] $end
|
|
$var reg 8 P* y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 Q* acc_in [31:0] $end
|
|
$var wire 64 R* w_bus [63:0] $end
|
|
$var wire 64 S* x_bus [63:0] $end
|
|
$var wire 32 T* acc_out [31:0] $end
|
|
$var parameter 32 U* ACC_WIDTH $end
|
|
$var parameter 32 V* DATA_WIDTH $end
|
|
$var parameter 32 W* PARALLEL $end
|
|
$var parameter 32 X* TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 Y* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Z* acc_in [31:0] $end
|
|
$var wire 8 [* w [7:0] $end
|
|
$var wire 8 \* x [7:0] $end
|
|
$var wire 32 ]* product_ext [31:0] $end
|
|
$var wire 16 ^* product [15:0] $end
|
|
$var wire 32 _* acc_out [31:0] $end
|
|
$var parameter 32 `* ACC_WIDTH $end
|
|
$var parameter 32 a* DATA_WIDTH $end
|
|
$var parameter 64 b* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 c* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 d* acc_in [31:0] $end
|
|
$var wire 8 e* w [7:0] $end
|
|
$var wire 8 f* x [7:0] $end
|
|
$var wire 32 g* product_ext [31:0] $end
|
|
$var wire 16 h* product [15:0] $end
|
|
$var wire 32 i* acc_out [31:0] $end
|
|
$var parameter 32 j* ACC_WIDTH $end
|
|
$var parameter 32 k* DATA_WIDTH $end
|
|
$var parameter 64 l* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 m* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 n* acc_in [31:0] $end
|
|
$var wire 8 o* w [7:0] $end
|
|
$var wire 8 p* x [7:0] $end
|
|
$var wire 32 q* product_ext [31:0] $end
|
|
$var wire 16 r* product [15:0] $end
|
|
$var wire 32 s* acc_out [31:0] $end
|
|
$var parameter 32 t* ACC_WIDTH $end
|
|
$var parameter 32 u* DATA_WIDTH $end
|
|
$var parameter 64 v* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 w* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 x* acc_in [31:0] $end
|
|
$var wire 8 y* w [7:0] $end
|
|
$var wire 8 z* x [7:0] $end
|
|
$var wire 32 {* product_ext [31:0] $end
|
|
$var wire 16 |* product [15:0] $end
|
|
$var wire 32 }* acc_out [31:0] $end
|
|
$var parameter 32 ~* ACC_WIDTH $end
|
|
$var parameter 32 !+ DATA_WIDTH $end
|
|
$var parameter 64 "+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 #+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 $+ acc_in [31:0] $end
|
|
$var wire 8 %+ w [7:0] $end
|
|
$var wire 8 &+ x [7:0] $end
|
|
$var wire 32 '+ product_ext [31:0] $end
|
|
$var wire 16 (+ product [15:0] $end
|
|
$var wire 32 )+ acc_out [31:0] $end
|
|
$var parameter 32 *+ ACC_WIDTH $end
|
|
$var parameter 32 ++ DATA_WIDTH $end
|
|
$var parameter 64 ,+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 -+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 .+ acc_in [31:0] $end
|
|
$var wire 8 /+ w [7:0] $end
|
|
$var wire 8 0+ x [7:0] $end
|
|
$var wire 32 1+ product_ext [31:0] $end
|
|
$var wire 16 2+ product [15:0] $end
|
|
$var wire 32 3+ acc_out [31:0] $end
|
|
$var parameter 32 4+ ACC_WIDTH $end
|
|
$var parameter 32 5+ DATA_WIDTH $end
|
|
$var parameter 64 6+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 7+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 8+ acc_in [31:0] $end
|
|
$var wire 8 9+ w [7:0] $end
|
|
$var wire 8 :+ x [7:0] $end
|
|
$var wire 32 ;+ product_ext [31:0] $end
|
|
$var wire 16 <+ product [15:0] $end
|
|
$var wire 32 =+ acc_out [31:0] $end
|
|
$var parameter 32 >+ ACC_WIDTH $end
|
|
$var parameter 32 ?+ DATA_WIDTH $end
|
|
$var parameter 64 @+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 A+ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 B+ acc_in [31:0] $end
|
|
$var wire 8 C+ w [7:0] $end
|
|
$var wire 8 D+ x [7:0] $end
|
|
$var wire 32 E+ product_ext [31:0] $end
|
|
$var wire 16 F+ product [15:0] $end
|
|
$var wire 32 G+ acc_out [31:0] $end
|
|
$var parameter 32 H+ ACC_WIDTH $end
|
|
$var parameter 32 I+ DATA_WIDTH $end
|
|
$var parameter 64 J+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 K+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 L+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 M+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 N+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 O+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 P+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 Q+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 R+ i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 S+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 T+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 U+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 V+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 W+ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 X+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 Y+ node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 Z+ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 [+ level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 \+ node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[7] $end
|
|
$var parameter 4 ]+ n $end
|
|
$scope module u_neuron $end
|
|
$var wire 2 ^+ activation [1:0] $end
|
|
$var wire 8 _+ bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 `+ final_acc_in_range $end
|
|
$var wire 1 a+ final_acc_le_zero $end
|
|
$var wire 1 b+ final_acc_upper_all0 $end
|
|
$var wire 16 c+ n_inputs_real [15:0] $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 256 d+ w_bus [255:0] $end
|
|
$var wire 256 e+ x_bus [255:0] $end
|
|
$var wire 8 f+ y_relu [7:0] $end
|
|
$var wire 8 g+ y_none [7:0] $end
|
|
$var wire 64 h+ x_group [63:0] $end
|
|
$var wire 64 i+ w_group [63:0] $end
|
|
$var wire 16 j+ groups_real [15:0] $end
|
|
$var wire 1 k+ final_acc_upper_all1 $end
|
|
$var wire 1 l+ final_acc_sign $end
|
|
$var wire 32 m+ final_acc [31:0] $end
|
|
$var wire 32 n+ bias_ext [31:0] $end
|
|
$var wire 32 o+ acc_next [31:0] $end
|
|
$var parameter 32 p+ ACC_WIDTH $end
|
|
$var parameter 2 q+ ACT_NONE $end
|
|
$var parameter 2 r+ ACT_RELU $end
|
|
$var parameter 32 s+ DATA_WIDTH $end
|
|
$var parameter 32 t+ GROUPS $end
|
|
$var parameter 32 u+ GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 v+ N_INPUTS $end
|
|
$var parameter 32 w+ PARALLEL $end
|
|
$var reg 32 x+ acc [31:0] $end
|
|
$var reg 1 y+ busy $end
|
|
$var reg 1 z+ done $end
|
|
$var reg 1 {+ finishing $end
|
|
$var reg 2 |+ group_index [1:0] $end
|
|
$var reg 8 }+ y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 ~+ acc_in [31:0] $end
|
|
$var wire 64 !, w_bus [63:0] $end
|
|
$var wire 64 ", x_bus [63:0] $end
|
|
$var wire 32 #, acc_out [31:0] $end
|
|
$var parameter 32 $, ACC_WIDTH $end
|
|
$var parameter 32 %, DATA_WIDTH $end
|
|
$var parameter 32 &, PARALLEL $end
|
|
$var parameter 32 ', TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 (, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ), acc_in [31:0] $end
|
|
$var wire 8 *, w [7:0] $end
|
|
$var wire 8 +, x [7:0] $end
|
|
$var wire 32 ,, product_ext [31:0] $end
|
|
$var wire 16 -, product [15:0] $end
|
|
$var wire 32 ., acc_out [31:0] $end
|
|
$var parameter 32 /, ACC_WIDTH $end
|
|
$var parameter 32 0, DATA_WIDTH $end
|
|
$var parameter 64 1, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 2, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 3, acc_in [31:0] $end
|
|
$var wire 8 4, w [7:0] $end
|
|
$var wire 8 5, x [7:0] $end
|
|
$var wire 32 6, product_ext [31:0] $end
|
|
$var wire 16 7, product [15:0] $end
|
|
$var wire 32 8, acc_out [31:0] $end
|
|
$var parameter 32 9, ACC_WIDTH $end
|
|
$var parameter 32 :, DATA_WIDTH $end
|
|
$var parameter 64 ;, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 <, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =, acc_in [31:0] $end
|
|
$var wire 8 >, w [7:0] $end
|
|
$var wire 8 ?, x [7:0] $end
|
|
$var wire 32 @, product_ext [31:0] $end
|
|
$var wire 16 A, product [15:0] $end
|
|
$var wire 32 B, acc_out [31:0] $end
|
|
$var parameter 32 C, ACC_WIDTH $end
|
|
$var parameter 32 D, DATA_WIDTH $end
|
|
$var parameter 64 E, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 F, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G, acc_in [31:0] $end
|
|
$var wire 8 H, w [7:0] $end
|
|
$var wire 8 I, x [7:0] $end
|
|
$var wire 32 J, product_ext [31:0] $end
|
|
$var wire 16 K, product [15:0] $end
|
|
$var wire 32 L, acc_out [31:0] $end
|
|
$var parameter 32 M, ACC_WIDTH $end
|
|
$var parameter 32 N, DATA_WIDTH $end
|
|
$var parameter 64 O, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 P, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q, acc_in [31:0] $end
|
|
$var wire 8 R, w [7:0] $end
|
|
$var wire 8 S, x [7:0] $end
|
|
$var wire 32 T, product_ext [31:0] $end
|
|
$var wire 16 U, product [15:0] $end
|
|
$var wire 32 V, acc_out [31:0] $end
|
|
$var parameter 32 W, ACC_WIDTH $end
|
|
$var parameter 32 X, DATA_WIDTH $end
|
|
$var parameter 64 Y, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 Z, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [, acc_in [31:0] $end
|
|
$var wire 8 \, w [7:0] $end
|
|
$var wire 8 ], x [7:0] $end
|
|
$var wire 32 ^, product_ext [31:0] $end
|
|
$var wire 16 _, product [15:0] $end
|
|
$var wire 32 `, acc_out [31:0] $end
|
|
$var parameter 32 a, ACC_WIDTH $end
|
|
$var parameter 32 b, DATA_WIDTH $end
|
|
$var parameter 64 c, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 d, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e, acc_in [31:0] $end
|
|
$var wire 8 f, w [7:0] $end
|
|
$var wire 8 g, x [7:0] $end
|
|
$var wire 32 h, product_ext [31:0] $end
|
|
$var wire 16 i, product [15:0] $end
|
|
$var wire 32 j, acc_out [31:0] $end
|
|
$var parameter 32 k, ACC_WIDTH $end
|
|
$var parameter 32 l, DATA_WIDTH $end
|
|
$var parameter 64 m, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 n, i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o, acc_in [31:0] $end
|
|
$var wire 8 p, w [7:0] $end
|
|
$var wire 8 q, x [7:0] $end
|
|
$var wire 32 r, product_ext [31:0] $end
|
|
$var wire 16 s, product [15:0] $end
|
|
$var wire 32 t, acc_out [31:0] $end
|
|
$var parameter 32 u, ACC_WIDTH $end
|
|
$var parameter 32 v, DATA_WIDTH $end
|
|
$var parameter 64 w, PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 x, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 y, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 z, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 {, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 |, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 }, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 ~, i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 !- i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 "- level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 #- node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 $- node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 %- node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 &- node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 '- level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 (- node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 )- node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 *- level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 +- node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope task run_layer $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$comment Show the parameter values. $end
|
|
$dumpall
|
|
b0 +-
|
|
b10 *-
|
|
b1 )-
|
|
b0 (-
|
|
b1 '-
|
|
b11 &-
|
|
b10 %-
|
|
b1 $-
|
|
b0 #-
|
|
b0 "-
|
|
b111 !-
|
|
b110 ~,
|
|
b101 },
|
|
b100 |,
|
|
b11 {,
|
|
b10 z,
|
|
b1 y,
|
|
b0 x,
|
|
b10000 w,
|
|
b1000 v,
|
|
b100000 u,
|
|
b111 n,
|
|
b10000 m,
|
|
b1000 l,
|
|
b100000 k,
|
|
b110 d,
|
|
b10000 c,
|
|
b1000 b,
|
|
b100000 a,
|
|
b101 Z,
|
|
b10000 Y,
|
|
b1000 X,
|
|
b100000 W,
|
|
b100 P,
|
|
b10000 O,
|
|
b1000 N,
|
|
b100000 M,
|
|
b11 F,
|
|
b10000 E,
|
|
b1000 D,
|
|
b100000 C,
|
|
b10 <,
|
|
b10000 ;,
|
|
b1000 :,
|
|
b100000 9,
|
|
b1 2,
|
|
b10000 1,
|
|
b1000 0,
|
|
b100000 /,
|
|
b0 (,
|
|
b11 ',
|
|
b1000 &,
|
|
b1000 %,
|
|
b100000 $,
|
|
b1000 w+
|
|
b100000 v+
|
|
b10 u+
|
|
b100 t+
|
|
b1000 s+
|
|
b1 r+
|
|
b0 q+
|
|
b100000 p+
|
|
b111 ]+
|
|
b0 \+
|
|
b10 [+
|
|
b1 Z+
|
|
b0 Y+
|
|
b1 X+
|
|
b11 W+
|
|
b10 V+
|
|
b1 U+
|
|
b0 T+
|
|
b0 S+
|
|
b111 R+
|
|
b110 Q+
|
|
b101 P+
|
|
b100 O+
|
|
b11 N+
|
|
b10 M+
|
|
b1 L+
|
|
b0 K+
|
|
b10000 J+
|
|
b1000 I+
|
|
b100000 H+
|
|
b111 A+
|
|
b10000 @+
|
|
b1000 ?+
|
|
b100000 >+
|
|
b110 7+
|
|
b10000 6+
|
|
b1000 5+
|
|
b100000 4+
|
|
b101 -+
|
|
b10000 ,+
|
|
b1000 ++
|
|
b100000 *+
|
|
b100 #+
|
|
b10000 "+
|
|
b1000 !+
|
|
b100000 ~*
|
|
b11 w*
|
|
b10000 v*
|
|
b1000 u*
|
|
b100000 t*
|
|
b10 m*
|
|
b10000 l*
|
|
b1000 k*
|
|
b100000 j*
|
|
b1 c*
|
|
b10000 b*
|
|
b1000 a*
|
|
b100000 `*
|
|
b0 Y*
|
|
b11 X*
|
|
b1000 W*
|
|
b1000 V*
|
|
b100000 U*
|
|
b1000 J*
|
|
b100000 I*
|
|
b10 H*
|
|
b100 G*
|
|
b1000 F*
|
|
b1 E*
|
|
b0 D*
|
|
b100000 C*
|
|
b110 0*
|
|
b0 /*
|
|
b10 .*
|
|
b1 -*
|
|
b0 ,*
|
|
b1 +*
|
|
b11 **
|
|
b10 )*
|
|
b1 (*
|
|
b0 '*
|
|
b0 &*
|
|
b111 %*
|
|
b110 $*
|
|
b101 #*
|
|
b100 "*
|
|
b11 !*
|
|
b10 ~)
|
|
b1 })
|
|
b0 |)
|
|
b10000 {)
|
|
b1000 z)
|
|
b100000 y)
|
|
b111 r)
|
|
b10000 q)
|
|
b1000 p)
|
|
b100000 o)
|
|
b110 h)
|
|
b10000 g)
|
|
b1000 f)
|
|
b100000 e)
|
|
b101 ^)
|
|
b10000 ])
|
|
b1000 \)
|
|
b100000 [)
|
|
b100 T)
|
|
b10000 S)
|
|
b1000 R)
|
|
b100000 Q)
|
|
b11 J)
|
|
b10000 I)
|
|
b1000 H)
|
|
b100000 G)
|
|
b10 @)
|
|
b10000 ?)
|
|
b1000 >)
|
|
b100000 =)
|
|
b1 6)
|
|
b10000 5)
|
|
b1000 4)
|
|
b100000 3)
|
|
b0 ,)
|
|
b11 +)
|
|
b1000 *)
|
|
b1000 ))
|
|
b100000 ()
|
|
b1000 {(
|
|
b100000 z(
|
|
b10 y(
|
|
b100 x(
|
|
b1000 w(
|
|
b1 v(
|
|
b0 u(
|
|
b100000 t(
|
|
b101 a(
|
|
b0 `(
|
|
b10 _(
|
|
b1 ^(
|
|
b0 ](
|
|
b1 \(
|
|
b11 [(
|
|
b10 Z(
|
|
b1 Y(
|
|
b0 X(
|
|
b0 W(
|
|
b111 V(
|
|
b110 U(
|
|
b101 T(
|
|
b100 S(
|
|
b11 R(
|
|
b10 Q(
|
|
b1 P(
|
|
b0 O(
|
|
b10000 N(
|
|
b1000 M(
|
|
b100000 L(
|
|
b111 E(
|
|
b10000 D(
|
|
b1000 C(
|
|
b100000 B(
|
|
b110 ;(
|
|
b10000 :(
|
|
b1000 9(
|
|
b100000 8(
|
|
b101 1(
|
|
b10000 0(
|
|
b1000 /(
|
|
b100000 .(
|
|
b100 '(
|
|
b10000 &(
|
|
b1000 %(
|
|
b100000 $(
|
|
b11 {'
|
|
b10000 z'
|
|
b1000 y'
|
|
b100000 x'
|
|
b10 q'
|
|
b10000 p'
|
|
b1000 o'
|
|
b100000 n'
|
|
b1 g'
|
|
b10000 f'
|
|
b1000 e'
|
|
b100000 d'
|
|
b0 ]'
|
|
b11 \'
|
|
b1000 ['
|
|
b1000 Z'
|
|
b100000 Y'
|
|
b1000 N'
|
|
b100000 M'
|
|
b10 L'
|
|
b100 K'
|
|
b1000 J'
|
|
b1 I'
|
|
b0 H'
|
|
b100000 G'
|
|
b100 4'
|
|
b0 3'
|
|
b10 2'
|
|
b1 1'
|
|
b0 0'
|
|
b1 /'
|
|
b11 .'
|
|
b10 -'
|
|
b1 ,'
|
|
b0 +'
|
|
b0 *'
|
|
b111 )'
|
|
b110 ('
|
|
b101 ''
|
|
b100 &'
|
|
b11 %'
|
|
b10 $'
|
|
b1 #'
|
|
b0 "'
|
|
b10000 !'
|
|
b1000 ~&
|
|
b100000 }&
|
|
b111 v&
|
|
b10000 u&
|
|
b1000 t&
|
|
b100000 s&
|
|
b110 l&
|
|
b10000 k&
|
|
b1000 j&
|
|
b100000 i&
|
|
b101 b&
|
|
b10000 a&
|
|
b1000 `&
|
|
b100000 _&
|
|
b100 X&
|
|
b10000 W&
|
|
b1000 V&
|
|
b100000 U&
|
|
b11 N&
|
|
b10000 M&
|
|
b1000 L&
|
|
b100000 K&
|
|
b10 D&
|
|
b10000 C&
|
|
b1000 B&
|
|
b100000 A&
|
|
b1 :&
|
|
b10000 9&
|
|
b1000 8&
|
|
b100000 7&
|
|
b0 0&
|
|
b11 /&
|
|
b1000 .&
|
|
b1000 -&
|
|
b100000 ,&
|
|
b1000 !&
|
|
b100000 ~%
|
|
b10 }%
|
|
b100 |%
|
|
b1000 {%
|
|
b1 z%
|
|
b0 y%
|
|
b100000 x%
|
|
b11 e%
|
|
b0 d%
|
|
b10 c%
|
|
b1 b%
|
|
b0 a%
|
|
b1 `%
|
|
b11 _%
|
|
b10 ^%
|
|
b1 ]%
|
|
b0 \%
|
|
b0 [%
|
|
b111 Z%
|
|
b110 Y%
|
|
b101 X%
|
|
b100 W%
|
|
b11 V%
|
|
b10 U%
|
|
b1 T%
|
|
b0 S%
|
|
b10000 R%
|
|
b1000 Q%
|
|
b100000 P%
|
|
b111 I%
|
|
b10000 H%
|
|
b1000 G%
|
|
b100000 F%
|
|
b110 ?%
|
|
b10000 >%
|
|
b1000 =%
|
|
b100000 <%
|
|
b101 5%
|
|
b10000 4%
|
|
b1000 3%
|
|
b100000 2%
|
|
b100 +%
|
|
b10000 *%
|
|
b1000 )%
|
|
b100000 (%
|
|
b11 !%
|
|
b10000 ~$
|
|
b1000 }$
|
|
b100000 |$
|
|
b10 u$
|
|
b10000 t$
|
|
b1000 s$
|
|
b100000 r$
|
|
b1 k$
|
|
b10000 j$
|
|
b1000 i$
|
|
b100000 h$
|
|
b0 a$
|
|
b11 `$
|
|
b1000 _$
|
|
b1000 ^$
|
|
b100000 ]$
|
|
b1000 R$
|
|
b100000 Q$
|
|
b10 P$
|
|
b100 O$
|
|
b1000 N$
|
|
b1 M$
|
|
b0 L$
|
|
b100000 K$
|
|
b10 8$
|
|
b0 7$
|
|
b10 6$
|
|
b1 5$
|
|
b0 4$
|
|
b1 3$
|
|
b11 2$
|
|
b10 1$
|
|
b1 0$
|
|
b0 /$
|
|
b0 .$
|
|
b111 -$
|
|
b110 ,$
|
|
b101 +$
|
|
b100 *$
|
|
b11 )$
|
|
b10 ($
|
|
b1 '$
|
|
b0 &$
|
|
b10000 %$
|
|
b1000 $$
|
|
b100000 #$
|
|
b111 z#
|
|
b10000 y#
|
|
b1000 x#
|
|
b100000 w#
|
|
b110 p#
|
|
b10000 o#
|
|
b1000 n#
|
|
b100000 m#
|
|
b101 f#
|
|
b10000 e#
|
|
b1000 d#
|
|
b100000 c#
|
|
b100 \#
|
|
b10000 [#
|
|
b1000 Z#
|
|
b100000 Y#
|
|
b11 R#
|
|
b10000 Q#
|
|
b1000 P#
|
|
b100000 O#
|
|
b10 H#
|
|
b10000 G#
|
|
b1000 F#
|
|
b100000 E#
|
|
b1 >#
|
|
b10000 =#
|
|
b1000 <#
|
|
b100000 ;#
|
|
b0 4#
|
|
b11 3#
|
|
b1000 2#
|
|
b1000 1#
|
|
b100000 0#
|
|
b1000 %#
|
|
b100000 $#
|
|
b10 ##
|
|
b100 "#
|
|
b1000 !#
|
|
b1 ~"
|
|
b0 }"
|
|
b100000 |"
|
|
b1 i"
|
|
b0 h"
|
|
b10 g"
|
|
b1 f"
|
|
b0 e"
|
|
b1 d"
|
|
b11 c"
|
|
b10 b"
|
|
b1 a"
|
|
b0 `"
|
|
b0 _"
|
|
b111 ^"
|
|
b110 ]"
|
|
b101 \"
|
|
b100 ["
|
|
b11 Z"
|
|
b10 Y"
|
|
b1 X"
|
|
b0 W"
|
|
b10000 V"
|
|
b1000 U"
|
|
b100000 T"
|
|
b111 M"
|
|
b10000 L"
|
|
b1000 K"
|
|
b100000 J"
|
|
b110 C"
|
|
b10000 B"
|
|
b1000 A"
|
|
b100000 @"
|
|
b101 9"
|
|
b10000 8"
|
|
b1000 7"
|
|
b100000 6"
|
|
b100 /"
|
|
b10000 ."
|
|
b1000 -"
|
|
b100000 ,"
|
|
b11 %"
|
|
b10000 $"
|
|
b1000 #"
|
|
b100000 ""
|
|
b10 y
|
|
b10000 x
|
|
b1000 w
|
|
b100000 v
|
|
b1 o
|
|
b10000 n
|
|
b1000 m
|
|
b100000 l
|
|
b0 e
|
|
b11 d
|
|
b1000 c
|
|
b1000 b
|
|
b100000 a
|
|
b1000 V
|
|
b100000 U
|
|
b10 T
|
|
b100 S
|
|
b1000 R
|
|
b1 Q
|
|
b0 P
|
|
b100000 O
|
|
b0 <
|
|
b1000 ;
|
|
b1000 :
|
|
b100000 9
|
|
b1000 8
|
|
b100000 7
|
|
b1000 (
|
|
b1000 '
|
|
b100000 &
|
|
b1000 %
|
|
b100000 $
|
|
$end
|
|
#0
|
|
$dumpvars
|
|
bx t,
|
|
bx s,
|
|
bx r,
|
|
bx q,
|
|
bx p,
|
|
b0 o,
|
|
bx j,
|
|
bx i,
|
|
bx h,
|
|
bx g,
|
|
bx f,
|
|
b0 e,
|
|
bx `,
|
|
bx _,
|
|
bx ^,
|
|
bx ],
|
|
bx \,
|
|
b0 [,
|
|
bx V,
|
|
bx U,
|
|
bx T,
|
|
bx S,
|
|
bx R,
|
|
b0 Q,
|
|
bx L,
|
|
bx K,
|
|
bx J,
|
|
bx I,
|
|
bx H,
|
|
b0 G,
|
|
bx B,
|
|
bx A,
|
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