micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
186 lines
8.4 KiB
Plaintext
186 lines
8.4 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 72/43848 0%
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Info: logic LUTs: 24/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 72/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 40 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x08e681ff
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 72/ 43848 0%
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Info: TRELLIS_COMB: 74/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 57 cells, random placement wirelen = 5888.
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Info: at initial placer iter 0, wirelen = 1162
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Info: at initial placer iter 1, wirelen = 1051
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Info: at initial placer iter 2, wirelen = 1014
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Info: at initial placer iter 3, wirelen = 984
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 983, spread = 1123, legal = 1130; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 1130
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Info: at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 763
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Info: at iteration #10: temp = 0.000000, timing cost = 30, wirelen = 741
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Info: at iteration #14: temp = 0.000000, timing cost = 18, wirelen = 742
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Info: SA placement time 0.02s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 432.34 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.71 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.61 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10187, 10265) |*
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Info: [ 10265, 10343) |***
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Info: [ 10343, 10421) |
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Info: [ 10421, 10499) |****
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Info: [ 10499, 10577) |
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Info: [ 10577, 10655) |******
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Info: [ 10655, 10733) |****
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Info: [ 10733, 10811) |**********************************
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Info: [ 10811, 10889) |***************
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Info: [ 10889, 10967) |*************
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Info: [ 10967, 11045) |*******************************
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Info: [ 11045, 11123) |******************************************************
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Info: [ 11123, 11201) |*****
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Info: [ 11201, 11279) |************************************************
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Info: [ 11279, 11357) |****************
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Info: [ 11357, 11435) |*********
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Info: [ 11435, 11513) |**************
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Info: [ 11513, 11591) |*
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Info: [ 11591, 11669) |***************
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Info: [ 11669, 11747) |***********
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Info: Checksum: 0x3a3fcdd5
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 532 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 687 | 134 545 | 134 545 | 0| 0.05 0.05|
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Info: Routing complete.
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Info: Router1 time 0.05s
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Info: Checksum: 0x452b9643
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.GEN_SLOT[2].GEN_LANE[0].rd_data_reg_TRELLIS_FF_Q_7.Q
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Info: routing 0.75 1.14 Net rd_data_flat[135] (36,12) -> (35,11)
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Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.B
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Info: Defined in:
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Info: hardware/v2/nms/rtl/nms_weight_packed.v:30.50-30.62
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Info: logic 0.18 1.32 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT_LUT4_Z.F
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Info: routing 0.00 1.32 Net chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_ALUT (35,11) -> (35,11)
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Info: Sink chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
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Info: logic 0.13 1.45 Source chk_TRELLIS_FF_Q_DI_PFUMX_Z_7_BLUT_LUT4_Z.OFX
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Info: routing 0.46 1.91 Net chk_TRELLIS_FF_Q_DI[7] (35,11) -> (36,11)
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Info: Sink chk_TRELLIS_FF_Q_7.M
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Info: setup 0.00 1.91 Source chk_TRELLIS_FF_Q_7.M
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Info: 0.70 ns logic, 1.21 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 3.14 3.14 Net rst$TRELLIS_IO_IN (90,11) -> (34,14)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_2.C
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:13.17-13.20
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Info: logic 0.18 3.32 Source seed_LUT4_B_Z_LUT4_Z_2.F
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Info: routing 0.12 3.44 Net seed_LUT4_B_Z[6] (34,14) -> (34,14)
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Info: Sink lfsr_TRELLIS_FF_Q_7.DI
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Info: setup 0.00 3.44 Source lfsr_TRELLIS_FF_Q_7.DI
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Info: 0.18 ns logic, 3.26 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_6.Q
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Info: routing 2.79 3.18 Net checksum[6]$TRELLIS_IO_OUT (35,13) -> (90,14)
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Info: Sink checksum[6]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_packed.v:40.15-40.18
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Info: 0.40 ns logic, 2.79 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 523.29 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.44 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.18 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 10589, 10650) |***
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Info: [ 10650, 10711) |***************
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Info: [ 10711, 10772) |****
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Info: [ 10772, 10833) |**
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Info: [ 10833, 10894) |******************
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Info: [ 10894, 10955) |*******************
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Info: [ 10955, 11016) |*****
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Info: [ 11016, 11077) |************
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Info: [ 11077, 11138) |************************
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Info: [ 11138, 11199) |***********************
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Info: [ 11199, 11260) |******************
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Info: [ 11260, 11321) |*******************
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Info: [ 11321, 11382) |******************************
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Info: [ 11382, 11443) |*******************************
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Info: [ 11443, 11504) |**
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Info: [ 11504, 11565) |****************
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Info: [ 11565, 11626) |******************
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Info: [ 11626, 11687) |*********
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Info: [ 11687, 11748) |**********
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Info: [ 11748, 11809) |******
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Info: Program finished normally.
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