micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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| 1 | design | n_slots | seed | fmax_mhz | pass_at_80mhz | classification |
|---|---|---|---|---|---|---|
| 2 | sdram | 2 | 1 | 102.29 | TRUE | POST-P&R |
| 3 | sdram | 2 | 2 | 94.32 | TRUE | POST-P&R |
| 4 | sdram | 2 | 3 | 103.99 | TRUE | POST-P&R |
| 5 | sdram | 4 | 1 | 80.15 | TRUE | POST-P&R |
| 6 | sdram | 4 | 2 | 74.88 | FALSE | POST-P&R |
| 7 | sdram | 4 | 3 | 81.55 | TRUE | POST-P&R |
| 8 | sdram | 4 | hifreq_target200 | 68.45_prelim_then_80.15_final | TRUE | POST-P&R |
| 9 | dual_psram | 2 | 1 | 100.48 | TRUE | POST-P&R |
| 10 | dual_psram | 2 | 2 | 103.52 | TRUE | POST-P&R |
| 11 | dual_psram | 2 | 3 | 101.37 | TRUE | POST-P&R |
| 12 | dual_psram | 4 | 1 | 84.68 | TRUE | POST-P&R |
| 13 | dual_psram | 4 | 2 | 77.72 | FALSE | POST-P&R |
| 14 | dual_psram | 4 | 3 | 87.26 | TRUE | POST-P&R |