//-------------------------------------------------------------------------------- // Auto-generated by LiteX (9ad3ecf74) on 2026-09-16 08:16:18 //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- // CSR Includes. //-------------------------------------------------------------------------------- #include #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H #include #include #ifndef CSR_ACCESSORS_DEFINED #include #endif /* ! CSR_ACCESSORS_DEFINED */ #ifndef CSR_BASE #define CSR_BASE 0x0L #endif /* ! CSR_BASE */ //-------------------------------------------------------------------------------- // CSR Registers/Fields Definition. //-------------------------------------------------------------------------------- /* DDRCTRL Registers */ #define CSR_DDRCTRL_BASE (CSR_BASE + 0x0L) #define CSR_DDRCTRL_INIT_DONE_ADDR (CSR_BASE + 0x0L) #define CSR_DDRCTRL_INIT_DONE_SIZE 1 #define CSR_DDRCTRL_INIT_ERROR_ADDR (CSR_BASE + 0x4L) #define CSR_DDRCTRL_INIT_ERROR_SIZE 1 /* DDRCTRL Fields */ /* DDRPHY Registers */ #define CSR_DDRPHY_BASE (CSR_BASE + 0x800L) #define CSR_DDRPHY_DLY_SEL_ADDR (CSR_BASE + 0x800L) #define CSR_DDRPHY_DLY_SEL_SIZE 1 #define CSR_DDRPHY_RDLY_DQ_RST_ADDR (CSR_BASE + 0x804L) #define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1 #define CSR_DDRPHY_RDLY_DQ_INC_ADDR (CSR_BASE + 0x808L) #define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1 #define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_ADDR (CSR_BASE + 0x80cL) #define CSR_DDRPHY_RDLY_DQ_BITSLIP_RST_SIZE 1 #define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR (CSR_BASE + 0x810L) #define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1 #define CSR_DDRPHY_BURSTDET_CLR_ADDR (CSR_BASE + 0x814L) #define CSR_DDRPHY_BURSTDET_CLR_SIZE 1 #define CSR_DDRPHY_BURSTDET_SEEN_ADDR (CSR_BASE + 0x818L) #define CSR_DDRPHY_BURSTDET_SEEN_SIZE 1 /* DDRPHY Fields */ /* SDRAM Registers */ #define CSR_SDRAM_BASE (CSR_BASE + 0x1000L) #define CSR_SDRAM_DFII_CONTROL_ADDR (CSR_BASE + 0x1000L) #define CSR_SDRAM_DFII_CONTROL_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_ADDR (CSR_BASE + 0x1004L) #define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1008L) #define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 #define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR (CSR_BASE + 0x100cL) #define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 1 #define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR (CSR_BASE + 0x1010L) #define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 #define CSR_SDRAM_DFII_PI0_WRDATA_ADDR (CSR_BASE + 0x1014L) #define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2 #define CSR_SDRAM_DFII_PI0_RDDATA_ADDR (CSR_BASE + 0x101cL) #define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2 #define CSR_SDRAM_DFII_PI1_COMMAND_ADDR (CSR_BASE + 0x1024L) #define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR (CSR_BASE + 0x1028L) #define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1 #define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR (CSR_BASE + 0x102cL) #define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 1 #define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR (CSR_BASE + 0x1030L) #define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1 #define CSR_SDRAM_DFII_PI1_WRDATA_ADDR (CSR_BASE + 0x1034L) #define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 2 #define CSR_SDRAM_DFII_PI1_RDDATA_ADDR (CSR_BASE + 0x103cL) #define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 2 /* SDRAM Fields */ #define CSR_SDRAM_DFII_CONTROL_SEL_OFFSET 0 #define CSR_SDRAM_DFII_CONTROL_SEL_SIZE 1 #define CSR_SDRAM_DFII_CONTROL_CKE_OFFSET 1 #define CSR_SDRAM_DFII_CONTROL_CKE_SIZE 1 #define CSR_SDRAM_DFII_CONTROL_ODT_OFFSET 2 #define CSR_SDRAM_DFII_CONTROL_ODT_SIZE 1 #define CSR_SDRAM_DFII_CONTROL_RESET_N_OFFSET 3 #define CSR_SDRAM_DFII_CONTROL_RESET_N_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_OFFSET 0 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_WE_OFFSET 1 #define CSR_SDRAM_DFII_PI0_COMMAND_WE_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_CAS_OFFSET 2 #define CSR_SDRAM_DFII_PI0_COMMAND_CAS_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_RAS_OFFSET 3 #define CSR_SDRAM_DFII_PI0_COMMAND_RAS_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_WREN_OFFSET 4 #define CSR_SDRAM_DFII_PI0_COMMAND_WREN_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_OFFSET 5 #define CSR_SDRAM_DFII_PI0_COMMAND_RDEN_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_OFFSET 6 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_TOP_SIZE 1 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_OFFSET 7 #define CSR_SDRAM_DFII_PI0_COMMAND_CS_BOTTOM_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_OFFSET 0 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_WE_OFFSET 1 #define CSR_SDRAM_DFII_PI1_COMMAND_WE_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_CAS_OFFSET 2 #define CSR_SDRAM_DFII_PI1_COMMAND_CAS_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_RAS_OFFSET 3 #define CSR_SDRAM_DFII_PI1_COMMAND_RAS_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_WREN_OFFSET 4 #define CSR_SDRAM_DFII_PI1_COMMAND_WREN_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_OFFSET 5 #define CSR_SDRAM_DFII_PI1_COMMAND_RDEN_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_OFFSET 6 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_TOP_SIZE 1 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_OFFSET 7 #define CSR_SDRAM_DFII_PI1_COMMAND_CS_BOTTOM_SIZE 1 //-------------------------------------------------------------------------------- // CSR Registers Access Functions. //-------------------------------------------------------------------------------- #ifndef LITEX_CSR_ACCESS_FUNCTIONS #define LITEX_CSR_ACCESS_FUNCTIONS 1 #endif #if LITEX_CSR_ACCESS_FUNCTIONS /* DDRCTRL Access Functions */ static inline uint32_t ddrctrl_init_done_read(void) { return csr_read_simple((CSR_BASE + 0x0L)); } static inline void ddrctrl_init_done_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x0L)); } static inline uint32_t ddrctrl_init_error_read(void) { return csr_read_simple((CSR_BASE + 0x4L)); } static inline void ddrctrl_init_error_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x4L)); } /* DDRPHY Access Functions */ static inline uint32_t ddrphy_dly_sel_read(void) { return csr_read_simple((CSR_BASE + 0x800L)); } static inline void ddrphy_dly_sel_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x800L)); } static inline uint32_t ddrphy_rdly_dq_rst_read(void) { return csr_read_simple((CSR_BASE + 0x804L)); } static inline void ddrphy_rdly_dq_rst_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x804L)); } static inline uint32_t ddrphy_rdly_dq_inc_read(void) { return csr_read_simple((CSR_BASE + 0x808L)); } static inline void ddrphy_rdly_dq_inc_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x808L)); } static inline uint32_t ddrphy_rdly_dq_bitslip_rst_read(void) { return csr_read_simple((CSR_BASE + 0x80cL)); } static inline void ddrphy_rdly_dq_bitslip_rst_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x80cL)); } static inline uint32_t ddrphy_rdly_dq_bitslip_read(void) { return csr_read_simple((CSR_BASE + 0x810L)); } static inline void ddrphy_rdly_dq_bitslip_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x810L)); } static inline uint32_t ddrphy_burstdet_clr_read(void) { return csr_read_simple((CSR_BASE + 0x814L)); } static inline void ddrphy_burstdet_clr_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x814L)); } static inline uint32_t ddrphy_burstdet_seen_read(void) { return csr_read_simple((CSR_BASE + 0x818L)); } /* SDRAM Access Functions */ static inline uint32_t sdram_dfii_control_read(void) { return csr_read_simple((CSR_BASE + 0x1000L)); } static inline void sdram_dfii_control_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1000L)); } static inline uint32_t sdram_dfii_pi0_command_read(void) { return csr_read_simple((CSR_BASE + 0x1004L)); } static inline void sdram_dfii_pi0_command_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1004L)); } static inline uint32_t sdram_dfii_pi0_command_issue_read(void) { return csr_read_simple((CSR_BASE + 0x1008L)); } static inline void sdram_dfii_pi0_command_issue_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1008L)); } static inline uint32_t sdram_dfii_pi0_address_read(void) { return csr_read_simple((CSR_BASE + 0x100cL)); } static inline void sdram_dfii_pi0_address_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x100cL)); } static inline uint32_t sdram_dfii_pi0_baddress_read(void) { return csr_read_simple((CSR_BASE + 0x1010L)); } static inline void sdram_dfii_pi0_baddress_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1010L)); } static inline uint64_t sdram_dfii_pi0_wrdata_read(void) { uint64_t r = csr_read_simple((CSR_BASE + 0x1014L)); r <<= 32; r |= csr_read_simple((CSR_BASE + 0x1018L)); return r; } static inline void sdram_dfii_pi0_wrdata_write(uint64_t v) { csr_write_simple(v >> 32, (CSR_BASE + 0x1014L)); csr_write_simple(v, (CSR_BASE + 0x1018L)); } static inline uint64_t sdram_dfii_pi0_rddata_read(void) { uint64_t r = csr_read_simple((CSR_BASE + 0x101cL)); r <<= 32; r |= csr_read_simple((CSR_BASE + 0x1020L)); return r; } static inline uint32_t sdram_dfii_pi1_command_read(void) { return csr_read_simple((CSR_BASE + 0x1024L)); } static inline void sdram_dfii_pi1_command_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1024L)); } static inline uint32_t sdram_dfii_pi1_command_issue_read(void) { return csr_read_simple((CSR_BASE + 0x1028L)); } static inline void sdram_dfii_pi1_command_issue_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1028L)); } static inline uint32_t sdram_dfii_pi1_address_read(void) { return csr_read_simple((CSR_BASE + 0x102cL)); } static inline void sdram_dfii_pi1_address_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x102cL)); } static inline uint32_t sdram_dfii_pi1_baddress_read(void) { return csr_read_simple((CSR_BASE + 0x1030L)); } static inline void sdram_dfii_pi1_baddress_write(uint32_t v) { csr_write_simple(v, (CSR_BASE + 0x1030L)); } static inline uint64_t sdram_dfii_pi1_wrdata_read(void) { uint64_t r = csr_read_simple((CSR_BASE + 0x1034L)); r <<= 32; r |= csr_read_simple((CSR_BASE + 0x1038L)); return r; } static inline void sdram_dfii_pi1_wrdata_write(uint64_t v) { csr_write_simple(v >> 32, (CSR_BASE + 0x1034L)); csr_write_simple(v, (CSR_BASE + 0x1038L)); } static inline uint64_t sdram_dfii_pi1_rddata_read(void) { uint64_t r = csr_read_simple((CSR_BASE + 0x103cL)); r <<= 32; r |= csr_read_simple((CSR_BASE + 0x1040L)); return r; } #endif /* LITEX_CSR_ACCESS_FUNCTIONS */ #endif /* ! __GENERATED_CSR_H */