micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1630 lines
114 KiB
Plaintext
1630 lines
114 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Running command `read_verilog hardware/v2/nms/rtl/nms_weight_packed.v hardware/v2/nms/synthesis/harness_nms_weight_packed.v; chparam -set N_SLOTS 2 -set MAX_TILES 16 harness_nms_weight_packed; synth_ecp5 -json hardware/v2/nms/synthesis/wt_packed_n2_t16/top.json -top harness_nms_weight_packed' --
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1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_weight_packed.v
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Parsing Verilog input from `hardware/v2/nms/rtl/nms_weight_packed.v' to AST representation.
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Generating RTLIL representation for module `\nms_weight_packed'.
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_weight_packed.v
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Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_weight_packed.v' to AST representation.
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Generating RTLIL representation for module `\harness_nms_weight_packed'.
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Successfully finished Verilog frontend.
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Parameter \N_SLOTS = 2
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Parameter \MAX_TILES = 16
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3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_weight_packed'.
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Parameter \N_SLOTS = 2
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Parameter \MAX_TILES = 16
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Generating RTLIL representation for module `$paramod$8f3eb27a7703d44be72af08458de811e7c8be6b9\harness_nms_weight_packed'.
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4. Executing SYNTH_LATTICE pass.
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4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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4.3. Executing HIERARCHY pass (managing design hierarchy).
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4.3.1. Analyzing design hierarchy..
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Top module: \harness_nms_weight_packed
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Used module: \nms_weight_packed
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \N_SLOTS = 2
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Parameter \MAX_TILES = 16
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4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_weight_packed'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \N_SLOTS = 2
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Parameter \MAX_TILES = 16
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Generating RTLIL representation for module `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed'.
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4.3.3. Analyzing design hierarchy..
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Top module: \harness_nms_weight_packed
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Used module: $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed
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4.3.4. Analyzing design hierarchy..
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Top module: \harness_nms_weight_packed
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Used module: $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed
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Removing unused module `\nms_weight_packed'.
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Removed 1 unused modules.
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4.4. Executing PROC pass (convert processes to netlists).
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4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300 in module harness_nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305 in module harness_nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549 in module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
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|
Removed a total of 0 dead cases.
|
|
|
|
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 2 redundant assignments.
|
|
Promoted 50 assignments to connections.
|
|
|
|
4.4.4. Executing PROC_INIT pass (extract init attributes).
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|
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|
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
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|
|
|
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~34 debug messages>
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|
|
|
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
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1/1: $0\lfsr[31:0]
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Creating decoders for process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
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1/3: $0\chk[7:0]
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|
2/3: $1\chk_next[7:0]
|
|
3/3: $1\k[31:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
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1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_EN[7:0]$675
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|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_DATA[7:0]$674
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_ADDR[3:0]$673
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[7].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
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|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$667
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_DATA[7:0]$666
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_ADDR[3:0]$665
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[6].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
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|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_EN[7:0]$659
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_DATA[7:0]$658
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_ADDR[3:0]$657
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[5].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
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|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_EN[7:0]$651
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_DATA[7:0]$650
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_ADDR[3:0]$649
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[4].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
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|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_EN[7:0]$643
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_DATA[7:0]$642
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_ADDR[3:0]$641
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[3].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
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|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_EN[7:0]$635
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_DATA[7:0]$634
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_ADDR[3:0]$633
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[2].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_EN[7:0]$627
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_DATA[7:0]$626
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_ADDR[3:0]$625
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[1].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$619
|
|
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_DATA[7:0]$618
|
|
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_ADDR[3:0]$617
|
|
4/4: $0\GEN_SLOT[1].GEN_LANE[0].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_EN[7:0]$611
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_DATA[7:0]$610
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_ADDR[3:0]$609
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[7].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$603
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_DATA[7:0]$602
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_ADDR[3:0]$601
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[6].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_EN[7:0]$595
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_DATA[7:0]$594
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_ADDR[3:0]$593
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[5].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_EN[7:0]$587
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_DATA[7:0]$586
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_ADDR[3:0]$585
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[4].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_EN[7:0]$579
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_DATA[7:0]$578
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_ADDR[3:0]$577
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[3].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_EN[7:0]$571
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_DATA[7:0]$570
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_ADDR[3:0]$569
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[2].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_EN[7:0]$563
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_DATA[7:0]$562
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_ADDR[3:0]$561
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[1].rd_data_reg[7:0]
|
|
Creating decoders for process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$555
|
|
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_DATA[7:0]$554
|
|
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_ADDR[3:0]$553
|
|
4/4: $0\GEN_SLOT[0].GEN_LANE[0].rd_data_reg[7:0]
|
|
|
|
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
|
|
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\harness_nms_weight_packed.\lfsr' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
|
|
created $dff cell `$procdff$865' with positive edge clock.
|
|
Creating register for signal `\harness_nms_weight_packed.\k' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
|
|
created $dff cell `$procdff$866' with positive edge clock.
|
|
Creating register for signal `\harness_nms_weight_packed.\chk' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
|
|
created $dff cell `$procdff$867' with positive edge clock.
|
|
Creating register for signal `\harness_nms_weight_packed.\chk_next' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
|
|
created $dff cell `$procdff$868' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[7].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
created $dff cell `$procdff$869' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
created $dff cell `$procdff$870' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
created $dff cell `$procdff$871' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
created $dff cell `$procdff$872' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[6].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
created $dff cell `$procdff$873' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
created $dff cell `$procdff$874' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
created $dff cell `$procdff$875' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
created $dff cell `$procdff$876' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[5].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
created $dff cell `$procdff$877' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
created $dff cell `$procdff$878' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
created $dff cell `$procdff$879' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
created $dff cell `$procdff$880' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[4].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
created $dff cell `$procdff$881' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
created $dff cell `$procdff$882' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
created $dff cell `$procdff$883' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
created $dff cell `$procdff$884' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[3].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
created $dff cell `$procdff$885' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
created $dff cell `$procdff$886' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
created $dff cell `$procdff$887' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
created $dff cell `$procdff$888' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[2].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
created $dff cell `$procdff$889' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
created $dff cell `$procdff$890' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
created $dff cell `$procdff$891' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
created $dff cell `$procdff$892' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[1].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
created $dff cell `$procdff$893' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
created $dff cell `$procdff$894' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
created $dff cell `$procdff$895' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
created $dff cell `$procdff$896' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[0].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
created $dff cell `$procdff$897' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
created $dff cell `$procdff$898' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
created $dff cell `$procdff$899' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
created $dff cell `$procdff$900' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[7].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
created $dff cell `$procdff$901' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
created $dff cell `$procdff$902' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
created $dff cell `$procdff$903' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
created $dff cell `$procdff$904' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[6].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
created $dff cell `$procdff$905' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
created $dff cell `$procdff$906' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
created $dff cell `$procdff$907' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
created $dff cell `$procdff$908' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[5].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
created $dff cell `$procdff$909' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
created $dff cell `$procdff$910' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
created $dff cell `$procdff$911' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$538_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
created $dff cell `$procdff$912' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[4].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
created $dff cell `$procdff$913' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
created $dff cell `$procdff$914' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
created $dff cell `$procdff$915' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$537_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
created $dff cell `$procdff$916' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[3].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
created $dff cell `$procdff$917' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
created $dff cell `$procdff$918' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
created $dff cell `$procdff$919' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$536_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
created $dff cell `$procdff$920' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[2].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
created $dff cell `$procdff$921' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
created $dff cell `$procdff$922' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
created $dff cell `$procdff$923' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$535_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
created $dff cell `$procdff$924' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[1].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
created $dff cell `$procdff$925' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
created $dff cell `$procdff$926' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
created $dff cell `$procdff$927' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$534_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
created $dff cell `$procdff$928' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[0].rd_data_reg' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
created $dff cell `$procdff$929' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_ADDR' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
created $dff cell `$procdff$930' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_DATA' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
created $dff cell `$procdff$931' with positive edge clock.
|
|
Creating register for signal `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN' using process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
created $dff cell `$procdff$932' with positive edge clock.
|
|
|
|
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
|
|
Removing empty process `harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
|
|
Found and cleaned up 1 empty switch in `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
|
|
Removing empty process `harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$669'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$661'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$653'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$645'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$637'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$629'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$621'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$613'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$605'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$597'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$589'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$581'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$573'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$565'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$557'.
|
|
Found and cleaned up 2 empty switches in `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
Removing empty process `$paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$549'.
|
|
Cleaned up 34 empty switches.
|
|
|
|
4.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
<suppressed ~1 debug messages>
|
|
Optimizing module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
|
|
|
|
4.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_weight_packed...
|
|
Checking module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed...
|
|
Found and reported 0 problems.
|
|
|
|
4.6. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$54061157f7b1fa2ed42d47bbd164111c1661279e\nms_weight_packed.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.7. Executing TRIBUF pass.
|
|
|
|
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
4.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 150 unused cells and 323 unused wires.
|
|
<suppressed ~181 debug messages>
|
|
|
|
4.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_weight_packed...
|
|
Found and reported 0 problems.
|
|
|
|
4.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 24 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$770: \lfsr [7:0] -> { \lfsr [7:2] 1'1 \lfsr [0] }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$858: \lfsr [7:0] -> { \lfsr [7:1] 1'1 }
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$861: \lfsr [3:0] -> { \lfsr [3:1] 1'1 }
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~20 debug messages>
|
|
|
|
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$767:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0]
|
|
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$616 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$855:
|
|
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0]
|
|
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$533_EN[7:0]$552 [0] }
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 2 changes.
|
|
|
|
4.12.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 24 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.12.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~20 debug messages>
|
|
|
|
4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 24 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
4.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 24 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~20 debug messages>
|
|
|
|
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 24 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $procdff$865 ($dff) from module harness_nms_weight_packed (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:21$304_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
|
|
Adding SRST signal on $procdff$867 ($dff) from module harness_nms_weight_packed (D = $xor$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:47$307_Y, Q = \chk, rval = 8'00000000).
|
|
Adding EN signal on $flatten\dut.$procdff$897 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$620_DATA, Q = \dut.GEN_SLOT[1].GEN_LANE[0].rd_data_reg).
|
|
Adding EN signal on $flatten\dut.$procdff$929 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$556_DATA, Q = \dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg).
|
|
|
|
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 3 unused cells and 3 unused wires.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~14 debug messages>
|
|
|
|
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 22 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 24 bits (of 32) from mux cell harness_nms_weight_packed.$procmux$678 ($mux).
|
|
Removed top 56 bits (of 128) from wire harness_nms_weight_packed.rd_data_flat.
|
|
Removed top 24 bits (of 32) from wire harness_nms_weight_packed.$0\lfsr[31:0].
|
|
|
|
4.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 0 unused cells and 2 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
4.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.19.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
4.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.22.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
4.24. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module harness_nms_weight_packed:
|
|
created 0 $alu and 0 $macc cells.
|
|
|
|
4.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 22 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~14 debug messages>
|
|
|
|
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 22 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.26. Executing MEMORY pass.
|
|
|
|
4.26.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[1].GEN_LANE[0].mem write port 0.
|
|
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[0].GEN_LANE[0].mem write port 0.
|
|
|
|
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\dut.GEN_SLOT[1].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
|
|
Write port 0: non-transparent.
|
|
Checking read port `\dut.GEN_SLOT[0].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
|
|
Write port 0: non-transparent.
|
|
|
|
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 2 unused cells and 18 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[1].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_
|
|
Extracted data FF from read port 0 of harness_nms_weight_packed.dut.GEN_SLOT[1].GEN_LANE[0].mem: $\dut.GEN_SLOT[1].GEN_LANE[0].mem$rdreg[0]
|
|
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[0].GEN_LANE[0].mem via $__TRELLIS_DPR16X4_
|
|
Extracted data FF from read port 0 of harness_nms_weight_packed.dut.GEN_SLOT[0].GEN_LANE[0].mem: $\dut.GEN_SLOT[0].GEN_LANE[0].mem$rdreg[0]
|
|
<suppressed ~994 debug messages>
|
|
|
|
4.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.29.3. Continuing TECHMAP pass.
|
|
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
|
|
No more expansions possible.
|
|
<suppressed ~22 debug messages>
|
|
|
|
4.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
<suppressed ~25 debug messages>
|
|
|
|
4.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 16 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 0 unused cells and 34 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.30.5. Finished fast OPT passes.
|
|
|
|
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
4.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 16 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 16 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.32.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
No more expansions possible.
|
|
<suppressed ~88 debug messages>
|
|
|
|
4.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 88 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 1 unused cells and 0 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.34.5. Finished fast OPT passes.
|
|
|
|
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
4.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 87 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.38.2. Continuing TECHMAP pass.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
No more expansions possible.
|
|
<suppressed ~149 debug messages>
|
|
|
|
4.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
4.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in harness_nms_weight_packed.
|
|
|
|
4.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
Removed 0 unused cells and 273 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_weight_packed...
|
|
Found and reported 0 problems.
|
|
|
|
4.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.46. Executing ABC9 pass.
|
|
|
|
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.3. Executing PROC pass (convert processes to netlists).
|
|
|
|
4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1381'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Removed a total of 0 dead cases.
|
|
|
|
4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 0 redundant assignments.
|
|
Promoted 22 assignments to connections.
|
|
|
|
4.46.3.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
4.46.3.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_EN[3:0]$1388
|
|
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_DATA[3:0]$1387
|
|
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_ADDR[3:0]$1386
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1381'.
|
|
|
|
4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1364_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1365_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1366_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1367_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1368_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1369_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1370_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1371_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1372_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1373_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1374_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1375_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1376_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1377_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1378_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1379_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1381'.
|
|
|
|
4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
created $dff cell `$procdff$1432' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
created $dff cell `$procdff$1433' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1380_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
created $dff cell `$procdff$1434' with positive edge clock.
|
|
|
|
4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1406'.
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1382'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1381'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
4.46.4. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module harness_nms_weight_packed.
|
|
Found 0 SCCs.
|
|
|
|
4.46.5. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.6. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.6.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~167 debug messages>
|
|
|
|
4.46.7. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.46.7.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
4.46.7.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Performed a total of 0 changes.
|
|
|
|
4.46.7.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
|
|
4.46.7.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
4.46.7.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.46.8. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.8.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~7 debug messages>
|
|
|
|
4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.12. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.46.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.13.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~171 debug messages>
|
|
|
|
4.46.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.46.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.46.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 0 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_weight_packed..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_weight_packed.
|
|
Performed a total of 0 changes.
|
|
|
|
4.46.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_weight_packed'.
|
|
Computing hashes of 0 cells of `\harness_nms_weight_packed'.
|
|
Finding duplicate cells in `\harness_nms_weight_packed'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_weight_packed..
|
|
|
|
4.46.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_weight_packed.
|
|
|
|
4.46.14.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
|
|
4.46.16. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_nms_weight_packed: replaced 26 cells with 182 new cells, skipped 65 cells.
|
|
replaced 2 cell types:
|
|
7 $_MUX_
|
|
19 $_XOR_
|
|
not replaced 4 cell types:
|
|
1 $scopeinfo
|
|
56 TRELLIS_FF
|
|
4 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
|
|
4 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
|
|
|
|
4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.16.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 78 AND gates and 337 wires from module `harness_nms_weight_packed' to a netlist network with 82 inputs and 71 outputs.
|
|
|
|
4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
4.46.16.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 82/ 71 and = 78 lev = 6 (0.50) mem = 0.01 MB box = 4 bb = 4
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 82/ 71 and = 180 lev = 4 (0.49) mem = 0.01 MB ch = 26 box = 4 bb = 4
|
|
ABC: cst = 0 cls = 26 lit = 26 unused = 226 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 180. Ch = 26. Total mem = 0.06 MB. Peak cut mem = 0.00 MB.
|
|
ABC: P: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: P: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: P: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: F: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: A: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: A: Del = 679.00. Ar = 16.0. Edge = 49. Cut = 902. T = 0.00 sec
|
|
ABC: Total time = 0.00 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: The network is not changed by "&mfs".
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 82/ 71 and = 78 lev = 4 (0.49) mem = 0.01 MB box = 4 bb = 4
|
|
ABC: Mapping (K=4) : lut = 16 edge = 49 lev = 1 (0.16) levB = 1 mem = 0.00 MB
|
|
ABC: LUT = 16 : 2=0 0.0 % 3=15 93.8 % 4=1 6.2 % Ave = 3.06
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.01 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.01 seconds, total: 0.01 seconds
|
|
|
|
4.46.16.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 153 unused cells and 315 unused wires.
|
|
|
|
4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 16
|
|
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 4
|
|
ABC RESULTS: input signals: 12
|
|
ABC RESULTS: output signals: 7
|
|
<suppressed ~306 debug messages>
|
|
Removing temp directory.
|
|
|
|
4.46.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.17.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
|
|
No more expansions possible.
|
|
<suppressed ~15 debug messages>
|
|
Removed 8 unused cells and 442 unused wires.
|
|
|
|
4.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~127 debug messages>
|
|
|
|
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in harness_nms_weight_packed.
|
|
Removed 0 unused cells and 32 unused wires.
|
|
|
|
4.49. Executing AUTONAME pass.
|
|
Renamed 77 objects in module harness_nms_weight_packed.
|
|
<suppressed ~77 debug messages>
|
|
|
|
4.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `harness_nms_weight_packed'. Setting top module to harness_nms_weight_packed.
|
|
|
|
4.50.1. Analyzing design hierarchy..
|
|
Top module: \harness_nms_weight_packed
|
|
|
|
4.50.2. Analyzing design hierarchy..
|
|
Top module: \harness_nms_weight_packed
|
|
Removed 0 unused modules.
|
|
|
|
4.51. Printing statistics.
|
|
|
|
=== harness_nms_weight_packed ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
27 wires
|
|
605 wire bits
|
|
27 public wires
|
|
605 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
1 cells
|
|
1 $scopeinfo
|
|
76 submodules
|
|
16 LUT4
|
|
4 TRELLIS_DPR16X4
|
|
56 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
1 harness_nms_weight_packed
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
27 wires
|
|
605 wire bits
|
|
27 public wires
|
|
605 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
1 cells
|
|
1 $scopeinfo
|
|
76 submodules
|
|
16 LUT4
|
|
4 TRELLIS_DPR16X4
|
|
56 TRELLIS_FF
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4.52. Executing CHECK pass (checking for obvious problems).
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Checking module harness_nms_weight_packed...
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Found and reported 0 problems.
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4.53. Executing JSON backend.
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End of script. Logfile hash: 3b4992a051, time: 0.27s, user: 0.23s, system: 0.01s, MEM: 30.09 MB peak
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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Time spent: 68% 22x read_verilog (0 sec), 11% 1x abc9_exe (0 sec), ...
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