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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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},
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},
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},
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},
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},
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},
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},
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},
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},
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"CH0_LSM_DISABLE": "DONTCARE",
"CH0_MATCH_2_ENABLE": "DONTCARE",
"CH0_MATCH_4_ENABLE": "DONTCARE",
"CH0_MIN_IPG_CNT": "DONTCARE",
"CH0_PCIE_EI_EN": "DONTCARE",
"CH0_PCIE_MODE": "DONTCARE",
"CH0_PCS_DET_TIME_SEL": "DONTCARE",
"CH0_PDEN_SEL": "DONTCARE",
"CH0_PRBS_ENABLE": "DONTCARE",
"CH0_PRBS_LOCK": "DONTCARE",
"CH0_PRBS_SELECTION": "DONTCARE",
"CH0_PROTOCOL": "DONTCARE",
"CH0_RATE_MODE_RX": "DONTCARE",
"CH0_RATE_MODE_TX": "DONTCARE",
"CH0_RCV_DCC_EN": "DONTCARE",
"CH0_REG_BAND_OFFSET": "DONTCARE",
"CH0_REG_BAND_SEL": "DONTCARE",
"CH0_REG_IDAC_EN": "DONTCARE",
"CH0_REG_IDAC_SEL": "DONTCARE",
"CH0_REQ_EN": "DONTCARE",
"CH0_REQ_LVL_SET": "DONTCARE",
"CH0_RIO_MODE": "DONTCARE",
"CH0_RLOS_SEL": "DONTCARE",
"CH0_RPWDNB": "DONTCARE",
"CH0_RTERM_RX": "DONTCARE",
"CH0_RTERM_TX": "DONTCARE",
"CH0_RXIN_CM": "DONTCARE",
"CH0_RXTERM_CM": "DONTCARE",
"CH0_RX_DCO_CK_DIV": "DONTCARE",
"CH0_RX_DIV11_SEL": "DONTCARE",
"CH0_RX_GEAR_BYPASS": "DONTCARE",
"CH0_RX_GEAR_MODE": "DONTCARE",
"CH0_RX_LOS_CEQ": "DONTCARE",
"CH0_RX_LOS_EN": "DONTCARE",
"CH0_RX_LOS_HYST_EN": "DONTCARE",
"CH0_RX_LOS_LVL": "DONTCARE",
"CH0_RX_RATE_SEL": "DONTCARE",
"CH0_RX_SB_BYPASS": "DONTCARE",
"CH0_SB_BYPASS": "DONTCARE",
"CH0_SEL_SD_RX_CLK": "DONTCARE",
"CH0_TDRV_DAT_SEL": "DONTCARE",
"CH0_TDRV_POST_EN": "DONTCARE",
"CH0_TDRV_PRE_EN": "DONTCARE",
"CH0_TDRV_SLICE0_CUR": "DONTCARE",
"CH0_TDRV_SLICE0_SEL": "DONTCARE",
"CH0_TDRV_SLICE1_CUR": "DONTCARE",
"CH0_TDRV_SLICE1_SEL": "DONTCARE",
"CH0_TDRV_SLICE2_CUR": "DONTCARE",
"CH0_TDRV_SLICE2_SEL": "DONTCARE",
"CH0_TDRV_SLICE3_CUR": "DONTCARE",
"CH0_TDRV_SLICE3_SEL": "DONTCARE",
"CH0_TDRV_SLICE4_CUR": "DONTCARE",
"CH0_TDRV_SLICE4_SEL": "DONTCARE",
"CH0_TDRV_SLICE5_CUR": "DONTCARE",
"CH0_TDRV_SLICE5_SEL": "DONTCARE",
"CH0_TPWDNB": "DONTCARE",
"CH0_TXAMPLITUDE": "DONTCARE",
"CH0_TXDEPOST": "DONTCARE",
"CH0_TXDEPRE": "DONTCARE",
"CH0_TX_CM_SEL": "DONTCARE",
"CH0_TX_DIV11_SEL": "DONTCARE",
"CH0_TX_GEAR_BYPASS": "DONTCARE",
"CH0_TX_GEAR_MODE": "DONTCARE",
"CH0_TX_POST_SIGN": "DONTCARE",
"CH0_TX_PRE_SIGN": "DONTCARE",
"CH0_UC_MODE": "DONTCARE",
"CH0_UDF_COMMA_A": "DONTCARE",
"CH0_UDF_COMMA_B": "DONTCARE",
"CH0_UDF_COMMA_MASK": "DONTCARE",
"CH0_WA_BYPASS": "DONTCARE",
"CH0_WA_MODE": "DONTCARE",
"CH1_AUTO_CALIB_EN": "DONTCARE",
"CH1_AUTO_FACQ_EN": "DONTCARE",
"CH1_BAND_THRESHOLD": "DONTCARE",
"CH1_CALIB_CK_MODE": "DONTCARE",
"CH1_CC_MATCH_1": "DONTCARE",
"CH1_CC_MATCH_2": "DONTCARE",
"CH1_CC_MATCH_3": "DONTCARE",
"CH1_CC_MATCH_4": "DONTCARE",
"CH1_CDR_CNT4SEL": "DONTCARE",
"CH1_CDR_CNT8SEL": "DONTCARE",
"CH1_CDR_MAX_RATE": "DONTCARE",
"CH1_CTC_BYPASS": "DONTCARE",
"CH1_DCOATDCFG": "DONTCARE",
"CH1_DCOATDDLY": "DONTCARE",
"CH1_DCOBYPSATD": "DONTCARE",
"CH1_DCOCALDIV": "DONTCARE",
"CH1_DCOCTLGI": "DONTCARE",
"CH1_DCODISBDAVOID": "DONTCARE",
"CH1_DCOFLTDAC": "DONTCARE",
"CH1_DCOFTNRG": "DONTCARE",
"CH1_DCOIOSTUNE": "DONTCARE",
"CH1_DCOITUNE": "DONTCARE",
"CH1_DCOITUNE4LSB": "DONTCARE",
"CH1_DCOIUPDNX2": "DONTCARE",
"CH1_DCONUOFLSB": "DONTCARE",
"CH1_DCOSCALEI": "DONTCARE",
"CH1_DCOSTARTVAL": "DONTCARE",
"CH1_DCOSTEP": "DONTCARE",
"CH1_DEC_BYPASS": "DONTCARE",
"CH1_ENABLE_CG_ALIGN": "DONTCARE",
"CH1_ENC_BYPASS": "DONTCARE",
"CH1_FF_RX_F_CLK_DIS": "DONTCARE",
"CH1_FF_RX_H_CLK_EN": "DONTCARE",
"CH1_FF_TX_F_CLK_DIS": "DONTCARE",
"CH1_FF_TX_H_CLK_EN": "DONTCARE",
"CH1_GE_AN_ENABLE": "DONTCARE",
"CH1_INVERT_RX": "DONTCARE",
"CH1_INVERT_TX": "DONTCARE",
"CH1_LDR_CORE2TX_SEL": "DONTCARE",
"CH1_LDR_RX2CORE_SEL": "DONTCARE",
"CH1_LEQ_OFFSET_SEL": "DONTCARE",
"CH1_LEQ_OFFSET_TRIM": "DONTCARE",
"CH1_LSM_DISABLE": "DONTCARE",
"CH1_MATCH_2_ENABLE": "DONTCARE",
"CH1_MATCH_4_ENABLE": "DONTCARE",
"CH1_MIN_IPG_CNT": "DONTCARE",
"CH1_PCIE_EI_EN": "DONTCARE",
"CH1_PCIE_MODE": "DONTCARE",
"CH1_PCS_DET_TIME_SEL": "DONTCARE",
"CH1_PDEN_SEL": "DONTCARE",
"CH1_PRBS_ENABLE": "DONTCARE",
"CH1_PRBS_LOCK": "DONTCARE",
"CH1_PRBS_SELECTION": "DONTCARE",
"CH1_PROTOCOL": "DONTCARE",
"CH1_RATE_MODE_RX": "DONTCARE",
"CH1_RATE_MODE_TX": "DONTCARE",
"CH1_RCV_DCC_EN": "DONTCARE",
"CH1_REG_BAND_OFFSET": "DONTCARE",
"CH1_REG_BAND_SEL": "DONTCARE",
"CH1_REG_IDAC_EN": "DONTCARE",
"CH1_REG_IDAC_SEL": "DONTCARE",
"CH1_REQ_EN": "DONTCARE",
"CH1_REQ_LVL_SET": "DONTCARE",
"CH1_RIO_MODE": "DONTCARE",
"CH1_RLOS_SEL": "DONTCARE",
"CH1_RPWDNB": "DONTCARE",
"CH1_RTERM_RX": "DONTCARE",
"CH1_RTERM_TX": "DONTCARE",
"CH1_RXIN_CM": "DONTCARE",
"CH1_RXTERM_CM": "DONTCARE",
"CH1_RX_DCO_CK_DIV": "DONTCARE",
"CH1_RX_DIV11_SEL": "DONTCARE",
"CH1_RX_GEAR_BYPASS": "DONTCARE",
"CH1_RX_GEAR_MODE": "DONTCARE",
"CH1_RX_LOS_CEQ": "DONTCARE",
"CH1_RX_LOS_EN": "DONTCARE",
"CH1_RX_LOS_HYST_EN": "DONTCARE",
"CH1_RX_LOS_LVL": "DONTCARE",
"CH1_RX_RATE_SEL": "DONTCARE",
"CH1_RX_SB_BYPASS": "DONTCARE",
"CH1_SB_BYPASS": "DONTCARE",
"CH1_SEL_SD_RX_CLK": "DONTCARE",
"CH1_TDRV_DAT_SEL": "DONTCARE",
"CH1_TDRV_POST_EN": "DONTCARE",
"CH1_TDRV_PRE_EN": "DONTCARE",
"CH1_TDRV_SLICE0_CUR": "DONTCARE",
"CH1_TDRV_SLICE0_SEL": "DONTCARE",
"CH1_TDRV_SLICE1_CUR": "DONTCARE",
"CH1_TDRV_SLICE1_SEL": "DONTCARE",
"CH1_TDRV_SLICE2_CUR": "DONTCARE",
"CH1_TDRV_SLICE2_SEL": "DONTCARE",
"CH1_TDRV_SLICE3_CUR": "DONTCARE",
"CH1_TDRV_SLICE3_SEL": "DONTCARE",
"CH1_TDRV_SLICE4_CUR": "DONTCARE",
"CH1_TDRV_SLICE4_SEL": "DONTCARE",
"CH1_TDRV_SLICE5_CUR": "DONTCARE",
"CH1_TDRV_SLICE5_SEL": "DONTCARE",
"CH1_TPWDNB": "DONTCARE",
"CH1_TXAMPLITUDE": "DONTCARE",
"CH1_TXDEPOST": "DONTCARE",
"CH1_TXDEPRE": "DONTCARE",
"CH1_TX_CM_SEL": "DONTCARE",
"CH1_TX_DIV11_SEL": "DONTCARE",
"CH1_TX_GEAR_BYPASS": "DONTCARE",
"CH1_TX_GEAR_MODE": "DONTCARE",
"CH1_TX_POST_SIGN": "DONTCARE",
"CH1_TX_PRE_SIGN": "DONTCARE",
"CH1_UC_MODE": "DONTCARE",
"CH1_UDF_COMMA_A": "DONTCARE",
"CH1_UDF_COMMA_B": "DONTCARE",
"CH1_UDF_COMMA_MASK": "DONTCARE",
"CH1_WA_BYPASS": "DONTCARE",
"CH1_WA_MODE": "DONTCARE",
"D_BITCLK_FROM_ND_EN": "DONTCARE",
"D_BITCLK_LOCAL_EN": "DONTCARE",
"D_BITCLK_ND_EN": "DONTCARE",
"D_BUS8BIT_SEL": "DONTCARE",
"D_CDR_LOL_SET": "DONTCARE",
"D_CMUSETBIASI": "DONTCARE",
"D_CMUSETI4CPP": "DONTCARE",
"D_CMUSETI4CPZ": "DONTCARE",
"D_CMUSETI4VCO": "DONTCARE",
"D_CMUSETICP4P": "DONTCARE",
"D_CMUSETICP4Z": "DONTCARE",
"D_CMUSETINITVCT": "DONTCARE",
"D_CMUSETISCL4VCO": "DONTCARE",
"D_CMUSETP1GM": "DONTCARE",
"D_CMUSETP2AGM": "DONTCARE",
"D_CMUSETZGM": "DONTCARE",
"D_DCO_CALIB_TIME_SEL": "DONTCARE",
"D_HIGH_MARK": "DONTCARE",
"D_IB_PWDNB": "DONTCARE",
"D_ISETLOS": "DONTCARE",
"D_LOW_MARK": "DONTCARE",
"D_MACROPDB": "DONTCARE",
"D_PD_ISET": "DONTCARE",
"D_PLL_LOL_SET": "DONTCARE",
"D_REFCK_MODE": "DONTCARE",
"D_REQ_ISET": "DONTCARE",
"D_RG_EN": "DONTCARE",
"D_RG_SET": "DONTCARE",
"D_SETICONST_AUX": "DONTCARE",
"D_SETICONST_CH": "DONTCARE",
"D_SETIRPOLY_AUX": "DONTCARE",
"D_SETIRPOLY_CH": "DONTCARE",
"D_SETPLLRC": "DONTCARE",
"D_SYNC_LOCAL_EN": "DONTCARE",
"D_SYNC_ND_EN": "DONTCARE",
"D_TXPLL_PWDNB": "DONTCARE",
"D_TX_MAX_RATE": "DONTCARE",
"D_TX_VCO_CK_DIV": "DONTCARE",
"D_XGE_MODE": "DONTCARE"
},
"ports": {
"CH0_HDINP": {
"direction": "input",
"bits": [ 2 ]
},
"CH1_HDINP": {
"direction": "input",
"bits": [ 3 ]
},
"CH0_HDINN": {
"direction": "input",
"bits": [ 4 ]
},
"CH1_HDINN": {
"direction": "input",
"bits": [ 5 ]
},
"D_TXBIT_CLKP_FROM_ND": {
"direction": "input",
"bits": [ 6 ]
},
"D_TXBIT_CLKN_FROM_ND": {
"direction": "input",
"bits": [ 7 ]
},
"D_SYNC_ND": {
"direction": "input",
"bits": [ 8 ]
},
"D_TXPLL_LOL_FROM_ND": {
"direction": "input",
"bits": [ 9 ]
},
"CH0_RX_REFCLK": {
"direction": "input",
"bits": [ 10 ]
},
"CH1_RX_REFCLK": {
"direction": "input",
"bits": [ 11 ]
},
"CH0_FF_RXI_CLK": {
"direction": "input",
"bits": [ 12 ]
},
"CH1_FF_RXI_CLK": {
"direction": "input",
"bits": [ 13 ]
},
"CH0_FF_TXI_CLK": {
"direction": "input",
"bits": [ 14 ]
},
"CH1_FF_TXI_CLK": {
"direction": "input",
"bits": [ 15 ]
},
"CH0_FF_EBRD_CLK": {
"direction": "input",
"bits": [ 16 ]
},
"CH1_FF_EBRD_CLK": {
"direction": "input",
"bits": [ 17 ]
},
"CH0_FF_TX_D_0": {
"direction": "input",
"bits": [ 18 ]
},
"CH1_FF_TX_D_0": {
"direction": "input",
"bits": [ 19 ]
},
"CH0_FF_TX_D_1": {
"direction": "input",
"bits": [ 20 ]
},
"CH1_FF_TX_D_1": {
"direction": "input",
"bits": [ 21 ]
},
"CH0_FF_TX_D_2": {
"direction": "input",
"bits": [ 22 ]
},
"CH1_FF_TX_D_2": {
"direction": "input",
"bits": [ 23 ]
},
"CH0_FF_TX_D_3": {
"direction": "input",
"bits": [ 24 ]
},
"CH1_FF_TX_D_3": {
"direction": "input",
"bits": [ 25 ]
},
"CH0_FF_TX_D_4": {
"direction": "input",
"bits": [ 26 ]
},
"CH1_FF_TX_D_4": {
"direction": "input",
"bits": [ 27 ]
},
"CH0_FF_TX_D_5": {
"direction": "input",
"bits": [ 28 ]
},
"CH1_FF_TX_D_5": {
"direction": "input",
"bits": [ 29 ]
},
"CH0_FF_TX_D_6": {
"direction": "input",
"bits": [ 30 ]
},
"CH1_FF_TX_D_6": {
"direction": "input",
"bits": [ 31 ]
},
"CH0_FF_TX_D_7": {
"direction": "input",
"bits": [ 32 ]
},
"CH1_FF_TX_D_7": {
"direction": "input",
"bits": [ 33 ]
},
"CH0_FF_TX_D_8": {
"direction": "input",
"bits": [ 34 ]
},
"CH1_FF_TX_D_8": {
"direction": "input",
"bits": [ 35 ]
},
"CH0_FF_TX_D_9": {
"direction": "input",
"bits": [ 36 ]
},
"CH1_FF_TX_D_9": {
"direction": "input",
"bits": [ 37 ]
},
"CH0_FF_TX_D_10": {
"direction": "input",
"bits": [ 38 ]
},
"CH1_FF_TX_D_10": {
"direction": "input",
"bits": [ 39 ]
},
"CH0_FF_TX_D_11": {
"direction": "input",
"bits": [ 40 ]
},
"CH1_FF_TX_D_11": {
"direction": "input",
"bits": [ 41 ]
},
"CH0_FF_TX_D_12": {
"direction": "input",
"bits": [ 42 ]
},
"CH1_FF_TX_D_12": {
"direction": "input",
"bits": [ 43 ]
},
"CH0_FF_TX_D_13": {
"direction": "input",
"bits": [ 44 ]
},
"CH1_FF_TX_D_13": {
"direction": "input",
"bits": [ 45 ]
},
"CH0_FF_TX_D_14": {
"direction": "input",
"bits": [ 46 ]
},
"CH1_FF_TX_D_14": {
"direction": "input",
"bits": [ 47 ]
},
"CH0_FF_TX_D_15": {
"direction": "input",
"bits": [ 48 ]
},
"CH1_FF_TX_D_15": {
"direction": "input",
"bits": [ 49 ]
},
"CH0_FF_TX_D_16": {
"direction": "input",
"bits": [ 50 ]
},
"CH1_FF_TX_D_16": {
"direction": "input",
"bits": [ 51 ]
},
"CH0_FF_TX_D_17": {
"direction": "input",
"bits": [ 52 ]
},
"CH1_FF_TX_D_17": {
"direction": "input",
"bits": [ 53 ]
},
"CH0_FF_TX_D_18": {
"direction": "input",
"bits": [ 54 ]
},
"CH1_FF_TX_D_18": {
"direction": "input",
"bits": [ 55 ]
},
"CH0_FF_TX_D_19": {
"direction": "input",
"bits": [ 56 ]
},
"CH1_FF_TX_D_19": {
"direction": "input",
"bits": [ 57 ]
},
"CH0_FF_TX_D_20": {
"direction": "input",
"bits": [ 58 ]
},
"CH1_FF_TX_D_20": {
"direction": "input",
"bits": [ 59 ]
},
"CH0_FF_TX_D_21": {
"direction": "input",
"bits": [ 60 ]
},
"CH1_FF_TX_D_21": {
"direction": "input",
"bits": [ 61 ]
},
"CH0_FF_TX_D_22": {
"direction": "input",
"bits": [ 62 ]
},
"CH1_FF_TX_D_22": {
"direction": "input",
"bits": [ 63 ]
},
"CH0_FF_TX_D_23": {
"direction": "input",
"bits": [ 64 ]
},
"CH1_FF_TX_D_23": {
"direction": "input",
"bits": [ 65 ]
},
"CH0_FFC_EI_EN": {
"direction": "input",
"bits": [ 66 ]
},
"CH1_FFC_EI_EN": {
"direction": "input",
"bits": [ 67 ]
},
"CH0_FFC_PCIE_DET_EN": {
"direction": "input",
"bits": [ 68 ]
},
"CH1_FFC_PCIE_DET_EN": {
"direction": "input",
"bits": [ 69 ]
},
"CH0_FFC_PCIE_CT": {
"direction": "input",
"bits": [ 70 ]
},
"CH1_FFC_PCIE_CT": {
"direction": "input",
"bits": [ 71 ]
},
"CH0_FFC_SB_INV_RX": {
"direction": "input",
"bits": [ 72 ]
},
"CH1_FFC_SB_INV_RX": {
"direction": "input",
"bits": [ 73 ]
},
"CH0_FFC_ENABLE_CGALIGN": {
"direction": "input",
"bits": [ 74 ]
},
"CH1_FFC_ENABLE_CGALIGN": {
"direction": "input",
"bits": [ 75 ]
},
"CH0_FFC_SIGNAL_DETECT": {
"direction": "input",
"bits": [ 76 ]
},
"CH1_FFC_SIGNAL_DETECT": {
"direction": "input",
"bits": [ 77 ]
},
"CH0_FFC_FB_LOOPBACK": {
"direction": "input",
"bits": [ 78 ]
},
"CH1_FFC_FB_LOOPBACK": {
"direction": "input",
"bits": [ 79 ]
},
"CH0_FFC_SB_PFIFO_LP": {
"direction": "input",
"bits": [ 80 ]
},
"CH1_FFC_SB_PFIFO_LP": {
"direction": "input",
"bits": [ 81 ]
},
"CH0_FFC_PFIFO_CLR": {
"direction": "input",
"bits": [ 82 ]
},
"CH1_FFC_PFIFO_CLR": {
"direction": "input",
"bits": [ 83 ]
},
"CH0_FFC_RATE_MODE_RX": {
"direction": "input",
"bits": [ 84 ]
},
"CH1_FFC_RATE_MODE_RX": {
"direction": "input",
"bits": [ 85 ]
},
"CH0_FFC_RATE_MODE_TX": {
"direction": "input",
"bits": [ 86 ]
},
"CH1_FFC_RATE_MODE_TX": {
"direction": "input",
"bits": [ 87 ]
},
"CH0_FFC_DIV11_MODE_RX": {
"direction": "input",
"bits": [ 88 ]
},
"CH1_FFC_DIV11_MODE_RX": {
"direction": "input",
"bits": [ 89 ]
},
"CH0_FFC_RX_GEAR_MODE": {
"direction": "input",
"bits": [ 90 ]
},
"CH1_FFC_RX_GEAR_MODE": {
"direction": "input",
"bits": [ 91 ]
},
"CH0_FFC_TX_GEAR_MODE": {
"direction": "input",
"bits": [ 92 ]
},
"CH1_FFC_TX_GEAR_MODE": {
"direction": "input",
"bits": [ 93 ]
},
"CH0_FFC_DIV11_MODE_TX": {
"direction": "input",
"bits": [ 94 ]
},
"CH1_FFC_DIV11_MODE_TX": {
"direction": "input",
"bits": [ 95 ]
},
"CH0_FFC_LDR_CORE2TX_EN": {
"direction": "input",
"bits": [ 96 ]
},
"CH1_FFC_LDR_CORE2TX_EN": {
"direction": "input",
"bits": [ 97 ]
},
"CH0_FFC_LANE_TX_RST": {
"direction": "input",
"bits": [ 98 ]
},
"CH1_FFC_LANE_TX_RST": {
"direction": "input",
"bits": [ 99 ]
},
"CH0_FFC_LANE_RX_RST": {
"direction": "input",
"bits": [ 100 ]
},
"CH1_FFC_LANE_RX_RST": {
"direction": "input",
"bits": [ 101 ]
},
"CH0_FFC_RRST": {
"direction": "input",
"bits": [ 102 ]
},
"CH1_FFC_RRST": {
"direction": "input",
"bits": [ 103 ]
},
"CH0_FFC_TXPWDNB": {
"direction": "input",
"bits": [ 104 ]
},
"CH1_FFC_TXPWDNB": {
"direction": "input",
"bits": [ 105 ]
},
"CH0_FFC_RXPWDNB": {
"direction": "input",
"bits": [ 106 ]
},
"CH1_FFC_RXPWDNB": {
"direction": "input",
"bits": [ 107 ]
},
"CH0_LDR_CORE2TX": {
"direction": "input",
"bits": [ 108 ]
},
"CH1_LDR_CORE2TX": {
"direction": "input",
"bits": [ 109 ]
},
"D_SCIWDATA0": {
"direction": "input",
"bits": [ 110 ]
},
"D_SCIWDATA1": {
"direction": "input",
"bits": [ 111 ]
},
"D_SCIWDATA2": {
"direction": "input",
"bits": [ 112 ]
},
"D_SCIWDATA3": {
"direction": "input",
"bits": [ 113 ]
},
"D_SCIWDATA4": {
"direction": "input",
"bits": [ 114 ]
},
"D_SCIWDATA5": {
"direction": "input",
"bits": [ 115 ]
},
"D_SCIWDATA6": {
"direction": "input",
"bits": [ 116 ]
},
"D_SCIWDATA7": {
"direction": "input",
"bits": [ 117 ]
},
"D_SCIADDR0": {
"direction": "input",
"bits": [ 118 ]
},
"D_SCIADDR1": {
"direction": "input",
"bits": [ 119 ]
},
"D_SCIADDR2": {
"direction": "input",
"bits": [ 120 ]
},
"D_SCIADDR3": {
"direction": "input",
"bits": [ 121 ]
},
"D_SCIADDR4": {
"direction": "input",
"bits": [ 122 ]
},
"D_SCIADDR5": {
"direction": "input",
"bits": [ 123 ]
},
"D_SCIENAUX": {
"direction": "input",
"bits": [ 124 ]
},
"D_SCISELAUX": {
"direction": "input",
"bits": [ 125 ]
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