micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
209 lines
11 KiB
Plaintext
209 lines
11 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 93/43848 0%
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Info: logic LUTs: 93/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 104/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 10 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x267d8a3c
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 4/ 108 3%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 104/ 43848 0%
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Info: TRELLIS_COMB: 95/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 172 cells, random placement wirelen = 15989.
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Info: at initial placer iter 0, wirelen = 1106
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Info: at initial placer iter 1, wirelen = 1095
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Info: at initial placer iter 2, wirelen = 994
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Info: at initial placer iter 3, wirelen = 971
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Info: Running main analytical placer, max placement attempts per cell = 10000.
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Info: at iteration #1, type ALL: wirelen solved = 962, spread = 2116, legal = 3978; time = 0.00s
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Info: at iteration #2, type ALL: wirelen solved = 991, spread = 1988, legal = 3748; time = 0.00s
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Info: at iteration #3, type ALL: wirelen solved = 1030, spread = 1908, legal = 2805; time = 0.00s
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Info: at iteration #4, type ALL: wirelen solved = 1033, spread = 1975, legal = 3224; time = 0.00s
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Info: at iteration #5, type ALL: wirelen solved = 1098, spread = 1987, legal = 3050; time = 0.00s
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Info: at iteration #6, type ALL: wirelen solved = 1095, spread = 1975, legal = 3154; time = 0.00s
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Info: at iteration #7, type ALL: wirelen solved = 1104, spread = 1985, legal = 2658; time = 0.00s
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Info: at iteration #8, type ALL: wirelen solved = 1126, spread = 2006, legal = 2807; time = 0.00s
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Info: at iteration #9, type ALL: wirelen solved = 1118, spread = 2008, legal = 3116; time = 0.00s
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Info: at iteration #10, type ALL: wirelen solved = 1157, spread = 2009, legal = 2744; time = 0.00s
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Info: at iteration #11, type ALL: wirelen solved = 1172, spread = 1942, legal = 2283; time = 0.00s
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Info: at iteration #12, type ALL: wirelen solved = 1143, spread = 2031, legal = 2137; time = 0.00s
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Info: at iteration #13, type ALL: wirelen solved = 1184, spread = 1943, legal = 2479; time = 0.00s
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Info: at iteration #14, type ALL: wirelen solved = 1172, spread = 1941, legal = 2420; time = 0.00s
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Info: at iteration #15, type ALL: wirelen solved = 1170, spread = 1948, legal = 2178; time = 0.00s
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Info: at iteration #16, type ALL: wirelen solved = 1172, spread = 2083, legal = 2122; time = 0.00s
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Info: at iteration #17, type ALL: wirelen solved = 1263, spread = 2044, legal = 2189; time = 0.00s
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Info: at iteration #18, type ALL: wirelen solved = 1280, spread = 2077, legal = 2101; time = 0.00s
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Info: at iteration #19, type ALL: wirelen solved = 1302, spread = 2059, legal = 2168; time = 0.00s
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Info: at iteration #20, type ALL: wirelen solved = 1287, spread = 2124, legal = 2319; time = 0.00s
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Info: at iteration #21, type ALL: wirelen solved = 1317, spread = 2071, legal = 2202; time = 0.00s
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Info: at iteration #22, type ALL: wirelen solved = 1294, spread = 2096, legal = 2419; time = 0.00s
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Info: at iteration #23, type ALL: wirelen solved = 1304, spread = 2205, legal = 2564; time = 0.00s
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Info: HeAP Placer Time: 0.08s
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Info: of which solving equations: 0.04s
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Info: of which spreading cells: 0.01s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 2101
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Info: at iteration #5: temp = 0.000000, timing cost = 24, wirelen = 1430
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Info: at iteration #10: temp = 0.000000, timing cost = 22, wirelen = 1391
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Info: at iteration #15: temp = 0.000000, timing cost = 18, wirelen = 1354
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Info: at iteration #15: temp = 0.000000, timing cost = 16, wirelen = 1371
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Info: SA placement time 0.03s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 145.26 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.09 ns
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Info: Slack histogram:
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Info: legend: * represents 2 endpoint(s)
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Info: + represents [1,2) endpoint(s)
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Info: [ 5616, 5922) |**
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Info: [ 5922, 6228) |*+
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Info: [ 6228, 6534) |+
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Info: [ 6534, 6840) |
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Info: [ 6840, 7146) |
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Info: [ 7146, 7452) |
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Info: [ 7452, 7758) |
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Info: [ 7758, 8064) |
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Info: [ 8064, 8370) |
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Info: [ 8370, 8676) |
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Info: [ 8676, 8982) |+
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Info: [ 8982, 9288) |*
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Info: [ 9288, 9594) |+
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Info: [ 9594, 9900) |
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Info: [ 9900, 10206) |
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Info: [ 10206, 10512) |****+
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Info: [ 10512, 10818) |************************************
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Info: [ 10818, 11124) |************************************************************
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Info: [ 11124, 11430) |*************************************
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Info: [ 11430, 11736) |**********************************
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Info: Checksum: 0xc75c98af
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 716 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 853 | 128 708 | 128 708 | 0| 0.16 0.16|
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Info: Routing complete.
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Info: Router1 time 0.16s
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Info: Checksum: 0x81680254
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 4.10 4.10 Source dut.GEN_SLOT[2].mem.0.0.DOA4
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Info: routing 1.03 5.13 Net dut.GEN_SLOT[2].mem.0.0_DOA4[0] (10,10) -> (3,9)
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Info: Sink dut.GEN_SLOT[3].mem.0.0_DOA4_LUT4_Z_1.A
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.31 Source dut.GEN_SLOT[3].mem.0.0_DOA4_LUT4_Z_1.F
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Info: routing 0.55 5.86 Net dut.GEN_SLOT[3].mem.0.0_DOA4[4] (3,9) -> (4,8)
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Info: Sink dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 6.05 Source dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
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Info: routing 0.47 6.52 Net dut.GEN_SLOT[3].mem.0.0_DOA5_LUT4_D_Z_LUT4_D_Z[4] (4,8) -> (3,8)
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Info: Sink chk_TRELLIS_FF_Q_1.M
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Info: setup 0.00 6.52 Source chk_TRELLIS_FF_Q_1.M
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Info: 4.47 ns logic, 2.04 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source seed[5]$tr_io.O
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Info: routing 3.65 3.65 Net seed[5]$TRELLIS_IO_IN (90,11) -> (8,11)
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Info: Sink seed_LUT4_B_Z_LUT4_Z_5.B
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Info: Defined in:
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Info: hardware/v2/nms/synthesis/harness_nms_weight_direct.v:14.23-14.27
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Info: logic 0.18 3.83 Source seed_LUT4_B_Z_LUT4_Z_5.F
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Info: routing 0.12 3.95 Net seed_LUT4_B_Z[5] (8,11) -> (8,11)
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Info: Sink lfsr_TRELLIS_FF_Q_9.DI
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Info: setup 0.00 3.95 Source lfsr_TRELLIS_FF_Q_9.DI
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Info: 0.18 ns logic, 3.77 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_4.Q
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Info: routing 4.04 4.44 Net checksum[6]$TRELLIS_IO_OUT (3,9) -> (90,14)
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Info: Sink checksum[6]$tr_io.I
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: 0.40 ns logic, 4.04 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 153.47 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.95 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.44 ns
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Info: Slack histogram:
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Info: legend: * represents 2 endpoint(s)
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Info: + represents [1,2) endpoint(s)
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Info: [ 5984, 6275) |**+
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Info: [ 6275, 6566) |+
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Info: [ 6566, 6857) |
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Info: [ 6857, 7148) |
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Info: [ 7148, 7439) |
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Info: [ 7439, 7730) |
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Info: [ 7730, 8021) |
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Info: [ 8021, 8312) |
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Info: [ 8312, 8603) |
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Info: [ 8603, 8894) |
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Info: [ 8894, 9185) |
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Info: [ 9185, 9476) |+
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Info: [ 9476, 9767) |*+
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Info: [ 9767, 10058) |
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Info: [ 10058, 10349) |*+
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Info: [ 10349, 10640) |******+
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Info: [ 10640, 10931) |*****************************************+
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Info: [ 10931, 11222) |************************************************************
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Info: [ 11222, 11513) |*******************************+
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Info: [ 11513, 11804) |******************+
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Info: Program finished normally.
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