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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

4952 lines
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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Running command `read_verilog hardware/v2/nms/rtl/nms_activation_banked.v hardware/v2/nms/synthesis/harness_nms_activation_banked.v; chparam -set N_SLOTS 8 -set N_BANKS 8 -set MAX_TILES 16 harness_nms_activation_banked; synth_ecp5 -json hardware/v2/nms/synthesis/act_bank_n8_b8/top.json -top harness_nms_activation_banked' --
1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/rtl/nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\harness_nms_activation_banked'.
Successfully finished Verilog frontend.
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 8
Parameter \MAX_TILES = 16
3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_activation_banked'.
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 8
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$9cc48d641a1813ae7b19310a215305b68f336893\harness_nms_activation_banked'.
4. Executing SYNTH_LATTICE pass.
4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
4.3. Executing HIERARCHY pass (managing design hierarchy).
4.3.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: \nms_activation_banked
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 8
Parameter \MAX_TILES = 16
4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_banked'.
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 8
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
4.3.3. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked
4.3.4. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked
Removing unused module `\nms_activation_banked'.
Removed 1 unused modules.
4.4. Executing PROC pass (convert processes to netlists).
4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443 in module harness_nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448 in module harness_nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed 128 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Marked 264 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827 in module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
Removed a total of 136 dead cases.
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 28 redundant assignments.
Promoted 353 assignments to connections.
4.4.4. Executing PROC_INIT pass (extract init attributes).
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~299 debug messages>
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
1/1: $0\lfsr[31:0]
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
1/3: $0\chk[7:0]
2/3: $1\chk_next[7:0]
3/3: $1\k[31:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$818_DATA[63:0]$2196
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$817_DATA[63:0]$2193
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$816_DATA[63:0]$2190
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$815_DATA[63:0]$2187
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$814_DATA[63:0]$2184
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$813_DATA[63:0]$2181
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$812_DATA[63:0]$2178
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$811_DATA[63:0]$2175
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2172'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2171'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2170'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2169'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2168'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2167'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2166'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2165'.
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
1/4: $1$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2162
2/4: $1$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_DATA[63:0]$2161
3/4: $1$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_ADDR[31:0]$2160
4/4: $0\GEN_BANK[7].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
1/4: $1$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2150
2/4: $1$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_DATA[63:0]$2149
3/4: $1$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_ADDR[31:0]$2148
4/4: $0\GEN_BANK[6].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
1/4: $1$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2138
2/4: $1$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_DATA[63:0]$2137
3/4: $1$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_ADDR[31:0]$2136
4/4: $0\GEN_BANK[5].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
1/4: $1$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2126
2/4: $1$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_DATA[63:0]$2125
3/4: $1$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_ADDR[31:0]$2124
4/4: $0\GEN_BANK[4].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
1/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2114
2/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_DATA[63:0]$2113
3/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_ADDR[31:0]$2112
4/4: $0\GEN_BANK[3].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
1/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2102
2/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_DATA[63:0]$2101
3/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_ADDR[31:0]$2100
4/4: $0\GEN_BANK[2].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
1/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2090
2/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_DATA[63:0]$2089
3/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_ADDR[31:0]$2088
4/4: $0\GEN_BANK[1].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
1/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2078
2/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_DATA[63:0]$2077
3/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_ADDR[31:0]$2076
4/4: $0\GEN_BANK[0].rd_data_r[63:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
1/36: $10\i[31:0]
2/36: $0\slot_bank_stage1[7][2:0]
3/36: $0\slot_bank_stage1[6][2:0]
4/36: $0\slot_bank_stage1[5][2:0]
5/36: $0\slot_bank_stage1[4][2:0]
6/36: $0\slot_bank_stage1[3][2:0]
7/36: $0\slot_bank_stage1[2][2:0]
8/36: $0\slot_bank_stage1[1][2:0]
9/36: $0\slot_bank_stage1[0][2:0]
10/36: $0\ack[7:0]
11/36: $0\ack_stage1[7:0]
12/36: $2\b[31:0]
13/36: $0\bank_rd_addr_stage1[7][0:0]
14/36: $0\bank_rd_en_stage1[7][0:0]
15/36: $0\bank_rd_addr_stage1[6][0:0]
16/36: $0\bank_rd_en_stage1[6][0:0]
17/36: $0\bank_rd_addr_stage1[5][0:0]
18/36: $0\bank_rd_en_stage1[5][0:0]
19/36: $0\bank_rd_addr_stage1[4][0:0]
20/36: $0\bank_rd_en_stage1[4][0:0]
21/36: $0\bank_rd_addr_stage1[3][0:0]
22/36: $0\bank_rd_en_stage1[3][0:0]
23/36: $0\bank_rd_addr_stage1[2][0:0]
24/36: $0\bank_rd_en_stage1[2][0:0]
25/36: $0\bank_rd_addr_stage1[1][0:0]
26/36: $0\bank_rd_en_stage1[1][0:0]
27/36: $0\bank_rd_addr_stage1[0][0:0]
28/36: $0\bank_rd_en_stage1[0][0:0]
29/36: $0\rr_ptr[7][2:0]
30/36: $0\rr_ptr[6][2:0]
31/36: $0\rr_ptr[5][2:0]
32/36: $0\rr_ptr[4][2:0]
33/36: $0\rr_ptr[3][2:0]
34/36: $0\rr_ptr[2][2:0]
35/36: $0\rr_ptr[1][2:0]
36/36: $0\rr_ptr[0][2:0]
Creating decoders for process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
1/584: $64\ack_comb[7:0] [7]
2/584: $71\ack_comb[6:6]
3/584: $70\ack_comb[5:5]
4/584: $69\ack_comb[4:4]
5/584: $68\ack_comb[3:3]
6/584: $67\ack_comb[2:2]
7/584: $66\ack_comb[1:1]
8/584: $65\ack_comb[0:0]
9/584: $8\i[31:0]
10/584: $64\ack_comb[7:0] [6]
11/584: $64\ack_comb[7:0] [5]
12/584: $64\ack_comb[7:0] [4]
13/584: $64\ack_comb[7:0] [3]
14/584: $64\ack_comb[7:0] [2]
15/584: $64\ack_comb[7:0] [1]
16/584: $64\ack_comb[7:0] [0]
17/584: $72\ack_comb[7:7]
18/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$810_DATA[3:0]$2019
19/584: $8\win_first[7][2:0]
20/584: $8\win_tile_idx[7][3:0]
21/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$810_DATA[3:0]$2018
22/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$810_ADDR[2:0]$2017
23/584: $8\win_valid[7][0:0]
24/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$809_DATA[2:0]$2011
25/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$808_DATA[3:0]$2008
26/584: $7\win_first[7][2:0]
27/584: $7\win_tile_idx[7][3:0]
28/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$808_DATA[3:0]$2007
29/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$808_ADDR[2:0]$2006
30/584: $7\win_valid[7][0:0]
31/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$807_DATA[2:0]$2000
32/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$806_DATA[3:0]$1997
33/584: $6\win_first[7][2:0]
34/584: $6\win_tile_idx[7][3:0]
35/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$806_DATA[3:0]$1996
36/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$806_ADDR[2:0]$1995
37/584: $6\win_valid[7][0:0]
38/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$805_DATA[2:0]$1989
39/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$804_DATA[3:0]$1986
40/584: $5\win_first[7][2:0]
41/584: $5\win_tile_idx[7][3:0]
42/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$804_DATA[3:0]$1985
43/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$804_ADDR[2:0]$1984
44/584: $5\win_valid[7][0:0]
45/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$803_DATA[2:0]$1978
46/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$802_DATA[3:0]$1975
47/584: $4\win_first[7][2:0]
48/584: $4\win_tile_idx[7][3:0]
49/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$802_DATA[3:0]$1974
50/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$802_ADDR[2:0]$1973
51/584: $4\win_valid[7][0:0]
52/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$801_DATA[2:0]$1967
53/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$800_DATA[3:0]$1964
54/584: $3\win_first[7][2:0]
55/584: $3\win_tile_idx[7][3:0]
56/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$800_DATA[3:0]$1963
57/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$800_ADDR[2:0]$1962
58/584: $3\win_valid[7][0:0]
59/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$799_DATA[2:0]$1956
60/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$798_DATA[3:0]$1953
61/584: $2\win_first[7][2:0]
62/584: $2\win_tile_idx[7][3:0]
63/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$798_DATA[3:0]$1952
64/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$798_ADDR[2:0]$1951
65/584: $2\win_valid[7][0:0]
66/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$797_DATA[2:0]$1945
67/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$796_DATA[3:0]$1942
68/584: $1\win_first[7][2:0]
69/584: $1\win_tile_idx[7][3:0]
70/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$796_DATA[3:0]$1941
71/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$796_ADDR[2:0]$1940
72/584: $1\win_valid[7][0:0]
73/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$795_DATA[2:0]$1934
74/584: $55\ack_comb[7:0] [7]
75/584: $62\ack_comb[6:6]
76/584: $61\ack_comb[5:5]
77/584: $60\ack_comb[4:4]
78/584: $59\ack_comb[3:3]
79/584: $58\ack_comb[2:2]
80/584: $57\ack_comb[1:1]
81/584: $56\ack_comb[0:0]
82/584: $7\i[31:0]
83/584: $55\ack_comb[7:0] [6]
84/584: $55\ack_comb[7:0] [5]
85/584: $55\ack_comb[7:0] [4]
86/584: $55\ack_comb[7:0] [3]
87/584: $55\ack_comb[7:0] [2]
88/584: $55\ack_comb[7:0] [1]
89/584: $55\ack_comb[7:0] [0]
90/584: $63\ack_comb[7:7]
91/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$794_DATA[3:0]$1899
92/584: $8\win_first[6][2:0]
93/584: $8\win_tile_idx[6][3:0]
94/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$794_DATA[3:0]$1898
95/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$794_ADDR[2:0]$1897
96/584: $8\win_valid[6][0:0]
97/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$793_DATA[2:0]$1891
98/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$792_DATA[3:0]$1888
99/584: $7\win_first[6][2:0]
100/584: $7\win_tile_idx[6][3:0]
101/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$792_DATA[3:0]$1887
102/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$792_ADDR[2:0]$1886
103/584: $7\win_valid[6][0:0]
104/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$791_DATA[2:0]$1880
105/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$790_DATA[3:0]$1877
106/584: $6\win_first[6][2:0]
107/584: $6\win_tile_idx[6][3:0]
108/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$790_DATA[3:0]$1876
109/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$790_ADDR[2:0]$1875
110/584: $6\win_valid[6][0:0]
111/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$789_DATA[2:0]$1869
112/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$788_DATA[3:0]$1866
113/584: $5\win_first[6][2:0]
114/584: $5\win_tile_idx[6][3:0]
115/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$788_DATA[3:0]$1865
116/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$788_ADDR[2:0]$1864
117/584: $5\win_valid[6][0:0]
118/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$787_DATA[2:0]$1858
119/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$786_DATA[3:0]$1855
120/584: $4\win_first[6][2:0]
121/584: $4\win_tile_idx[6][3:0]
122/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$786_DATA[3:0]$1854
123/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$786_ADDR[2:0]$1853
124/584: $4\win_valid[6][0:0]
125/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$785_DATA[2:0]$1847
126/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$784_DATA[3:0]$1844
127/584: $3\win_first[6][2:0]
128/584: $3\win_tile_idx[6][3:0]
129/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$784_DATA[3:0]$1843
130/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$784_ADDR[2:0]$1842
131/584: $3\win_valid[6][0:0]
132/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$783_DATA[2:0]$1836
133/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$782_DATA[3:0]$1833
134/584: $2\win_first[6][2:0]
135/584: $2\win_tile_idx[6][3:0]
136/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$782_DATA[3:0]$1832
137/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$782_ADDR[2:0]$1831
138/584: $2\win_valid[6][0:0]
139/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$781_DATA[2:0]$1825
140/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$780_DATA[3:0]$1822
141/584: $1\win_first[6][2:0]
142/584: $1\win_tile_idx[6][3:0]
143/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$780_DATA[3:0]$1821
144/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$780_ADDR[2:0]$1820
145/584: $1\win_valid[6][0:0]
146/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$779_DATA[2:0]$1814
147/584: $46\ack_comb[7:0] [7]
148/584: $53\ack_comb[6:6]
149/584: $52\ack_comb[5:5]
150/584: $51\ack_comb[4:4]
151/584: $50\ack_comb[3:3]
152/584: $49\ack_comb[2:2]
153/584: $48\ack_comb[1:1]
154/584: $47\ack_comb[0:0]
155/584: $6\i[31:0]
156/584: $46\ack_comb[7:0] [6]
157/584: $46\ack_comb[7:0] [5]
158/584: $46\ack_comb[7:0] [4]
159/584: $46\ack_comb[7:0] [3]
160/584: $46\ack_comb[7:0] [2]
161/584: $46\ack_comb[7:0] [1]
162/584: $46\ack_comb[7:0] [0]
163/584: $54\ack_comb[7:7]
164/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$778_DATA[3:0]$1779
165/584: $8\win_first[5][2:0]
166/584: $8\win_tile_idx[5][3:0]
167/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$778_DATA[3:0]$1778
168/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$778_ADDR[2:0]$1777
169/584: $8\win_valid[5][0:0]
170/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$777_DATA[2:0]$1771
171/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$776_DATA[3:0]$1768
172/584: $7\win_first[5][2:0]
173/584: $7\win_tile_idx[5][3:0]
174/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$776_DATA[3:0]$1767
175/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$776_ADDR[2:0]$1766
176/584: $7\win_valid[5][0:0]
177/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$775_DATA[2:0]$1760
178/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$774_DATA[3:0]$1757
179/584: $6\win_first[5][2:0]
180/584: $6\win_tile_idx[5][3:0]
181/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$774_DATA[3:0]$1756
182/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$774_ADDR[2:0]$1755
183/584: $6\win_valid[5][0:0]
184/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$773_DATA[2:0]$1749
185/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$772_DATA[3:0]$1746
186/584: $5\win_first[5][2:0]
187/584: $5\win_tile_idx[5][3:0]
188/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$772_DATA[3:0]$1745
189/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$772_ADDR[2:0]$1744
190/584: $5\win_valid[5][0:0]
191/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$771_DATA[2:0]$1738
192/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$770_DATA[3:0]$1735
193/584: $4\win_first[5][2:0]
194/584: $4\win_tile_idx[5][3:0]
195/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$770_DATA[3:0]$1734
196/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$770_ADDR[2:0]$1733
197/584: $4\win_valid[5][0:0]
198/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$769_DATA[2:0]$1727
199/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$768_DATA[3:0]$1724
200/584: $3\win_first[5][2:0]
201/584: $3\win_tile_idx[5][3:0]
202/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$768_DATA[3:0]$1723
203/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$768_ADDR[2:0]$1722
204/584: $3\win_valid[5][0:0]
205/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$767_DATA[2:0]$1716
206/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$766_DATA[3:0]$1713
207/584: $2\win_first[5][2:0]
208/584: $2\win_tile_idx[5][3:0]
209/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$766_DATA[3:0]$1712
210/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$766_ADDR[2:0]$1711
211/584: $2\win_valid[5][0:0]
212/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$765_DATA[2:0]$1705
213/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$764_DATA[3:0]$1702
214/584: $1\win_first[5][2:0]
215/584: $1\win_tile_idx[5][3:0]
216/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$764_DATA[3:0]$1701
217/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$764_ADDR[2:0]$1700
218/584: $1\win_valid[5][0:0]
219/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$763_DATA[2:0]$1694
220/584: $37\ack_comb[7:0] [7]
221/584: $44\ack_comb[6:6]
222/584: $43\ack_comb[5:5]
223/584: $42\ack_comb[4:4]
224/584: $41\ack_comb[3:3]
225/584: $40\ack_comb[2:2]
226/584: $39\ack_comb[1:1]
227/584: $38\ack_comb[0:0]
228/584: $5\i[31:0]
229/584: $37\ack_comb[7:0] [6]
230/584: $37\ack_comb[7:0] [5]
231/584: $37\ack_comb[7:0] [4]
232/584: $37\ack_comb[7:0] [3]
233/584: $37\ack_comb[7:0] [2]
234/584: $37\ack_comb[7:0] [1]
235/584: $37\ack_comb[7:0] [0]
236/584: $45\ack_comb[7:7]
237/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$762_DATA[3:0]$1659
238/584: $8\win_first[4][2:0]
239/584: $8\win_tile_idx[4][3:0]
240/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$762_DATA[3:0]$1658
241/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$762_ADDR[2:0]$1657
242/584: $8\win_valid[4][0:0]
243/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$761_DATA[2:0]$1651
244/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$760_DATA[3:0]$1648
245/584: $7\win_first[4][2:0]
246/584: $7\win_tile_idx[4][3:0]
247/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$760_DATA[3:0]$1647
248/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$760_ADDR[2:0]$1646
249/584: $7\win_valid[4][0:0]
250/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$759_DATA[2:0]$1640
251/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$758_DATA[3:0]$1637
252/584: $6\win_first[4][2:0]
253/584: $6\win_tile_idx[4][3:0]
254/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$758_DATA[3:0]$1636
255/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$758_ADDR[2:0]$1635
256/584: $6\win_valid[4][0:0]
257/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$757_DATA[2:0]$1629
258/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$756_DATA[3:0]$1626
259/584: $5\win_first[4][2:0]
260/584: $5\win_tile_idx[4][3:0]
261/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$756_DATA[3:0]$1625
262/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$756_ADDR[2:0]$1624
263/584: $5\win_valid[4][0:0]
264/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$755_DATA[2:0]$1618
265/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$754_DATA[3:0]$1615
266/584: $4\win_first[4][2:0]
267/584: $4\win_tile_idx[4][3:0]
268/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$754_DATA[3:0]$1614
269/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$754_ADDR[2:0]$1613
270/584: $4\win_valid[4][0:0]
271/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$753_DATA[2:0]$1607
272/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$752_DATA[3:0]$1604
273/584: $3\win_first[4][2:0]
274/584: $3\win_tile_idx[4][3:0]
275/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$752_DATA[3:0]$1603
276/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$752_ADDR[2:0]$1602
277/584: $3\win_valid[4][0:0]
278/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$751_DATA[2:0]$1596
279/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$750_DATA[3:0]$1593
280/584: $2\win_first[4][2:0]
281/584: $2\win_tile_idx[4][3:0]
282/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$750_DATA[3:0]$1592
283/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$750_ADDR[2:0]$1591
284/584: $2\win_valid[4][0:0]
285/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$749_DATA[2:0]$1585
286/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$748_DATA[3:0]$1582
287/584: $1\win_first[4][2:0]
288/584: $1\win_tile_idx[4][3:0]
289/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$748_DATA[3:0]$1581
290/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$748_ADDR[2:0]$1580
291/584: $1\win_valid[4][0:0]
292/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$747_DATA[2:0]$1574
293/584: $28\ack_comb[7:0] [7]
294/584: $35\ack_comb[6:6]
295/584: $34\ack_comb[5:5]
296/584: $33\ack_comb[4:4]
297/584: $32\ack_comb[3:3]
298/584: $31\ack_comb[2:2]
299/584: $30\ack_comb[1:1]
300/584: $29\ack_comb[0:0]
301/584: $4\i[31:0]
302/584: $28\ack_comb[7:0] [6]
303/584: $28\ack_comb[7:0] [5]
304/584: $28\ack_comb[7:0] [4]
305/584: $28\ack_comb[7:0] [3]
306/584: $28\ack_comb[7:0] [2]
307/584: $28\ack_comb[7:0] [1]
308/584: $28\ack_comb[7:0] [0]
309/584: $36\ack_comb[7:7]
310/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_DATA[3:0]$1539
311/584: $8\win_first[3][2:0]
312/584: $8\win_tile_idx[3][3:0]
313/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_DATA[3:0]$1538
314/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_ADDR[2:0]$1537
315/584: $8\win_valid[3][0:0]
316/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$745_DATA[2:0]$1531
317/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_DATA[3:0]$1528
318/584: $7\win_first[3][2:0]
319/584: $7\win_tile_idx[3][3:0]
320/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_DATA[3:0]$1527
321/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_ADDR[2:0]$1526
322/584: $7\win_valid[3][0:0]
323/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$743_DATA[2:0]$1520
324/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_DATA[3:0]$1517
325/584: $6\win_first[3][2:0]
326/584: $6\win_tile_idx[3][3:0]
327/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_DATA[3:0]$1516
328/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_ADDR[2:0]$1515
329/584: $6\win_valid[3][0:0]
330/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$741_DATA[2:0]$1509
331/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_DATA[3:0]$1506
332/584: $5\win_first[3][2:0]
333/584: $5\win_tile_idx[3][3:0]
334/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_DATA[3:0]$1505
335/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_ADDR[2:0]$1504
336/584: $5\win_valid[3][0:0]
337/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$739_DATA[2:0]$1498
338/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_DATA[3:0]$1495
339/584: $4\win_first[3][2:0]
340/584: $4\win_tile_idx[3][3:0]
341/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_DATA[3:0]$1494
342/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_ADDR[2:0]$1493
343/584: $4\win_valid[3][0:0]
344/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$737_DATA[2:0]$1487
345/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_DATA[3:0]$1484
346/584: $3\win_first[3][2:0]
347/584: $3\win_tile_idx[3][3:0]
348/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_DATA[3:0]$1483
349/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_ADDR[2:0]$1482
350/584: $3\win_valid[3][0:0]
351/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$735_DATA[2:0]$1476
352/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_DATA[3:0]$1473
353/584: $2\win_first[3][2:0]
354/584: $2\win_tile_idx[3][3:0]
355/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_DATA[3:0]$1472
356/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_ADDR[2:0]$1471
357/584: $2\win_valid[3][0:0]
358/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$733_DATA[2:0]$1465
359/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_DATA[3:0]$1462
360/584: $1\win_first[3][2:0]
361/584: $1\win_tile_idx[3][3:0]
362/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_DATA[3:0]$1461
363/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_ADDR[2:0]$1460
364/584: $1\win_valid[3][0:0]
365/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$731_DATA[2:0]$1454
366/584: $19\ack_comb[7:0] [7]
367/584: $26\ack_comb[6:6]
368/584: $25\ack_comb[5:5]
369/584: $24\ack_comb[4:4]
370/584: $23\ack_comb[3:3]
371/584: $22\ack_comb[2:2]
372/584: $21\ack_comb[1:1]
373/584: $20\ack_comb[0:0]
374/584: $3\i[31:0]
375/584: $19\ack_comb[7:0] [6]
376/584: $19\ack_comb[7:0] [5]
377/584: $19\ack_comb[7:0] [4]
378/584: $19\ack_comb[7:0] [3]
379/584: $19\ack_comb[7:0] [2]
380/584: $19\ack_comb[7:0] [1]
381/584: $19\ack_comb[7:0] [0]
382/584: $27\ack_comb[7:7]
383/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_DATA[3:0]$1419
384/584: $8\win_first[2][2:0]
385/584: $8\win_tile_idx[2][3:0]
386/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_DATA[3:0]$1418
387/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_ADDR[2:0]$1417
388/584: $8\win_valid[2][0:0]
389/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$729_DATA[2:0]$1411
390/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_DATA[3:0]$1408
391/584: $7\win_first[2][2:0]
392/584: $7\win_tile_idx[2][3:0]
393/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_DATA[3:0]$1407
394/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_ADDR[2:0]$1406
395/584: $7\win_valid[2][0:0]
396/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$727_DATA[2:0]$1400
397/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_DATA[3:0]$1397
398/584: $6\win_first[2][2:0]
399/584: $6\win_tile_idx[2][3:0]
400/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_DATA[3:0]$1396
401/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_ADDR[2:0]$1395
402/584: $6\win_valid[2][0:0]
403/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$725_DATA[2:0]$1389
404/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_DATA[3:0]$1386
405/584: $5\win_first[2][2:0]
406/584: $5\win_tile_idx[2][3:0]
407/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_DATA[3:0]$1385
408/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_ADDR[2:0]$1384
409/584: $5\win_valid[2][0:0]
410/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$723_DATA[2:0]$1378
411/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_DATA[3:0]$1375
412/584: $4\win_first[2][2:0]
413/584: $4\win_tile_idx[2][3:0]
414/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_DATA[3:0]$1374
415/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_ADDR[2:0]$1373
416/584: $4\win_valid[2][0:0]
417/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$721_DATA[2:0]$1367
418/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_DATA[3:0]$1364
419/584: $3\win_first[2][2:0]
420/584: $3\win_tile_idx[2][3:0]
421/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_DATA[3:0]$1363
422/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_ADDR[2:0]$1362
423/584: $3\win_valid[2][0:0]
424/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$719_DATA[2:0]$1356
425/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_DATA[3:0]$1353
426/584: $2\win_first[2][2:0]
427/584: $2\win_tile_idx[2][3:0]
428/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_DATA[3:0]$1352
429/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_ADDR[2:0]$1351
430/584: $2\win_valid[2][0:0]
431/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$717_DATA[2:0]$1345
432/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_DATA[3:0]$1342
433/584: $1\win_first[2][2:0]
434/584: $1\win_tile_idx[2][3:0]
435/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_DATA[3:0]$1341
436/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_ADDR[2:0]$1340
437/584: $1\win_valid[2][0:0]
438/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$715_DATA[2:0]$1334
439/584: $10\ack_comb[7:0] [7]
440/584: $17\ack_comb[6:6]
441/584: $16\ack_comb[5:5]
442/584: $15\ack_comb[4:4]
443/584: $14\ack_comb[3:3]
444/584: $13\ack_comb[2:2]
445/584: $12\ack_comb[1:1]
446/584: $11\ack_comb[0:0]
447/584: $2\i[31:0]
448/584: $10\ack_comb[7:0] [6]
449/584: $10\ack_comb[7:0] [5]
450/584: $10\ack_comb[7:0] [4]
451/584: $10\ack_comb[7:0] [3]
452/584: $10\ack_comb[7:0] [2]
453/584: $10\ack_comb[7:0] [1]
454/584: $10\ack_comb[7:0] [0]
455/584: $18\ack_comb[7:7]
456/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_DATA[3:0]$1299
457/584: $8\win_first[1][2:0]
458/584: $8\win_tile_idx[1][3:0]
459/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_DATA[3:0]$1298
460/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_ADDR[2:0]$1297
461/584: $8\win_valid[1][0:0]
462/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$713_DATA[2:0]$1291
463/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_DATA[3:0]$1288
464/584: $7\win_first[1][2:0]
465/584: $7\win_tile_idx[1][3:0]
466/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_DATA[3:0]$1287
467/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_ADDR[2:0]$1286
468/584: $7\win_valid[1][0:0]
469/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$711_DATA[2:0]$1280
470/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1277
471/584: $6\win_first[1][2:0]
472/584: $6\win_tile_idx[1][3:0]
473/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1276
474/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_ADDR[2:0]$1275
475/584: $6\win_valid[1][0:0]
476/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$709_DATA[2:0]$1269
477/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$1266
478/584: $5\win_first[1][2:0]
479/584: $5\win_tile_idx[1][3:0]
480/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$1265
481/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_ADDR[2:0]$1264
482/584: $5\win_valid[1][0:0]
483/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$707_DATA[2:0]$1258
484/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$1255
485/584: $4\win_first[1][2:0]
486/584: $4\win_tile_idx[1][3:0]
487/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$1254
488/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_ADDR[2:0]$1253
489/584: $4\win_valid[1][0:0]
490/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$705_DATA[2:0]$1247
491/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$1244
492/584: $3\win_first[1][2:0]
493/584: $3\win_tile_idx[1][3:0]
494/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$1243
495/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_ADDR[2:0]$1242
496/584: $3\win_valid[1][0:0]
497/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$703_DATA[2:0]$1236
498/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$1233
499/584: $2\win_first[1][2:0]
500/584: $2\win_tile_idx[1][3:0]
501/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$1232
502/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_ADDR[2:0]$1231
503/584: $2\win_valid[1][0:0]
504/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$701_DATA[2:0]$1225
505/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$1222
506/584: $1\win_first[1][2:0]
507/584: $1\win_tile_idx[1][3:0]
508/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$1221
509/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_ADDR[2:0]$1220
510/584: $1\win_valid[1][0:0]
511/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$699_DATA[2:0]$1214
512/584: $1\ack_comb[7:0] [7]
513/584: $8\ack_comb[6:6]
514/584: $7\ack_comb[5:5]
515/584: $6\ack_comb[4:4]
516/584: $5\ack_comb[3:3]
517/584: $4\ack_comb[2:2]
518/584: $3\ack_comb[1:1]
519/584: $2\ack_comb[0:0]
520/584: $1\i[31:0]
521/584: $1\ack_comb[7:0] [6]
522/584: $1\ack_comb[7:0] [5]
523/584: $1\ack_comb[7:0] [4]
524/584: $1\ack_comb[7:0] [3]
525/584: $1\ack_comb[7:0] [2]
526/584: $1\ack_comb[7:0] [1]
527/584: $1\ack_comb[7:0] [0]
528/584: $9\ack_comb[7:7]
529/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$1179
530/584: $8\win_first[0][2:0]
531/584: $8\win_tile_idx[0][3:0]
532/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$1178
533/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_ADDR[2:0]$1177
534/584: $8\win_valid[0][0:0]
535/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$697_DATA[2:0]$1171
536/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$1168
537/584: $7\win_first[0][2:0]
538/584: $7\win_tile_idx[0][3:0]
539/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$1167
540/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_ADDR[2:0]$1166
541/584: $7\win_valid[0][0:0]
542/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$695_DATA[2:0]$1160
543/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$1157
544/584: $6\win_first[0][2:0]
545/584: $6\win_tile_idx[0][3:0]
546/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$1156
547/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_ADDR[2:0]$1155
548/584: $6\win_valid[0][0:0]
549/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$693_DATA[2:0]$1149
550/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$1146
551/584: $5\win_first[0][2:0]
552/584: $5\win_tile_idx[0][3:0]
553/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$1145
554/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_ADDR[2:0]$1144
555/584: $5\win_valid[0][0:0]
556/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$691_DATA[2:0]$1138
557/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$1135
558/584: $4\win_first[0][2:0]
559/584: $4\win_tile_idx[0][3:0]
560/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$1134
561/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_ADDR[2:0]$1133
562/584: $4\win_valid[0][0:0]
563/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$689_DATA[2:0]$1127
564/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$1124
565/584: $3\win_first[0][2:0]
566/584: $3\win_tile_idx[0][3:0]
567/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$1123
568/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_ADDR[2:0]$1122
569/584: $3\win_valid[0][0:0]
570/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$687_DATA[2:0]$1116
571/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$1113
572/584: $2\win_first[0][2:0]
573/584: $2\win_tile_idx[0][3:0]
574/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$1112
575/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_ADDR[2:0]$1111
576/584: $2\win_valid[0][0:0]
577/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$685_DATA[2:0]$1105
578/584: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$1102
579/584: $1\win_first[0][2:0]
580/584: $1\win_tile_idx[0][3:0]
581/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$1101
582/584: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_ADDR[2:0]$1100
583/584: $1\win_valid[0][0:0]
584/584: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$683_DATA[2:0]$1094
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$818_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$817_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$816_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$815_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$814_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$813_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$812_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$811_DATA' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2172'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2171'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2170'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2169'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2168'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2167'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2166'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_data_reg[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2165'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\b' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\i' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\ack_comb' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\scan_i' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\cand' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[0]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[1]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[2]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[3]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_tile_idx[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\req_bank[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_comb[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_valid[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_tile_idx[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[4]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[5]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[6]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
No latch inferred for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\win_first[7]' from process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\harness_nms_activation_banked.\lfsr' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
created $dff cell `$procdff$5394' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\k' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$5395' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$5396' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk_next' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$5397' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[7].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
created $dff cell `$procdff$5398' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
created $dff cell `$procdff$5399' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
created $dff cell `$procdff$5400' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
created $dff cell `$procdff$5401' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[6].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
created $dff cell `$procdff$5402' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
created $dff cell `$procdff$5403' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
created $dff cell `$procdff$5404' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
created $dff cell `$procdff$5405' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[5].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
created $dff cell `$procdff$5406' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
created $dff cell `$procdff$5407' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
created $dff cell `$procdff$5408' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
created $dff cell `$procdff$5409' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[4].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
created $dff cell `$procdff$5410' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
created $dff cell `$procdff$5411' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
created $dff cell `$procdff$5412' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
created $dff cell `$procdff$5413' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[3].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
created $dff cell `$procdff$5414' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
created $dff cell `$procdff$5415' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
created $dff cell `$procdff$5416' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
created $dff cell `$procdff$5417' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[2].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
created $dff cell `$procdff$5418' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
created $dff cell `$procdff$5419' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
created $dff cell `$procdff$5420' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
created $dff cell `$procdff$5421' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[1].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
created $dff cell `$procdff$5422' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
created $dff cell `$procdff$5423' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
created $dff cell `$procdff$5424' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
created $dff cell `$procdff$5425' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\GEN_BANK[0].rd_data_r' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
created $dff cell `$procdff$5426' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_ADDR' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
created $dff cell `$procdff$5427' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_DATA' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
created $dff cell `$procdff$5428' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
created $dff cell `$procdff$5429' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\b' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5430' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\i' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5431' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\ack' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5432' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\ack_stage1' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5433' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[0]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5434' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[1]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5435' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[2]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5436' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[3]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5437' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[0]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5438' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[1]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5439' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[2]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5440' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[3]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5441' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[0]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5442' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[1]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5443' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[2]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5444' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[3]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5445' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[0]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5446' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[1]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5447' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[2]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5448' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[3]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5449' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[4]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5450' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[5]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5451' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[6]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5452' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\rr_ptr[7]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5453' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[4]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5454' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[5]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5455' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[6]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5456' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_en_stage1[7]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5457' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[4]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5458' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[5]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5459' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[6]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5460' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\bank_rd_addr_stage1[7]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5461' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[4]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5462' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[5]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5463' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[6]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5464' with positive edge clock.
Creating register for signal `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.\slot_bank_stage1[7]' using process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
created $dff cell `$procdff$5465' with positive edge clock.
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2194'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2191'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2188'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2185'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2182'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2179'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2176'.
Found and cleaned up 1 empty switch in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$2173'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2172'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2171'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2170'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2169'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2168'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2167'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2166'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$2165'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2156'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2144'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2132'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2120'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2108'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2096'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2084'.
Found and cleaned up 2 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$2072'.
Found and cleaned up 9 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$2052'.
Found and cleaned up 264 empty switches in `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
Removing empty process `$paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$827'.
Cleaned up 299 empty switches.
4.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~1 debug messages>
Optimizing module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
<suppressed ~176 debug messages>
4.5. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Checking module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked...
Warning: Drivers conflicting with a constant 1'0 driver:
port Q[0] of cell $procdff$5431 ($dff)
port Q[1] of cell $procdff$5431 ($dff)
port Q[2] of cell $procdff$5431 ($dff)
port Q[4] of cell $procdff$5431 ($dff)
port Q[5] of cell $procdff$5431 ($dff)
port Q[6] of cell $procdff$5431 ($dff)
port Q[7] of cell $procdff$5431 ($dff)
port Q[8] of cell $procdff$5431 ($dff)
port Q[9] of cell $procdff$5431 ($dff)
port Q[10] of cell $procdff$5431 ($dff)
port Q[11] of cell $procdff$5431 ($dff)
port Q[12] of cell $procdff$5431 ($dff)
port Q[13] of cell $procdff$5431 ($dff)
port Q[14] of cell $procdff$5431 ($dff)
port Q[15] of cell $procdff$5431 ($dff)
port Q[16] of cell $procdff$5431 ($dff)
port Q[17] of cell $procdff$5431 ($dff)
port Q[18] of cell $procdff$5431 ($dff)
port Q[19] of cell $procdff$5431 ($dff)
port Q[20] of cell $procdff$5431 ($dff)
port Q[21] of cell $procdff$5431 ($dff)
port Q[22] of cell $procdff$5431 ($dff)
port Q[23] of cell $procdff$5431 ($dff)
port Q[24] of cell $procdff$5431 ($dff)
port Q[25] of cell $procdff$5431 ($dff)
port Q[26] of cell $procdff$5431 ($dff)
port Q[27] of cell $procdff$5431 ($dff)
port Q[28] of cell $procdff$5431 ($dff)
port Q[29] of cell $procdff$5431 ($dff)
port Q[30] of cell $procdff$5431 ($dff)
port Q[31] of cell $procdff$5431 ($dff)
port Q[0] of cell $procdff$5430 ($dff)
port Q[1] of cell $procdff$5430 ($dff)
port Q[2] of cell $procdff$5430 ($dff)
port Q[4] of cell $procdff$5430 ($dff)
port Q[5] of cell $procdff$5430 ($dff)
port Q[6] of cell $procdff$5430 ($dff)
port Q[7] of cell $procdff$5430 ($dff)
port Q[8] of cell $procdff$5430 ($dff)
port Q[9] of cell $procdff$5430 ($dff)
port Q[10] of cell $procdff$5430 ($dff)
port Q[11] of cell $procdff$5430 ($dff)
port Q[12] of cell $procdff$5430 ($dff)
port Q[13] of cell $procdff$5430 ($dff)
port Q[14] of cell $procdff$5430 ($dff)
port Q[15] of cell $procdff$5430 ($dff)
port Q[16] of cell $procdff$5430 ($dff)
port Q[17] of cell $procdff$5430 ($dff)
port Q[18] of cell $procdff$5430 ($dff)
port Q[19] of cell $procdff$5430 ($dff)
port Q[20] of cell $procdff$5430 ($dff)
port Q[21] of cell $procdff$5430 ($dff)
port Q[22] of cell $procdff$5430 ($dff)
port Q[23] of cell $procdff$5430 ($dff)
port Q[24] of cell $procdff$5430 ($dff)
port Q[25] of cell $procdff$5430 ($dff)
port Q[26] of cell $procdff$5430 ($dff)
port Q[27] of cell $procdff$5430 ($dff)
port Q[28] of cell $procdff$5430 ($dff)
port Q[29] of cell $procdff$5430 ($dff)
port Q[30] of cell $procdff$5430 ($dff)
port Q[31] of cell $procdff$5430 ($dff)
Warning: Drivers conflicting with a constant 1'1 driver:
port Q[3] of cell $procdff$5431 ($dff)
port Q[3] of cell $procdff$5430 ($dff)
Found and reported 2 problems.
4.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$2c10e2177787145d3e4fe7ee78855d90f508fce7\nms_activation_banked.
<suppressed ~1 debug messages>
4.7. Executing TRIBUF pass.
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
4.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~200 debug messages>
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 158 unused cells and 2220 unused wires.
<suppressed ~169 debug messages>
4.11. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.12. Executing OPT pass (performing simple optimizations).
4.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 2461 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1942 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1935 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~1578 debug messages>
Removed a total of 526 cells.
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $flatten\dut.$procmux$2498.
dead port 2/2 on $mux $flatten\dut.$procmux$2504.
dead port 2/2 on $mux $flatten\dut.$procmux$2510.
dead port 2/2 on $mux $flatten\dut.$procmux$2516.
dead port 2/2 on $mux $flatten\dut.$procmux$2522.
dead port 2/2 on $mux $flatten\dut.$procmux$2528.
dead port 2/2 on $mux $flatten\dut.$procmux$2534.
dead port 2/2 on $mux $flatten\dut.$procmux$2564.
dead port 2/2 on $mux $flatten\dut.$procmux$2576.
dead port 2/2 on $mux $flatten\dut.$procmux$2612.
dead port 2/2 on $mux $flatten\dut.$procmux$2648.
dead port 2/2 on $mux $flatten\dut.$procmux$2684.
dead port 2/2 on $mux $flatten\dut.$procmux$2720.
dead port 2/2 on $mux $flatten\dut.$procmux$2756.
dead port 2/2 on $mux $flatten\dut.$procmux$2792.
dead port 2/2 on $mux $flatten\dut.$procmux$2828.
dead port 2/2 on $mux $flatten\dut.$procmux$2861.
dead port 2/2 on $mux $flatten\dut.$procmux$2867.
dead port 2/2 on $mux $flatten\dut.$procmux$2873.
dead port 2/2 on $mux $flatten\dut.$procmux$2879.
dead port 2/2 on $mux $flatten\dut.$procmux$2885.
dead port 2/2 on $mux $flatten\dut.$procmux$2891.
dead port 2/2 on $mux $flatten\dut.$procmux$2897.
dead port 2/2 on $mux $flatten\dut.$procmux$2927.
dead port 2/2 on $mux $flatten\dut.$procmux$2939.
dead port 2/2 on $mux $flatten\dut.$procmux$2975.
dead port 2/2 on $mux $flatten\dut.$procmux$3011.
dead port 2/2 on $mux $flatten\dut.$procmux$3047.
dead port 2/2 on $mux $flatten\dut.$procmux$3083.
dead port 2/2 on $mux $flatten\dut.$procmux$3119.
dead port 2/2 on $mux $flatten\dut.$procmux$3155.
dead port 2/2 on $mux $flatten\dut.$procmux$3191.
dead port 2/2 on $mux $flatten\dut.$procmux$3224.
dead port 2/2 on $mux $flatten\dut.$procmux$3230.
dead port 2/2 on $mux $flatten\dut.$procmux$3236.
dead port 2/2 on $mux $flatten\dut.$procmux$3242.
dead port 2/2 on $mux $flatten\dut.$procmux$3248.
dead port 2/2 on $mux $flatten\dut.$procmux$3254.
dead port 2/2 on $mux $flatten\dut.$procmux$3260.
dead port 2/2 on $mux $flatten\dut.$procmux$3290.
dead port 2/2 on $mux $flatten\dut.$procmux$3302.
dead port 2/2 on $mux $flatten\dut.$procmux$3338.
dead port 2/2 on $mux $flatten\dut.$procmux$3374.
dead port 2/2 on $mux $flatten\dut.$procmux$3410.
dead port 2/2 on $mux $flatten\dut.$procmux$3446.
dead port 2/2 on $mux $flatten\dut.$procmux$3482.
dead port 2/2 on $mux $flatten\dut.$procmux$3518.
dead port 2/2 on $mux $flatten\dut.$procmux$3554.
dead port 2/2 on $mux $flatten\dut.$procmux$3587.
dead port 2/2 on $mux $flatten\dut.$procmux$3593.
dead port 2/2 on $mux $flatten\dut.$procmux$3599.
dead port 2/2 on $mux $flatten\dut.$procmux$3605.
dead port 2/2 on $mux $flatten\dut.$procmux$3611.
dead port 2/2 on $mux $flatten\dut.$procmux$3617.
dead port 2/2 on $mux $flatten\dut.$procmux$3623.
dead port 2/2 on $mux $flatten\dut.$procmux$3653.
dead port 2/2 on $mux $flatten\dut.$procmux$3665.
dead port 2/2 on $mux $flatten\dut.$procmux$3701.
dead port 2/2 on $mux $flatten\dut.$procmux$3737.
dead port 2/2 on $mux $flatten\dut.$procmux$3773.
dead port 2/2 on $mux $flatten\dut.$procmux$3809.
dead port 2/2 on $mux $flatten\dut.$procmux$3845.
dead port 2/2 on $mux $flatten\dut.$procmux$3881.
dead port 2/2 on $mux $flatten\dut.$procmux$3917.
dead port 2/2 on $mux $flatten\dut.$procmux$3950.
dead port 2/2 on $mux $flatten\dut.$procmux$3956.
dead port 2/2 on $mux $flatten\dut.$procmux$3962.
dead port 2/2 on $mux $flatten\dut.$procmux$3968.
dead port 2/2 on $mux $flatten\dut.$procmux$3974.
dead port 2/2 on $mux $flatten\dut.$procmux$3980.
dead port 2/2 on $mux $flatten\dut.$procmux$3986.
dead port 2/2 on $mux $flatten\dut.$procmux$4016.
dead port 2/2 on $mux $flatten\dut.$procmux$4028.
dead port 2/2 on $mux $flatten\dut.$procmux$4064.
dead port 2/2 on $mux $flatten\dut.$procmux$4100.
dead port 2/2 on $mux $flatten\dut.$procmux$4136.
dead port 2/2 on $mux $flatten\dut.$procmux$4172.
dead port 2/2 on $mux $flatten\dut.$procmux$4208.
dead port 2/2 on $mux $flatten\dut.$procmux$4244.
dead port 2/2 on $mux $flatten\dut.$procmux$4280.
dead port 2/2 on $mux $flatten\dut.$procmux$4313.
dead port 2/2 on $mux $flatten\dut.$procmux$4319.
dead port 2/2 on $mux $flatten\dut.$procmux$4325.
dead port 2/2 on $mux $flatten\dut.$procmux$4331.
dead port 2/2 on $mux $flatten\dut.$procmux$4337.
dead port 2/2 on $mux $flatten\dut.$procmux$4343.
dead port 2/2 on $mux $flatten\dut.$procmux$4349.
dead port 2/2 on $mux $flatten\dut.$procmux$4379.
dead port 2/2 on $mux $flatten\dut.$procmux$4391.
dead port 2/2 on $mux $flatten\dut.$procmux$4427.
dead port 2/2 on $mux $flatten\dut.$procmux$4463.
dead port 2/2 on $mux $flatten\dut.$procmux$4499.
dead port 2/2 on $mux $flatten\dut.$procmux$4535.
dead port 2/2 on $mux $flatten\dut.$procmux$4571.
dead port 2/2 on $mux $flatten\dut.$procmux$4607.
dead port 2/2 on $mux $flatten\dut.$procmux$4643.
dead port 2/2 on $mux $flatten\dut.$procmux$4676.
dead port 2/2 on $mux $flatten\dut.$procmux$4682.
dead port 2/2 on $mux $flatten\dut.$procmux$4688.
dead port 2/2 on $mux $flatten\dut.$procmux$4694.
dead port 2/2 on $mux $flatten\dut.$procmux$4700.
dead port 2/2 on $mux $flatten\dut.$procmux$4706.
dead port 2/2 on $mux $flatten\dut.$procmux$4712.
dead port 2/2 on $mux $flatten\dut.$procmux$4742.
dead port 2/2 on $mux $flatten\dut.$procmux$4754.
dead port 2/2 on $mux $flatten\dut.$procmux$4790.
dead port 2/2 on $mux $flatten\dut.$procmux$4826.
dead port 2/2 on $mux $flatten\dut.$procmux$4862.
dead port 2/2 on $mux $flatten\dut.$procmux$4898.
dead port 2/2 on $mux $flatten\dut.$procmux$4934.
dead port 2/2 on $mux $flatten\dut.$procmux$4970.
dead port 2/2 on $mux $flatten\dut.$procmux$5006.
dead port 2/2 on $mux $flatten\dut.$procmux$5039.
dead port 2/2 on $mux $flatten\dut.$procmux$5045.
dead port 2/2 on $mux $flatten\dut.$procmux$5051.
dead port 2/2 on $mux $flatten\dut.$procmux$5057.
dead port 2/2 on $mux $flatten\dut.$procmux$5063.
dead port 2/2 on $mux $flatten\dut.$procmux$5069.
dead port 2/2 on $mux $flatten\dut.$procmux$5075.
dead port 2/2 on $mux $flatten\dut.$procmux$5104.
dead port 2/2 on $mux $flatten\dut.$procmux$5116.
dead port 2/2 on $mux $flatten\dut.$procmux$5152.
dead port 2/2 on $mux $flatten\dut.$procmux$5188.
dead port 2/2 on $mux $flatten\dut.$procmux$5224.
dead port 2/2 on $mux $flatten\dut.$procmux$5260.
dead port 2/2 on $mux $flatten\dut.$procmux$5296.
dead port 2/2 on $mux $flatten\dut.$procmux$5332.
dead port 2/2 on $mux $flatten\dut.$procmux$5368.
Removed 128 multiplexer ports.
<suppressed ~2000 debug messages>
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2282:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] $flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_EN[63:0]$2159 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2293:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] $flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_EN[63:0]$2147 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2304:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] $flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_EN[63:0]$2135 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2315:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] $flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_EN[63:0]$2123 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2326:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_EN[63:0]$2111 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2337:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_EN[63:0]$2099 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2348:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_EN[63:0]$2087 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$2359:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_EN[63:0]$2075 [0] }
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 8 changes.
4.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1807 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 654 unused wires.
<suppressed ~1 debug messages>
4.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1552 debug messages>
4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1807 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
4.13. Executing FSM pass (extract and optimize FSM).
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking harness_nms_activation_banked.dut.ack_stage1 as FSM state register:
Users of register don't seem to benefit from recoding.
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.14. Executing OPT pass (performing simple optimizations).
4.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1807 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1552 debug messages>
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1807 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$5394 ($dff) from module harness_nms_activation_banked (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:26$447_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
Adding SRST signal on $procdff$5396 ($dff) from module harness_nms_activation_banked (D = $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:56$457_Y, Q = \chk, rval = 8'00000000).
Adding SRST signal on $flatten\dut.$procdff$5450 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2466_Y, Q = \dut.rr_ptr[4], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5478 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2062_Y, Q = \dut.rr_ptr[4]).
Adding SRST signal on $flatten\dut.$procdff$5449 ($dff) from module harness_nms_activation_banked (D = \lfsr [14:12], Q = \dut.slot_bank_stage1[3], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5448 ($dff) from module harness_nms_activation_banked (D = \lfsr [10:8], Q = \dut.slot_bank_stage1[2], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5447 ($dff) from module harness_nms_activation_banked (D = \lfsr [6:4], Q = \dut.slot_bank_stage1[1], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5446 ($dff) from module harness_nms_activation_banked (D = \lfsr [2:0], Q = \dut.slot_bank_stage1[0], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5445 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[3] [3], Q = \dut.bank_rd_addr_stage1[3], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5444 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[2] [3], Q = \dut.bank_rd_addr_stage1[2], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5443 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[1] [3], Q = \dut.bank_rd_addr_stage1[1], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5442 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[0] [3], Q = \dut.bank_rd_addr_stage1[0], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5441 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[3], Q = \dut.bank_rd_en_stage1[3], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5440 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[2], Q = \dut.bank_rd_en_stage1[2], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5439 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[1], Q = \dut.bank_rd_en_stage1[1], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5438 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[0], Q = \dut.bank_rd_en_stage1[0], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5437 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2471_Y, Q = \dut.rr_ptr[3], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5492 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2060_Y, Q = \dut.rr_ptr[3]).
Adding SRST signal on $flatten\dut.$procdff$5436 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2476_Y, Q = \dut.rr_ptr[2], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5494 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2058_Y, Q = \dut.rr_ptr[2]).
Adding SRST signal on $flatten\dut.$procdff$5435 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2481_Y, Q = \dut.rr_ptr[1], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5496 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2056_Y, Q = \dut.rr_ptr[1]).
Adding SRST signal on $flatten\dut.$procdff$5434 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2486_Y, Q = \dut.rr_ptr[0], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5498 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2054_Y, Q = \dut.rr_ptr[0]).
Adding SRST signal on $flatten\dut.$procdff$5433 ($dff) from module harness_nms_activation_banked (D = \dut.ack_comb, Q = \dut.ack_stage1, rval = 8'00000000).
Adding SRST signal on $flatten\dut.$procdff$5432 ($dff) from module harness_nms_activation_banked (D = \dut.ack_stage1, Q = \dut.ack, rval = 8'00000000).
Adding EN signal on $flatten\dut.$procdff$5426 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2080_DATA, Q = \dut.GEN_BANK[0].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5422 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2092_DATA, Q = \dut.GEN_BANK[1].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5418 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2104_DATA, Q = \dut.GEN_BANK[2].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5414 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2116_DATA, Q = \dut.GEN_BANK[3].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5410 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2128_DATA, Q = \dut.GEN_BANK[4].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5406 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2140_DATA, Q = \dut.GEN_BANK[5].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5402 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2152_DATA, Q = \dut.GEN_BANK[6].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$5398 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$2164_DATA, Q = \dut.GEN_BANK[7].rd_data_r).
Adding SRST signal on $flatten\dut.$procdff$5457 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[7], Q = \dut.bank_rd_en_stage1[7], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5458 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[4] [3], Q = \dut.bank_rd_addr_stage1[4], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5459 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[5] [3], Q = \dut.bank_rd_addr_stage1[5], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5456 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[6], Q = \dut.bank_rd_en_stage1[6], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5460 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[6] [3], Q = \dut.bank_rd_addr_stage1[6], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5461 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[7] [3], Q = \dut.bank_rd_addr_stage1[7], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5455 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[5], Q = \dut.bank_rd_en_stage1[5], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5454 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[4], Q = \dut.bank_rd_en_stage1[4], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$5462 ($dff) from module harness_nms_activation_banked (D = \lfsr [18:16], Q = \dut.slot_bank_stage1[4], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5463 ($dff) from module harness_nms_activation_banked (D = \lfsr [22:20], Q = \dut.slot_bank_stage1[5], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5453 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2451_Y, Q = \dut.rr_ptr[7], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5520 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2068_Y, Q = \dut.rr_ptr[7]).
Adding SRST signal on $flatten\dut.$procdff$5464 ($dff) from module harness_nms_activation_banked (D = \lfsr [26:24], Q = \dut.slot_bank_stage1[6], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5465 ($dff) from module harness_nms_activation_banked (D = \lfsr [30:28], Q = \dut.slot_bank_stage1[7], rval = 3'000).
Adding SRST signal on $flatten\dut.$procdff$5452 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2456_Y, Q = \dut.rr_ptr[6], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5524 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2066_Y, Q = \dut.rr_ptr[6]).
Adding SRST signal on $flatten\dut.$procdff$5451 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$2461_Y, Q = \dut.rr_ptr[5], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$5526 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2064_Y, Q = \dut.rr_ptr[5]).
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 51 unused cells and 51 unused wires.
<suppressed ~52 debug messages>
4.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1466 debug messages>
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1757 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
4.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5467 (dut.GEN_BANK[6].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5466 (dut.GEN_BANK[7].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5473 (dut.GEN_BANK[0].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5472 (dut.GEN_BANK[1].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5471 (dut.GEN_BANK[2].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5468 (dut.GEN_BANK[5].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5469 (dut.GEN_BANK[4].mem).
Removed top 31 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$5470 (dut.GEN_BANK[3].mem).
Removed top 7 bits (of 8) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5501 ($sdff).
Removed top 7 bits (of 8) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5500 ($sdff).
Removed top 7 bits (of 8) from port B of cell harness_nms_activation_banked.$xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:54$449 ($xor).
Removed top 24 bits (of 32) from mux cell harness_nms_activation_banked.$procmux$2198 ($mux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5366_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5365_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5364_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5330_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5329_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5328_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5294_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5293_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5292_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5258_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5257_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5256_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5222_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5221_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5220_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5186_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5185_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5184_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5150_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5149_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5148_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5114_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5113_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5112_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5004_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5003_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$5002_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4968_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4967_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4966_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4932_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4931_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4930_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4896_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4895_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4894_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4860_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4859_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4858_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4824_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4823_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4822_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4788_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4787_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4786_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4752_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4751_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4750_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4641_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4640_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4639_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4605_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4604_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4603_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4569_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4568_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4567_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4533_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4532_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4531_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4497_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4496_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4495_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4461_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4460_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4459_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4425_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4424_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4423_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4389_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4388_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4387_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4278_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4277_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4276_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4242_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4241_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4240_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4206_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4205_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4204_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4170_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4169_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4168_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4134_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4133_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4132_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4098_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4097_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4096_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4062_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4061_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4060_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4026_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4025_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$4024_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3915_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3914_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3913_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3879_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3878_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3877_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3843_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3842_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3841_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3807_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3806_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3805_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3771_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3770_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3769_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3735_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3734_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3733_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3699_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3698_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3697_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3663_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3662_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3661_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3552_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3551_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3550_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3516_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3515_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3514_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3480_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3479_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3478_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3444_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3443_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3442_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3408_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3407_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3406_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3372_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3371_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3370_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3336_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3335_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3334_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3300_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3299_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3298_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3189_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3188_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3187_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3153_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3152_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3151_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3117_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3116_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3115_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3081_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3080_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3079_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3045_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3044_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3043_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3009_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3008_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3007_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2973_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2972_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2971_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2937_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2936_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2935_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2826_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2825_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2824_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2790_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2789_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2788_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2754_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2753_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2752_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2718_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2717_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2716_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2682_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2681_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2680_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2646_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2645_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2644_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2610_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2609_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2608_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2574_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2573_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2572_CMP0 ($eq).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2555 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2552 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2549 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2546 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2543 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2540 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2526 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2520 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2514 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2508 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2502 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2496 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$2492 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2365 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2354 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2343 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2332 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2321 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2310 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2299 ($mux).
Removed top 31 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2288 ($mux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2279_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2278_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2277_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2272 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2270_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2269_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2268_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2263 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2261_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2260_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2259_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2254 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2252_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2251_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2250_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2245 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2243_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2242_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2241_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2236 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2234_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2233_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2232_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2227 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2225_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2224_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2223_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2218 ($pmux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2216_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2215_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2214_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$2209 ($pmux).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:66$2094 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:66$2082 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$2012 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$2001 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1998 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1998 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1990 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1987 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1987 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1979 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1976 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1976 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1968 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1965 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1965 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1957 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1954 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1954 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1946 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1943 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1943 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1935 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1892 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1889 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1889 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1881 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1878 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1878 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1870 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1867 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1867 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1859 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1856 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1856 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1848 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1845 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1845 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1837 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1834 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1834 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1826 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1823 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1823 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1815 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1772 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1769 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1769 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1761 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1758 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1758 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1750 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1747 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1747 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1739 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1736 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1736 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1728 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1725 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1725 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1717 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1714 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1714 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1706 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1703 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1703 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1695 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1652 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1649 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1649 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1641 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1638 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1638 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1630 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1627 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1627 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1619 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1616 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1616 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1608 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1605 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1605 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1597 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1594 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1594 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1586 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1583 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1583 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1575 ($shiftx).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1568 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1564 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1560 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1556 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1552 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1548 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1544 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1540 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1533 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1532 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1529 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1529 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1522 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1521 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1518 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1518 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1511 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1510 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1507 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1507 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1500 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1499 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1496 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1496 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1489 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1488 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1485 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1485 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1478 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1477 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1474 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1474 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1467 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1466 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1463 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1463 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1456 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1455 ($shiftx).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1448 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1444 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1440 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1436 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1432 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1428 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1424 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1413 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1412 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1409 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1409 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1402 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1401 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1398 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1398 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1391 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1390 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1387 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1387 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1380 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1379 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1376 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1376 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1369 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1368 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1365 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1365 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1358 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1357 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1354 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1354 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1347 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1346 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1343 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1343 ($add).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1336 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1335 ($shiftx).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1328 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1324 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1320 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1316 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1312 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1308 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1304 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1293 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1292 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1282 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1281 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1271 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1270 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1260 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1259 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1256 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1256 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1249 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1248 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1245 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1245 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1238 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1237 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1234 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1234 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1227 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1226 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1223 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1223 ($add).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1216 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1215 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1172 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1161 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1150 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1139 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1136 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1136 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1128 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1125 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1125 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1117 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1114 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1114 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1106 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1103 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1103 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1095 ($shiftx).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5509 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5508 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5507 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5506 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5505 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5504 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5503 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$5502 ($dffe).
Removed top 29 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009_Y.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$819_ADDR[31:0]$2073.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$820_ADDR[31:0]$2085.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$821_ADDR[31:0]$2097.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$822_ADDR[31:0]$2109.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[4].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$823_ADDR[31:0]$2121.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[5].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$824_ADDR[31:0]$2133.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[6].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$825_ADDR[31:0]$2145.
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[7].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$826_ADDR[31:0]$2157.
Removed top 7 bits (of 8) from wire harness_nms_activation_banked.ack.
Removed top 56 bits (of 512) from wire harness_nms_activation_banked.rd_data_flat.
Removed top 24 bits (of 32) from wire harness_nms_activation_banked.$0\lfsr[31:0].
4.16. Executing PEEPOPT pass (run peephole optimizers).
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 323 unused cells and 348 unused wires.
<suppressed ~324 debug messages>
4.18. Executing SHARE pass (SAT-based resource sharing).
4.19. Executing TECHMAP pass (map to technology primitives).
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
4.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
4.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.22. Executing TECHMAP pass (map to technology primitives).
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
4.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.23. Executing TECHMAP pass (map to technology primitives).
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
4.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
4.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module harness_nms_activation_banked:
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1409 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1605 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1616 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1627 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1136 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1496 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1638 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1398 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1649 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1125 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1387 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1703 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1376 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1714 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1725 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1736 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1747 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1758 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1365 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1769 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1354 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1485 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1507 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1823 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1343 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1834 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1103 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1845 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1856 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1867 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1878 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1889 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1943 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1954 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1965 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1474 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1976 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1987 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1998 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1583 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1529 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1518 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2054 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2056 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1463 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2058 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1594 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2060 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2062 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2064 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2066 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2068 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1114 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1256 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1245 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1234 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1223 ($add).
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1223.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1234.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1245.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1256.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1114.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2068.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2066.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2064.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2062.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2060.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1594.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2058.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1463.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2056.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2054.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1518.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1529.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1583.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1998.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1987.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1976.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1474.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1965.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1954.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1943.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1889.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1878.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1867.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1856.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1845.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1103.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1834.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1343.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1823.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1507.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1485.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1354.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1769.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1365.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1758.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1747.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1736.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1725.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1714.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1376.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1703.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1387.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1125.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1649.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1398.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1638.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1496.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1136.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1627.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1616.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1605.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1409.
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1409: $auto$alumacc.cc:548:replace_alu$5541
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1605: $auto$alumacc.cc:548:replace_alu$5544
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147: $auto$alumacc.cc:548:replace_alu$5547
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1616: $auto$alumacc.cc:548:replace_alu$5550
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1627: $auto$alumacc.cc:548:replace_alu$5553
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1136: $auto$alumacc.cc:548:replace_alu$5556
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1496: $auto$alumacc.cc:548:replace_alu$5559
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1638: $auto$alumacc.cc:548:replace_alu$5562
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1398: $auto$alumacc.cc:548:replace_alu$5565
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1649: $auto$alumacc.cc:548:replace_alu$5568
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1125: $auto$alumacc.cc:548:replace_alu$5571
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1387: $auto$alumacc.cc:548:replace_alu$5574
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1703: $auto$alumacc.cc:548:replace_alu$5577
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1376: $auto$alumacc.cc:548:replace_alu$5580
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1714: $auto$alumacc.cc:548:replace_alu$5583
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158: $auto$alumacc.cc:548:replace_alu$5586
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1725: $auto$alumacc.cc:548:replace_alu$5589
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1736: $auto$alumacc.cc:548:replace_alu$5592
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1747: $auto$alumacc.cc:548:replace_alu$5595
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1758: $auto$alumacc.cc:548:replace_alu$5598
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1365: $auto$alumacc.cc:548:replace_alu$5601
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1769: $auto$alumacc.cc:548:replace_alu$5604
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1354: $auto$alumacc.cc:548:replace_alu$5607
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1485: $auto$alumacc.cc:548:replace_alu$5610
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1507: $auto$alumacc.cc:548:replace_alu$5613
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1823: $auto$alumacc.cc:548:replace_alu$5616
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169: $auto$alumacc.cc:548:replace_alu$5619
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1343: $auto$alumacc.cc:548:replace_alu$5622
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1834: $auto$alumacc.cc:548:replace_alu$5625
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1103: $auto$alumacc.cc:548:replace_alu$5628
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1845: $auto$alumacc.cc:548:replace_alu$5631
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1856: $auto$alumacc.cc:548:replace_alu$5634
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1867: $auto$alumacc.cc:548:replace_alu$5637
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1878: $auto$alumacc.cc:548:replace_alu$5640
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1889: $auto$alumacc.cc:548:replace_alu$5643
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1943: $auto$alumacc.cc:548:replace_alu$5646
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1954: $auto$alumacc.cc:548:replace_alu$5649
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1965: $auto$alumacc.cc:548:replace_alu$5652
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1474: $auto$alumacc.cc:548:replace_alu$5655
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1976: $auto$alumacc.cc:548:replace_alu$5658
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1987: $auto$alumacc.cc:548:replace_alu$5661
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1998: $auto$alumacc.cc:548:replace_alu$5664
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$2009: $auto$alumacc.cc:548:replace_alu$5667
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1583: $auto$alumacc.cc:548:replace_alu$5670
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1529: $auto$alumacc.cc:548:replace_alu$5673
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1518: $auto$alumacc.cc:548:replace_alu$5676
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2054: $auto$alumacc.cc:548:replace_alu$5679
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2056: $auto$alumacc.cc:548:replace_alu$5682
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1463: $auto$alumacc.cc:548:replace_alu$5685
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2058: $auto$alumacc.cc:548:replace_alu$5688
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1594: $auto$alumacc.cc:548:replace_alu$5691
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2060: $auto$alumacc.cc:548:replace_alu$5694
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2062: $auto$alumacc.cc:548:replace_alu$5697
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2064: $auto$alumacc.cc:548:replace_alu$5700
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2066: $auto$alumacc.cc:548:replace_alu$5703
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$2068: $auto$alumacc.cc:548:replace_alu$5706
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289: $auto$alumacc.cc:548:replace_alu$5709
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1114: $auto$alumacc.cc:548:replace_alu$5712
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278: $auto$alumacc.cc:548:replace_alu$5715
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267: $auto$alumacc.cc:548:replace_alu$5718
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1256: $auto$alumacc.cc:548:replace_alu$5721
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1245: $auto$alumacc.cc:548:replace_alu$5724
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1234: $auto$alumacc.cc:548:replace_alu$5727
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1223: $auto$alumacc.cc:548:replace_alu$5730
created 64 $alu and 0 $macc cells.
4.25. Executing OPT pass (performing simple optimizations).
4.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1421 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~660 debug messages>
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1421 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
4.26. Executing MEMORY pass.
4.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing harness_nms_activation_banked.dut.GEN_BANK[0].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[1].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[2].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[3].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[4].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[5].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[6].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[7].mem write port 0.
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\dut.GEN_BANK[0].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[1].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_BANK[2].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[3].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_BANK[4].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[5].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_BANK[6].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[7].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 8 unused cells and 64 unused wires.
<suppressed ~9 debug messages>
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory harness_nms_activation_banked.dut.GEN_BANK[0].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[0].mem: $\dut.GEN_BANK[0].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[1].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[1].mem: $\dut.GEN_BANK[1].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[2].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[2].mem: $\dut.GEN_BANK[2].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[3].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[3].mem: $\dut.GEN_BANK[3].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[4].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[4].mem: $\dut.GEN_BANK[4].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[5].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[5].mem: $\dut.GEN_BANK[5].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[6].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[6].mem: $\dut.GEN_BANK[6].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[7].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[7].mem: $\dut.GEN_BANK[7].mem$rdreg[0]
<suppressed ~3604 debug messages>
4.29. Executing TECHMAP pass (map to technology primitives).
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
4.29.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~146 debug messages>
4.30. Executing OPT pass (performing simple optimizations).
4.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~560 debug messages>
4.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1508 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1507 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1506 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 80 unused cells and 1017 unused wires.
<suppressed ~81 debug messages>
4.30.5. Finished fast OPT passes.
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.32. Executing OPT pass (performing simple optimizations).
4.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1426 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~593 debug messages>
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1426 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.9. Finished fast OPT passes. (There is nothing left to do.)
4.33. Executing TECHMAP pass (map to technology primitives).
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
4.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$79fc7abbb3333dbd5736999d565fd903198fb1eb\_90_alu for cells of type $alu.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$constmap:495c8dc1812f09f0b6f9ecda08e517e7538e08fd$paramod$2cd5a0fc12c713b111b124c014c3805512a5d620\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $not.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
No more expansions possible.
<suppressed ~3393 debug messages>
4.34. Executing OPT pass (performing simple optimizations).
4.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~5181 debug messages>
4.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 14090 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 11302 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 10123 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 9515 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 9259 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 9051 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~15117 debug messages>
Removed a total of 5039 cells.
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 1361 unused cells and 7768 unused wires.
<suppressed ~1362 debug messages>
4.34.5. Finished fast OPT passes.
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
4.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 7690 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.38. Executing TECHMAP pass (map to technology primitives).
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.38.2. Continuing TECHMAP pass.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
No more expansions possible.
<suppressed ~245 debug messages>
4.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
4.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in harness_nms_activation_banked.
4.42. Executing ATTRMVCP pass (move or copy attributes).
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 777 unused wires.
<suppressed ~1 debug messages>
4.44. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.45. Executing TECHMAP pass (map to technology primitives).
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
4.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.46. Executing ABC9 pass.
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.3. Executing PROC pass (convert processes to netlists).
4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$35989'.
Cleaned up 1 empty switch.
4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.
4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.
4.46.3.4. Executing PROC_INIT pass (extract init attributes).
4.46.3.5. Executing PROC_ARST pass (detect async resets in processes).
4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_EN[3:0]$35996
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_DATA[3:0]$35995
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_ADDR[3:0]$35994
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$35989'.
4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35972_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35973_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35974_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35975_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35976_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35977_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35978_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35979_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35980_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35981_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35982_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35983_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35984_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35985_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35986_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$35987_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$35989'.
4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
created $dff cell `$procdff$36040' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
created $dff cell `$procdff$36041' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$35988_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
created $dff cell `$procdff$36042' with positive edge clock.
4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$36014'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$35990'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$35989'.
Cleaned up 1 empty switch.
4.46.4. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module harness_nms_activation_banked.
Found 0 SCCs.
4.46.5. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.6. Executing TECHMAP pass (map to technology primitives).
4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~167 debug messages>
4.46.7. Executing OPT pass (performing simple optimizations).
4.46.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.
4.46.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
4.46.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.8. Executing TECHMAP pass (map to technology primitives).
4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
4.46.8.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~19 debug messages>
4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.13. Executing TECHMAP pass (map to technology primitives).
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.13.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~171 debug messages>
4.46.14. Executing OPT pass (performing simple optimizations).
4.46.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.46.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.46.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.15. Executing AIGMAP pass (map logic to AIG).
4.46.16. Executing AIGMAP pass (map logic to AIG).
Module harness_nms_activation_banked: replaced 4310 cells with 20894 new cells, skipped 3396 cells.
replaced 3 cell types:
1038 $_MUX_
3092 $_OR_
180 $_XOR_
not replaced 6 cell types:
2400 $_AND_
811 $_NOT_
1 $scopeinfo
152 TRELLIS_FF
16 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
16 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 9146 AND gates and 24467 wires from module `harness_nms_activation_banked' to a netlist network with 226 inputs and 185 outputs.
4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
4.46.16.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 226/ 185 and = 8897 lev = 68 (5.44) mem = 0.11 MB box = 16 bb = 16
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 226/ 185 and = 11071 lev = 24 (2.94) mem = 0.14 MB ch = 958 box = 16 bb = 16
ABC: cst = 0 cls = 722 lit = 958 unused = 9681 proof = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 11071. Ch = 722. Total mem = 1.92 MB. Peak cut mem = 0.22 MB.
ABC: P: Del = 4625.00. Ar = 7460.0. Edge = 9331. Cut = 165820. T = 0.02 sec
ABC: P: Del = 4541.00. Ar = 7548.0. Edge = 9417. Cut = 163591. T = 0.02 sec
ABC: P: Del = 4541.00. Ar = 5446.0. Edge = 11264. Cut = 280459. T = 0.03 sec
ABC: F: Del = 4541.00. Ar = 3839.0. Edge = 10106. Cut = 209043. T = 0.03 sec
ABC: A: Del = 4541.00. Ar = 3499.0. Edge = 9155. Cut = 183771. T = 0.03 sec
ABC: A: Del = 4541.00. Ar = 3436.0. Edge = 9080. Cut = 184790. T = 0.03 sec
ABC: Total time = 0.16 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 226/ 185 and = 7694 lev = 27 (3.06) mem = 0.10 MB box = 16 bb = 16
ABC: Mapping (K=7) : lut = 2194 edge = 8629 lev = 9 (1.25) levB = 9 mem = 0.08 MB
ABC: LUT = 2194 : 2=224 10.2 % 3=378 17.2 % 4=1151 52.5 % 5=273 12.4 % 6=98 4.5 % 7=70 3.2 % Ave = 3.93
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.14 sec
ABC: + time
ABC: elapse: 1.42 seconds, total: 1.42 seconds
4.46.16.6. Executing AIGER frontend.
<suppressed ~10 debug messages>
Removed 10114 unused cells and 10658 unused wires.
4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 2194
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 16
ABC RESULTS: input signals: 41
ABC RESULTS: output signals: 72
<suppressed ~822 debug messages>
Removing temp directory.
4.46.17. Executing TECHMAP pass (map to technology primitives).
4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
4.46.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~39 debug messages>
Removed 36 unused cells and 27376 unused wires.
4.47. Executing TECHMAP pass (map to technology primitives).
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
4.47.2. Continuing TECHMAP pass.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750$lut for cells of type $lut.
Using template $paramod$c93083768903e88c37e0c9b82fead370b0886961$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af$lut for cells of type $lut.
Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e$lut for cells of type $lut.
Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$872d4f64a8c919c890337a35e4fe527bfa1325d3$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84$lut for cells of type $lut.
Using template $paramod$371ae93dd2f5924fee28656f59a2d7d2757eda91$lut for cells of type $lut.
Using template $paramod$5056416678496c44972b5f2c251435b63cdafeb4$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
Using template $paramod$e496e1ebaf8968b0448781d0c7b4fab8e5e7c961$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
Using template $paramod$c6386220a7a54c5098c7b9e80f8ba5bc42999efa$lut for cells of type $lut.
Using template $paramod$4996c3dc15d58e10bd885795bdf7c36745efdae8$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010101 for cells of type $lut.
Using template $paramod$393c369193de8779f50882599bd9625c7fe51238$lut for cells of type $lut.
Using template $paramod$d88c2f04827408967f26993d407fa8030e6e129f$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29$lut for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut.
Using template $paramod$15dcd80d72f8269cefeea2cbc86007d3271f025d$lut for cells of type $lut.
Using template $paramod$eb0b7b796486150424969057dee3cec0b7ea7771$lut for cells of type $lut.
Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c$lut for cells of type $lut.
Using template $paramod$7f937f9b61bf542e3f85320ab27ebb3043b4337a$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd$lut for cells of type $lut.
Using template $paramod$bd69e3c0d2d96276ad348367b782c97ebfbc49e8$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96$lut for cells of type $lut.
Using template $paramod$eb5e2fc57187e0cdc01c04f3719e84b2310b0a32$lut for cells of type $lut.
Using template $paramod$fb48883a050c9ce018ba42b144cc00f32b90e2c2$lut for cells of type $lut.
Using template $paramod$5049287853c17eda46e2be1c56e1d80cb563e118$lut for cells of type $lut.
Using template $paramod$81c2e473ba00a9cfa3dfe1d42c1fabf3cd269a21$lut for cells of type $lut.
Using template $paramod$93662c54b3caa8cbc9725ac5d60f3b40260150e5$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366$lut for cells of type $lut.
Using template $paramod$c1b7bf788f3e0e8c4f0137b183111694004ae089$lut for cells of type $lut.
Using template $paramod$f92e79ccd6f3d23a5916839d2ca07e4c590942af$lut for cells of type $lut.
Using template $paramod$c145f84e6b9aba2d7bbf6cd4a827e636b5fa3ae0$lut for cells of type $lut.
Using template $paramod$3efe3d4e03a4e30d9c6f8c028f6dc0ddc0d80638$lut for cells of type $lut.
Using template $paramod$05c6ed00b657e441f9facdd1b8577436ff8f81a1$lut for cells of type $lut.
Using template $paramod$86c1e81fa96a31432421f1d3d44686ba5b7d9473$lut for cells of type $lut.
Using template $paramod$410424105860162e69bfdb274ff8735ad79733c7$lut for cells of type $lut.
Using template $paramod$9a9b1eb93cf8cae3712704918bfa4b29d6a116b2$lut for cells of type $lut.
Using template $paramod$ad0f864af8653f28a2000203a1cf45c22a6b8166$lut for cells of type $lut.
Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304$lut for cells of type $lut.
Using template $paramod$6786213342169f46cbca44284df298da11653c08$lut for cells of type $lut.
Using template $paramod$777ef192fe7e1e9d180e8daa5e2b4e22cc8d4acd$lut for cells of type $lut.
Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c$lut for cells of type $lut.
Using template $paramod$3f2774da7ec4a6417559f6fb965247f349599d51$lut for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2$lut for cells of type $lut.
Using template $paramod$d8a851edf04260eb28aaaf93d5a60542d6e72d32$lut for cells of type $lut.
Using template $paramod$f8472f50a89e594a6082fb36c827682329e70a37$lut for cells of type $lut.
Using template $paramod$dc41a956c02896bb314b3585a99557a5e53688a4$lut for cells of type $lut.
Using template $paramod$ecf13843486484b63c7ea53cfda07e0bd34af45c$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad$lut for cells of type $lut.
Using template $paramod$5f196c11001392886d4660a84e4fd427ce5ae24d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e$lut for cells of type $lut.
Using template $paramod$ca640d1ef8cc3eef346f8a331d338bd4862c2ef5$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$e6fb771c4c8566932ef9751124ee6380e06f2455$lut for cells of type $lut.
Using template $paramod$d4fb1bc26b7b9ce11784c9cbfe7e1ae6afd58caa$lut for cells of type $lut.
Using template $paramod$de168c593feeac3576dfd2fe793531bfe1628024$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc$lut for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467$lut for cells of type $lut.
Using template $paramod$4c019fad677a6751d10c7683062ad8483ed51b71$lut for cells of type $lut.
Using template $paramod$6a0faddbb1877e236e8eb8130711942937277f4e$lut for cells of type $lut.
Using template $paramod$2a79b2bc3c99ee453ad8fe8c4c8e635ce29e67d7$lut for cells of type $lut.
Using template $paramod$1d10e522f8c4a4fecd6a8bab27ce601329aaae96$lut for cells of type $lut.
Using template $paramod$b4d73d1fe7f7c338e989937e344676fd7b3b133a$lut for cells of type $lut.
Using template $paramod$fdb9c5353b9b58fdf8cebd992b2560b321e64c4e$lut for cells of type $lut.
Using template $paramod$a60fb5e58f32fa52e99570cc95b8fd2921527aca$lut for cells of type $lut.
Using template $paramod$1041dd328ce0ca0e1e75deee2a0c853ad892eef4$lut for cells of type $lut.
Using template $paramod$368ece0cbe0dd8813956f5c0ea41432c34a980c2$lut for cells of type $lut.
Using template $paramod$defe54705e960f63458bcc1bf9cceae5034e7dc8$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$4dfa26e736f9800d377c839a343d7cf750e306a6$lut for cells of type $lut.
Using template $paramod$946e4ba6cc6d5f643745e6b56089375901ce6d2c$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut.
Using template $paramod$c0a4d9417755c1bd5ec9a311325000b8535d91ad$lut for cells of type $lut.
Using template $paramod$8b07c408baa3a0babbe199b3e93b1640d36fa5e4$lut for cells of type $lut.
Using template $paramod$ab2d8c2b9d8aa7f76721394c261b87284f763090$lut for cells of type $lut.
Using template $paramod$e89af2b13f2a3894e76d77f57e00c9c09e3a1911$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514$lut for cells of type $lut.
Using template $paramod$f2eb4f343990b5a009173458078c61c11685441c$lut for cells of type $lut.
Using template $paramod$68caabde22227f072d769456c5f371ee3d257246$lut for cells of type $lut.
Using template $paramod$c9ac2be49a400c6b773aa5b957bf963d13cda23b$lut for cells of type $lut.
Using template $paramod$2bde02b8b9e7d4618088fbf4dd7d45ed8df60d20$lut for cells of type $lut.
Using template $paramod$c0e0b8c1907b2ff3f9a831d5a742da8810adb963$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb$lut for cells of type $lut.
Using template $paramod$cfcc41897735ad5ea14a1f12fcee73dcacb20e30$lut for cells of type $lut.
Using template $paramod$c75ca06703b8990f8b5e09e87c914b4537abb14d$lut for cells of type $lut.
Using template $paramod$150ef1cc573a226e51e94d04ec24cdad3a5c60a3$lut for cells of type $lut.
Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01$lut for cells of type $lut.
Using template $paramod$97981d5c49e651b366b0c1beb0e80bd1919261b5$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut.
Using template $paramod$d909494d67d7075f17a422f7cb5526f6d6564ea6$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut.
Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab$lut for cells of type $lut.
Using template $paramod$15b1be980a14edac79713e171a9494e1b4bd5060$lut for cells of type $lut.
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809$lut for cells of type $lut.
Using template $paramod$38d839833f368ba2ca5a9cdf744ab7952572a68d$lut for cells of type $lut.
Using template $paramod$9126804ae7ac07423eb9d14c035f33dd3c39c83c$lut for cells of type $lut.
Using template $paramod$262c6fdeee01e2b71f9c0e67a44c707f1204ae2c$lut for cells of type $lut.
Using template $paramod$82902039ae762e81544902874fbfd1d7aca0233a$lut for cells of type $lut.
Using template $paramod$e942ff15257dd44eb70ae034d1b665e0116c7a3e$lut for cells of type $lut.
Using template $paramod$c9bd248755dabb658ae9570b4045d7344392d6c9$lut for cells of type $lut.
Using template $paramod$70e1b1098f05f8bc9abbd13525eb0341773fcc8b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$9a3e28b389c1f3cb6cf0807228c461506fb829f5$lut for cells of type $lut.
Using template $paramod$c34bd785a67c473fb63ea0177b5ef15fccf52556$lut for cells of type $lut.
Using template $paramod$dd351332a44263d6274369352ca1bd334f12f053$lut for cells of type $lut.
Using template $paramod$4fade65feaf5a62ce548a38c8a88a2dc2804eecb$lut for cells of type $lut.
Using template $paramod$01d1badebdb17f5d737fb2d89d208cb7f0ffab68$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$756861dd4dfe0a5b9de37af2241117b1958e2ffe$lut for cells of type $lut.
Using template $paramod$1e3442e8318d940ec2225a309a98e0c6bd2f8ca2$lut for cells of type $lut.
Using template $paramod$779ce1856232fd2857259a50e6832c67ad66128e$lut for cells of type $lut.
Using template $paramod$e8cfa82fe9fafda665970c4013f959dbd624c098$lut for cells of type $lut.
Using template $paramod$986810eff0e4e3827907e3e711ed31cc3ba5076c$lut for cells of type $lut.
Using template $paramod$23fd246d232de6bfd916dcbb1d02a62d3d768e8d$lut for cells of type $lut.
Using template $paramod$f60ec2feaf11637f36e7a1534471d12c2d3b8634$lut for cells of type $lut.
Using template $paramod$9ab6f26069edb5825a344e47a0d082450ffaf887$lut for cells of type $lut.
Using template $paramod$a1b7ff19b8bbd60382b0187854e665ed43ad5602$lut for cells of type $lut.
Using template $paramod$cd4457b32a286bcb33e3ec0631650673cdc5b177$lut for cells of type $lut.
Using template $paramod$68a1f10a25b7ac78db680b73332f69b4bb2322c6$lut for cells of type $lut.
Using template $paramod$b8de0526e9d13be7b2595b36edbf19874b70dc66$lut for cells of type $lut.
Using template $paramod$cae86cc3087f0ba749b437cbf8d16c8515959860$lut for cells of type $lut.
Using template $paramod$5110a6c960827f09ca754c042b63f78bd5f84523$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut.
Using template $paramod$9cc232f6244bf953845762b1862297b745e2e166$lut for cells of type $lut.
Using template $paramod$e6a85936eaa7a3305cad23523bc966430b038ac6$lut for cells of type $lut.
Using template $paramod$b86ca946e71d68c1b53608bf6d3eb74af58f4dc0$lut for cells of type $lut.
Using template $paramod$84b1eac3ac1c630612c9cfeb838f550ff1ff45f4$lut for cells of type $lut.
Using template $paramod$c6364c1c44c01bd533fa2efe3a700455891e44b1$lut for cells of type $lut.
Using template $paramod$5e553af6bf68b0641d6aa5d9b0e83e92a8707e56$lut for cells of type $lut.
Using template $paramod$99e243cf2610d96af12f5e281daca78176769214$lut for cells of type $lut.
Using template $paramod$f2d22947d144afc97fbfe77dd7b67614b454e6ce$lut for cells of type $lut.
Using template $paramod$9bfbc7c935f46f1f5aaefccb8cf88f5023ffd847$lut for cells of type $lut.
Using template $paramod$23db9926fe633e30e825fd101a17a28c1f6679f4$lut for cells of type $lut.
Using template $paramod$a05b26eeb60c76e717fa898c8cc7ef1306ce2abc$lut for cells of type $lut.
Using template $paramod$edbcfb03bc1e5a8d769533f985a4886cf0c49a2f$lut for cells of type $lut.
Using template $paramod$1421c0f79ead75e62e4cbb8576d623facb48d5b4$lut for cells of type $lut.
Using template $paramod$73a5df16621ef784522b67337a59ea39f6f28f4f$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db$lut for cells of type $lut.
Using template $paramod$8c0aa4283e004d7e549a2fa42300002224408629$lut for cells of type $lut.
Using template $paramod$4e5c78db886e260fae81580d9aff04819947b95f$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52$lut for cells of type $lut.
Using template $paramod$e9e030bf2250db03d2279259a20a04f612f0d195$lut for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5$lut for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75$lut for cells of type $lut.
Using template $paramod$79fcd6877631f8ad66bc8725d8a5419347717758$lut for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e$lut for cells of type $lut.
Using template $paramod$5920229cea70399b1e6162a0a0a8f5df7373dbe6$lut for cells of type $lut.
Using template $paramod$5cdd6c45be1730619480254670476c4ed2df25cf$lut for cells of type $lut.
Using template $paramod$152933c3c10a0b6565167a91c2a9ea06871b8166$lut for cells of type $lut.
Using template $paramod$b4178000258689c4950cbc4ecbfd97b7475eee0f$lut for cells of type $lut.
Using template $paramod$b19a11e0d6fb2d71008d22ffdd590c6f8ba7f68a$lut for cells of type $lut.
Using template $paramod$9ab494594f178f1b2722725c1a755ee5c002129c$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
Using template $paramod$0260ba258d9e1a608f5e349a51c65fb9e84b9283$lut for cells of type $lut.
Using template $paramod$03093da30565309b0719c81da32adb1e5bf43e63$lut for cells of type $lut.
Using template $paramod$dc976353173719d4dd8d5c043661f2d4d2730689$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
Using template $paramod$ce126191d7aa1cb76b0f1dcd34438902325b1ba8$lut for cells of type $lut.
Using template $paramod$28b2ee02b191cdb9286b1ca35409cd7d1b61dafa$lut for cells of type $lut.
Using template $paramod$60fe94377db7d34bbbbf096cb3e1a7a3b72a38a6$lut for cells of type $lut.
Using template $paramod$b7792e1962fb8b65865c48433cacb9941e24b485$lut for cells of type $lut.
Using template $paramod$ba61979b396255b0f5491a4d4df5fa46e2c9bd3d$lut for cells of type $lut.
Using template $paramod$2fbd76808776c82e8d8f3d85d59fc99b3a9444a3$lut for cells of type $lut.
Using template $paramod$509134bc2cb2a13bd358205e16f70c14c8dfafaa$lut for cells of type $lut.
Using template $paramod$3767a4ace77a91866b441b12ea8b11c60d44781d$lut for cells of type $lut.
Using template $paramod$a2241d5ec0a8f3e22a06d121139c830891d880d6$lut for cells of type $lut.
Using template $paramod$cb2306e60f582a83aced5cf010278719e09345bd$lut for cells of type $lut.
Using template $paramod$15a361e9afe53d073e5f05a5a1fc7d88e6644bc6$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2$lut for cells of type $lut.
Using template $paramod$0623e17b239149821fdbe2294e3bbba8e938900a$lut for cells of type $lut.
Using template $paramod$172562782b29adf13eed00aa5949ba18b75fb966$lut for cells of type $lut.
Using template $paramod$b7ffccfabd6e7ca08ce1262cc41379da0e08bf9a$lut for cells of type $lut.
Using template $paramod$0e97d695a2176bfc635c448897fed5905cbc93c0$lut for cells of type $lut.
Using template $paramod$14f60a5a22ce5ab3f64357bb1bd967b13ccdbe9a$lut for cells of type $lut.
Using template $paramod$9dbe36982f6b8ca20db05cfcd5650178f13179f3$lut for cells of type $lut.
Using template $paramod$a4df9cb6a33186f138fb7b84c3b0e638dff0944d$lut for cells of type $lut.
Using template $paramod$8c8f9e1da2d595be942f9e71fb135c51a9423f7d$lut for cells of type $lut.
Using template $paramod$c7a24a1202dc4fa964ac6d653b9acffcd805369e$lut for cells of type $lut.
Using template $paramod$5c8c9d879bd9421408756789efcd573655c3b5ba$lut for cells of type $lut.
Using template $paramod$c5fbf6d12605a60ab74ffbf854220e5fa1852037$lut for cells of type $lut.
Using template $paramod$0168072450226b493f7201bdb9fc41a6a0b6f539$lut for cells of type $lut.
Using template $paramod$360c58d28d9464261c8da0db5ef6cb9debcc6a8e$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b$lut for cells of type $lut.
Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d$lut for cells of type $lut.
Using template $paramod$b765092b315cb697876ab84d59246ca9aafc4635$lut for cells of type $lut.
Using template $paramod$57114a15f3c3846c2edf0b8a142dbb0d138e6e26$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc$lut for cells of type $lut.
Using template $paramod$0d32e36bab4cd3e24dbcc94204821aa7f75d106e$lut for cells of type $lut.
Using template $paramod$1df16ebc226f748eb8e9646622bda1544caf2a3b$lut for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d$lut for cells of type $lut.
Using template $paramod$2c7d7b6f5902306a70af16781d1df4f7c6bd2411$lut for cells of type $lut.
Using template $paramod$0cd6624728e68e87f93b3d27aef965436c9cc353$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e$lut for cells of type $lut.
Using template $paramod$4deee9e01367a494a2b37b160350b076cf464fe0$lut for cells of type $lut.
Using template $paramod$bf5c1393b4a26417eca152b76f61c07bbc32a438$lut for cells of type $lut.
Using template $paramod$da9695c03a50f5540c039ab45043906f37a2a530$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec$lut for cells of type $lut.
Using template $paramod$6a1c4b02378242d4c97bf4b7a7f98bc914e5a900$lut for cells of type $lut.
Using template $paramod$8ec169e137149e2e58a8dd6016da6949f4d6abd5$lut for cells of type $lut.
Using template $paramod$be0d52b4adde38396aa8d181484c99080ee57661$lut for cells of type $lut.
Using template $paramod$1c0f08947fce17be9eefa865d254e450a07b477c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$7bba97d58a35bcb4c546bf5700f2b674231eb5bd$lut for cells of type $lut.
Using template $paramod$f940b3836b816258cf0bf1afa7ea5d3b0e7a8025$lut for cells of type $lut.
Using template $paramod$33cfa21841c36c45df947255efb43df2a09980c9$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut.
Using template $paramod$3d61124bf13b14b11480a8c908c1f3ff98c9649d$lut for cells of type $lut.
Using template $paramod$2f8ced2b1543439c77f221e948c1c21655a402b3$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd$lut for cells of type $lut.
Using template $paramod$652a7ee7ae8301ca83361e399d3003826bdef5e3$lut for cells of type $lut.
Using template $paramod$429498effd216097e7acd1ad9fe5e0149262a3ee$lut for cells of type $lut.
Using template $paramod$4f79d472867f62e55dd736f8b9b25cd05a56667d$lut for cells of type $lut.
Using template $paramod$c5fc75a3c76ca4b62ba5ce67ff8eaffd884835f1$lut for cells of type $lut.
Using template $paramod$0fdb80a3c62468b55f2b85193981ad60a14873e7$lut for cells of type $lut.
Using template $paramod$27b6dc3c2e8f5c52ce4a8fc0538d7a93f1883b9f$lut for cells of type $lut.
Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7$lut for cells of type $lut.
Using template $paramod$7d8050379a0adaa7ca91e969f58f7281d288ce41$lut for cells of type $lut.
Using template $paramod$99ba7e80fc5077f9a2c5f62d113d8e3ac97ab48f$lut for cells of type $lut.
Using template $paramod$579177068df873e2977f6cc47ce1ca65e4cb10ab$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc$lut for cells of type $lut.
Using template $paramod$8540495becc5977ef0ebaa7b0aa27d3683d9ed0c$lut for cells of type $lut.
Using template $paramod$3a76ae1ac16567d84de882ad5b89dd62763f5d7e$lut for cells of type $lut.
Using template $paramod$c22a370b0ac036786339c000f458c7a0a658e959$lut for cells of type $lut.
Using template $paramod$9f192dbf58cb79f646ab5325f4e378c31285241d$lut for cells of type $lut.
Using template $paramod$176ad6c58abf520685885c03f7bda4993e550d22$lut for cells of type $lut.
Using template $paramod$f096cea9ae08fe9c72114c100344ebc33a6a5988$lut for cells of type $lut.
Using template $paramod$f81ecf3eb88491df8fecf1e071b57debc429282a$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e$lut for cells of type $lut.
Using template $paramod$c03dff893ffcf5747c5915b3f34923aae22d05a9$lut for cells of type $lut.
Using template $paramod$660a72f63d46a844bb0ddab189b65027c878fc6b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7$lut for cells of type $lut.
Using template $paramod$876c83b10cfb4d4ddef346f34fcd085356f74521$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$68992113512b543ae4667d4058fd6fbccad99a3a$lut for cells of type $lut.
Using template $paramod$f6e6717391ec9a1cbe38997b8a3b6c11e8abbc85$lut for cells of type $lut.
Using template $paramod$974f15c03a0d33c52f33b783b38f5fbc8d673fc6$lut for cells of type $lut.
Using template $paramod$66f9c58c759edf7b58a57f136aceed50d0680ddb$lut for cells of type $lut.
Using template $paramod$fef639961010220782cb5dc187da065d88f69127$lut for cells of type $lut.
Using template $paramod$80ac0ade7cb4ac4daa001fa5570286e6b33868f7$lut for cells of type $lut.
Using template $paramod$8458a2af2bec38d65e757a16c16ceecd7b073edc$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$f0cb2d24aa08bb88b51518cb6e0a8d1253ca294f$lut for cells of type $lut.
Using template $paramod$53d1295e92eea38a512b9ce693445c7190afdb5d$lut for cells of type $lut.
Using template $paramod$e00d03686849cf5e50e9f0c13f0f78958ff5e7ae$lut for cells of type $lut.
Using template $paramod$80d119b846de9eb67cf123b4d4c105633f15e6f8$lut for cells of type $lut.
Using template $paramod$bc051162dfb23caab98d73c4ec086fe9a67895f2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$1d411fd062123bc39f2e308cfceb6b39df8f57b9$lut for cells of type $lut.
Using template $paramod$fb7f36ceefc7a45462dab9004ed5b2c039cbd880$lut for cells of type $lut.
Using template $paramod$0169eb4949898e841c25bb571c240875d67e3d25$lut for cells of type $lut.
Using template $paramod$b698dd2b885039c9e1d53e243fc4e0191632dfd9$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed$lut for cells of type $lut.
Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32$lut for cells of type $lut.
Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760$lut for cells of type $lut.
Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc$lut for cells of type $lut.
Using template $paramod$e035640c5400ebc6b1db9018dbf7e784b8617ead$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut.
Using template $paramod$343c340914da1bc1b087d2ab3971dc221716ccb1$lut for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$af6c031ac0fb107e7be9abc2ea21f49ba863ff94$lut for cells of type $lut.
Using template $paramod$1bf5ee4386820bff5f1538d75cd0acb8f4ee7bd0$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796$lut for cells of type $lut.
Using template $paramod$048d4aa2263b685fba6c6b0d38f6224df0dc3042$lut for cells of type $lut.
Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0$lut for cells of type $lut.
Using template $paramod$09fa89531d411d822576d2550b48621f24953723$lut for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc$lut for cells of type $lut.
Using template $paramod$0d7eb4de36f98a95eaced140c7c6af7fd6e81a58$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4$lut for cells of type $lut.
Using template $paramod$da98d9e875932ba6a280d468e3b5f7014491d245$lut for cells of type $lut.
Using template $paramod$b1ac80a0cdd076fa54cc05ae05506ad85a8b3505$lut for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e$lut for cells of type $lut.
Using template $paramod$e5147b62611105fcf933af2974b7ef196811f774$lut for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218$lut for cells of type $lut.
Using template $paramod$d7816c8fe91c91c2deadbc0f27110529e1999027$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut.
Using template $paramod$1a0bf6a2024582c33687c0149caac1d863a39438$lut for cells of type $lut.
Using template $paramod$912cf622adc9bd99771a3792f165476315a967eb$lut for cells of type $lut.
Using template $paramod$b514466acaf663c3d2f254afaa521f7edc1c9f5b$lut for cells of type $lut.
Using template $paramod$2742be0ed00fb6d09829fa808d27fe197467639b$lut for cells of type $lut.
Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569$lut for cells of type $lut.
Using template $paramod$d131dcfcf1cb96f1f152e451bfc496220c94f2d0$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut.
Using template $paramod$4ffcd8ad3231d5b7cb41aaf4bd2541724c482154$lut for cells of type $lut.
Using template $paramod$cabe1255f99912a50f8be6297337467146b8a928$lut for cells of type $lut.
Using template $paramod$a369bfe75c0267c4e9af83fc543c2554d3c0cc36$lut for cells of type $lut.
Using template $paramod$d2ec486d8b2889a21aa032cf93d5656e9b3bfcfa$lut for cells of type $lut.
Using template $paramod$713014ced24cd55a8980524f01758be6d6283f08$lut for cells of type $lut.
Using template $paramod$f1a1d9f676e9a8dfefb9d549b9b2c26a026e27e6$lut for cells of type $lut.
Using template $paramod$44a242dd0f200a1cb6d1557047a05466416c6f13$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010010 for cells of type $lut.
Using template $paramod$7ebd08002724a0c14791045e39f3ab3cbae80083$lut for cells of type $lut.
Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04$lut for cells of type $lut.
Using template $paramod$44c048438ccf31b277be5f782aaf187986bf6f3b$lut for cells of type $lut.
Using template $paramod$de327811a6271e6592a0decde17e887b2cc212f1$lut for cells of type $lut.
Using template $paramod$b66cebf810e27d89b39155cd737f78e6be0d69e9$lut for cells of type $lut.
Using template $paramod$a00bfdb2e32e906bd02cb90575300680c9b88850$lut for cells of type $lut.
Using template $paramod$67ed851dcd4a972c20f6ecfb6a1f8766cd1ed285$lut for cells of type $lut.
Using template $paramod$3cd7ba4e37ac845a21f7d679f20c35087949289b$lut for cells of type $lut.
Using template $paramod$6b1d36f4277d381d748d4217cc5ce170d6643752$lut for cells of type $lut.
Using template $paramod$a4310c1caf8884c972a07b326daf75ae88796f65$lut for cells of type $lut.
Using template $paramod$c00ca835df90180f9fa64edccff76d911f6ae54a$lut for cells of type $lut.
Using template $paramod$6bc00c60e367fe102fb6e0e1b97d6bd3cc3165d4$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$65c97ea59a0ce660c2df1ef098338b1e0d2f42ae$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8$lut for cells of type $lut.
Using template $paramod$a8e743603bd27f5355e491419cf4feb4b34f98f2$lut for cells of type $lut.
Using template $paramod$c7cce0263a0278c8f40a85582956846b1d90c21a$lut for cells of type $lut.
Using template $paramod$65a392d177d6dfd207ad73b6c2c4ee6841d0a6e5$lut for cells of type $lut.
Using template $paramod$6d110d0046918c612b20b0b2d3c341f6a7ba2a9c$lut for cells of type $lut.
Using template $paramod$54c22508e627e136a4eb5325979e11a4edb160e6$lut for cells of type $lut.
Using template $paramod$f9cf0acbac93555011fb1308be5916b385fcb0f0$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705$lut for cells of type $lut.
Using template $paramod$521e422991a7ffb3ccd721b21711f1ad6ac662c6$lut for cells of type $lut.
Using template $paramod$fe6b9140fa8badb9aa0c84263397a986020885c5$lut for cells of type $lut.
Using template $paramod$d5661fce5f6c9eec63fc1f9b5ae13f29f48512ba$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100001 for cells of type $lut.
Using template $paramod$57f5bce617b35bc3fd41f75a397684908d884c4b$lut for cells of type $lut.
Using template $paramod$6a4d9f474558398603f28738c05008922ed36f76$lut for cells of type $lut.
Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340$lut for cells of type $lut.
Using template $paramod$69d3e56fe2d9332c54da1b89171bc1c92db4f184$lut for cells of type $lut.
Using template $paramod$e0bb302abce11ed2533e814e32f4feeac6ffe4e2$lut for cells of type $lut.
Using template $paramod$e49596d042a84aed045a2ef506bcae8eb4bb0040$lut for cells of type $lut.
Using template $paramod$e16ec4d9ed5eba7edb4f2e33ba7c3bed811da9cd$lut for cells of type $lut.
Using template $paramod$975817b14e428934970c836668538a3bbe3dd485$lut for cells of type $lut.
Using template $paramod$819904a5b43c3231358348074e8adc9747180049$lut for cells of type $lut.
Using template $paramod$5208f1ee85d8b841695bba828aefbd364748e6bd$lut for cells of type $lut.
Using template $paramod$21da7e88c4ae7140167c3a8153e8b02c54a3d42b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$ec92a12a6c253d77e034afe727d88510388f2a54$lut for cells of type $lut.
Using template $paramod$384ca820697864e5f2b9b7570e4569b99724b771$lut for cells of type $lut.
Using template $paramod$ee027be034f17b4a3101947a266b05925d77c12f$lut for cells of type $lut.
Using template $paramod$c280fabee9d1ea7617fb74c5e39156b7a8e1b514$lut for cells of type $lut.
Using template $paramod$aca078032ff7e6a1667c3b789e10ae0de095a283$lut for cells of type $lut.
Using template $paramod$98c377328f303d3ed9039ca0db26b18f36e929b2$lut for cells of type $lut.
Using template $paramod$71d09d8354f5555fb54ab0bd4f3934a22c793990$lut for cells of type $lut.
Using template $paramod$4ea40776a4bba174d95a4d880d074a40aa4b25c9$lut for cells of type $lut.
Using template $paramod$72db1019c1335c60d7c6344d50ccc95efe353c50$lut for cells of type $lut.
Using template $paramod$3a32ef807aa1d0522624e34977bfe7be743687eb$lut for cells of type $lut.
Using template $paramod$47ed65e4e482e3f8e400747beed1befd70e68963$lut for cells of type $lut.
Using template $paramod$605359e564ea8c0b55a0c688dc8ccd88edbf3ef4$lut for cells of type $lut.
Using template $paramod$839efa77b01d612444ab356b5beb3a9fc43cb6d7$lut for cells of type $lut.
Using template $paramod$fbba4d378f3d360ef95f3c92d09ceb5d02e92f97$lut for cells of type $lut.
Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645$lut for cells of type $lut.
Using template $paramod$ca6127f89015de0391140c4c969456e8ccf4fecb$lut for cells of type $lut.
Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120$lut for cells of type $lut.
Using template $paramod$b8606256ecab549b1d974031e75aeab1d25a6323$lut for cells of type $lut.
Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0$lut for cells of type $lut.
Using template $paramod$4578f71fbba77228c54d62ce629ca5809a29003b$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d$lut for cells of type $lut.
Using template $paramod$e85adda8ca03c59dd705bd345f58957b5394296c$lut for cells of type $lut.
Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09$lut for cells of type $lut.
Using template $paramod$4d4d2de1163efd498341c3ba6f7f01f488e6fa1a$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402$lut for cells of type $lut.
Using template $paramod$fe9279d24bc5073c3c88495fdd1fb99e359a378d$lut for cells of type $lut.
Using template $paramod$09aa8a3143d50cc59564172c2564d6271fb3a300$lut for cells of type $lut.
Using template $paramod$410654a338494d4983a424035c9c9af4ae257a26$lut for cells of type $lut.
Using template $paramod$ff7561cfb7d3ae7112e6974b98c96c3d891737ce$lut for cells of type $lut.
Using template $paramod$d7b2eb972c461206bde800257a50e48284791bae$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$9c8034312613383a60fd318871077c7959d5deee$lut for cells of type $lut.
Using template $paramod$543cfd709cbe0240d568c7dcba69b033ff3e3bf1$lut for cells of type $lut.
Using template $paramod$6aa2b282446f67ade2189ae541d59b9c66c18106$lut for cells of type $lut.
Using template $paramod$9a8bcdc2c322f8a8de53e3dcdde508331178135e$lut for cells of type $lut.
Using template $paramod$62c3deccab91e6f4a72f5f3cce4abf5fa05e071b$lut for cells of type $lut.
Using template $paramod$93c8059fc0e26e858e27026ca777b0db9be92739$lut for cells of type $lut.
Using template $paramod$9180657acf0913fe438a4942d663b388f6502b32$lut for cells of type $lut.
Using template $paramod$23264f4f8a208e703e3520efb10b5171cc8ca9fc$lut for cells of type $lut.
Using template $paramod$f462f5397ad85741e8d903cdbf9a12985b305a13$lut for cells of type $lut.
Using template $paramod$9071c612ebf5b46097f2977e38acd564cf55637d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
Using template $paramod$d40b9254d01cca1a5395f2263a9d12df7b6cb3c1$lut for cells of type $lut.
Using template $paramod$66fa5f0091ddf0e95fc21f4cc02805ddf33c3024$lut for cells of type $lut.
Using template $paramod$af4cd3cc8c9282b643f11edc71a41a6eabf51e7d$lut for cells of type $lut.
Using template $paramod$4c892e55a9e30af841c5d0a2a15b9d37ef7970ca$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5$lut for cells of type $lut.
Using template $paramod$22cc3c6b4f57b7128c5f3a6c91c8cf239c3a0ce0$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8155 debug messages>
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in harness_nms_activation_banked.
Optimizing lut $abc$77999$lut$aiger$o212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger$o210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$6136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger$o130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3833.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1772.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5271.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$879.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$915.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4628.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$2172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6449.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78022.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger$o210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger$o145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$7222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7208.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$7177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$4435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$1470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78011.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$7039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$2503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$7007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$4548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$7002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$6198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$5090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$5319.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$1622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$3217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$2554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$3217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6932.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$6162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$1667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$5683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$4131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$77999$lut$aiger77998$1674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger$o140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$77999$lut$aiger77998$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$77999$lut$aiger77998$2843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$78028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$77999$lut$aiger77998$3374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 5830 unused wires.
4.49. Executing AUTONAME pass.
Renamed 7292 objects in module harness_nms_activation_banked.
<suppressed ~7292 debug messages>
4.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `harness_nms_activation_banked'. Setting top module to harness_nms_activation_banked.
4.50.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
4.50.2. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Removed 0 unused modules.
4.51. Printing statistics.
=== harness_nms_activation_banked ===
+----------Local Count, excluding submodules.
|
2956 wires
8412 wire bits
2956 public wires
8412 public wire bits
4 ports
18 port bits
1 cells
1 $scopeinfo
4476 submodules
308 L6MUX21
3251 LUT4
749 PFUMX
16 TRELLIS_DPR16X4
152 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
1 harness_nms_activation_banked
+----------Count including submodules.
|
2956 wires
8412 wire bits
2956 public wires
8412 public wire bits
4 ports
18 port bits
- memories
- memory bits
- processes
1 cells
1 $scopeinfo
4476 submodules
308 L6MUX21
3251 LUT4
749 PFUMX
16 TRELLIS_DPR16X4
152 TRELLIS_FF
4.52. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.53. Executing JSON backend.
Warnings: 12 unique messages, 22 total
End of script. Logfile hash: 50e65614a2, time: 2.80s, user: 1.48s, system: 0.05s, MEM: 206.39 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 48% 1x abc9_exe (1 sec), 10% 12x techmap (0 sec), ...
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