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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Running command `read_verilog hardware/v2/nms/rtl/nms_activation_banked.v hardware/v2/nms/synthesis/harness_nms_activation_banked.v; chparam -set N_SLOTS 8 -set N_BANKS 4 -set MAX_TILES 16 harness_nms_activation_banked; synth_ecp5 -json hardware/v2/nms/synthesis/act_bank_n8_b4/top.json -top harness_nms_activation_banked' --
1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/rtl/nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\harness_nms_activation_banked'.
Successfully finished Verilog frontend.
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_activation_banked'.
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$a095d535a428e5e7865d11fea3595189cbf190a3\harness_nms_activation_banked'.
4. Executing SYNTH_LATTICE pass.
4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
4.3. Executing HIERARCHY pass (managing design hierarchy).
4.3.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: \nms_activation_banked
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_banked'.
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
4.3.3. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked
4.3.4. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked
Removing unused module `\nms_activation_banked'.
Removed 1 unused modules.
4.4. Executing PROC pass (convert processes to netlists).
4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443 in module harness_nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448 in module harness_nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed 64 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Marked 132 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759 in module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
Removed a total of 72 dead cases.
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 20 redundant assignments.
Promoted 197 assignments to connections.
4.4.4. Executing PROC_INIT pass (extract init attributes).
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~155 debug messages>
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
1/1: $0\lfsr[31:0]
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
1/3: $0\chk[7:0]
2/3: $1\chk_next[7:0]
3/3: $1\k[31:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$754_DATA[63:0]$1460
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$753_DATA[63:0]$1457
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$752_DATA[63:0]$1454
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$751_DATA[63:0]$1451
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$750_DATA[63:0]$1448
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$749_DATA[63:0]$1445
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$748_DATA[63:0]$1442
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$747_DATA[63:0]$1439
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1436'.
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1435'.
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1434'.
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1433'.
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
1/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1430
2/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_DATA[63:0]$1429
3/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_ADDR[31:0]$1428
4/4: $0\GEN_BANK[3].rd_data_r[63:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
1/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1418
2/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_DATA[63:0]$1417
3/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_ADDR[31:0]$1416
4/4: $0\GEN_BANK[2].rd_data_r[63:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
1/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1406
2/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_DATA[63:0]$1405
3/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_ADDR[31:0]$1404
4/4: $0\GEN_BANK[1].rd_data_r[63:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
1/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1394
2/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_DATA[63:0]$1393
3/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_ADDR[31:0]$1392
4/4: $0\GEN_BANK[0].rd_data_r[63:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
1/24: $6\i[31:0]
2/24: $0\slot_bank_stage1[7][1:0]
3/24: $0\slot_bank_stage1[6][1:0]
4/24: $0\slot_bank_stage1[5][1:0]
5/24: $0\slot_bank_stage1[4][1:0]
6/24: $0\slot_bank_stage1[3][1:0]
7/24: $0\slot_bank_stage1[2][1:0]
8/24: $0\slot_bank_stage1[1][1:0]
9/24: $0\slot_bank_stage1[0][1:0]
10/24: $0\ack[7:0]
11/24: $0\ack_stage1[7:0]
12/24: $2\b[31:0]
13/24: $0\bank_rd_addr_stage1[3][1:0]
14/24: $0\bank_rd_en_stage1[3][0:0]
15/24: $0\bank_rd_addr_stage1[2][1:0]
16/24: $0\bank_rd_en_stage1[2][0:0]
17/24: $0\bank_rd_addr_stage1[1][1:0]
18/24: $0\bank_rd_en_stage1[1][0:0]
19/24: $0\bank_rd_addr_stage1[0][1:0]
20/24: $0\bank_rd_en_stage1[0][0:0]
21/24: $0\rr_ptr[3][2:0]
22/24: $0\rr_ptr[2][2:0]
23/24: $0\rr_ptr[1][2:0]
24/24: $0\rr_ptr[0][2:0]
Creating decoders for process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
1/292: $28\ack_comb[7:0] [7]
2/292: $35\ack_comb[6:6]
3/292: $34\ack_comb[5:5]
4/292: $33\ack_comb[4:4]
5/292: $32\ack_comb[3:3]
6/292: $31\ack_comb[2:2]
7/292: $30\ack_comb[1:1]
8/292: $29\ack_comb[0:0]
9/292: $4\i[31:0]
10/292: $28\ack_comb[7:0] [6]
11/292: $28\ack_comb[7:0] [5]
12/292: $28\ack_comb[7:0] [4]
13/292: $28\ack_comb[7:0] [3]
14/292: $28\ack_comb[7:0] [2]
15/292: $28\ack_comb[7:0] [1]
16/292: $28\ack_comb[7:0] [0]
17/292: $36\ack_comb[7:7]
18/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_DATA[3:0]$1343
19/292: $8\win_first[3][2:0]
20/292: $8\win_tile_idx[3][3:0]
21/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_DATA[3:0]$1342
22/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$746_ADDR[2:0]$1341
23/292: $8\win_valid[3][0:0]
24/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$745_DATA[1:0]$1335
25/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_DATA[3:0]$1332
26/292: $7\win_first[3][2:0]
27/292: $7\win_tile_idx[3][3:0]
28/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_DATA[3:0]$1331
29/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$744_ADDR[2:0]$1330
30/292: $7\win_valid[3][0:0]
31/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$743_DATA[1:0]$1324
32/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_DATA[3:0]$1321
33/292: $6\win_first[3][2:0]
34/292: $6\win_tile_idx[3][3:0]
35/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_DATA[3:0]$1320
36/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$742_ADDR[2:0]$1319
37/292: $6\win_valid[3][0:0]
38/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$741_DATA[1:0]$1313
39/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_DATA[3:0]$1310
40/292: $5\win_first[3][2:0]
41/292: $5\win_tile_idx[3][3:0]
42/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_DATA[3:0]$1309
43/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$740_ADDR[2:0]$1308
44/292: $5\win_valid[3][0:0]
45/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$739_DATA[1:0]$1302
46/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_DATA[3:0]$1299
47/292: $4\win_first[3][2:0]
48/292: $4\win_tile_idx[3][3:0]
49/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_DATA[3:0]$1298
50/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$738_ADDR[2:0]$1297
51/292: $4\win_valid[3][0:0]
52/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$737_DATA[1:0]$1291
53/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_DATA[3:0]$1288
54/292: $3\win_first[3][2:0]
55/292: $3\win_tile_idx[3][3:0]
56/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_DATA[3:0]$1287
57/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$736_ADDR[2:0]$1286
58/292: $3\win_valid[3][0:0]
59/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$735_DATA[1:0]$1280
60/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_DATA[3:0]$1277
61/292: $2\win_first[3][2:0]
62/292: $2\win_tile_idx[3][3:0]
63/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_DATA[3:0]$1276
64/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$734_ADDR[2:0]$1275
65/292: $2\win_valid[3][0:0]
66/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$733_DATA[1:0]$1269
67/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_DATA[3:0]$1266
68/292: $1\win_first[3][2:0]
69/292: $1\win_tile_idx[3][3:0]
70/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_DATA[3:0]$1265
71/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$732_ADDR[2:0]$1264
72/292: $1\win_valid[3][0:0]
73/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$731_DATA[1:0]$1258
74/292: $19\ack_comb[7:0] [7]
75/292: $26\ack_comb[6:6]
76/292: $25\ack_comb[5:5]
77/292: $24\ack_comb[4:4]
78/292: $23\ack_comb[3:3]
79/292: $22\ack_comb[2:2]
80/292: $21\ack_comb[1:1]
81/292: $20\ack_comb[0:0]
82/292: $3\i[31:0]
83/292: $19\ack_comb[7:0] [6]
84/292: $19\ack_comb[7:0] [5]
85/292: $19\ack_comb[7:0] [4]
86/292: $19\ack_comb[7:0] [3]
87/292: $19\ack_comb[7:0] [2]
88/292: $19\ack_comb[7:0] [1]
89/292: $19\ack_comb[7:0] [0]
90/292: $27\ack_comb[7:7]
91/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_DATA[3:0]$1223
92/292: $8\win_first[2][2:0]
93/292: $8\win_tile_idx[2][3:0]
94/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_DATA[3:0]$1222
95/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$730_ADDR[2:0]$1221
96/292: $8\win_valid[2][0:0]
97/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$729_DATA[1:0]$1215
98/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_DATA[3:0]$1212
99/292: $7\win_first[2][2:0]
100/292: $7\win_tile_idx[2][3:0]
101/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_DATA[3:0]$1211
102/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$728_ADDR[2:0]$1210
103/292: $7\win_valid[2][0:0]
104/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$727_DATA[1:0]$1204
105/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_DATA[3:0]$1201
106/292: $6\win_first[2][2:0]
107/292: $6\win_tile_idx[2][3:0]
108/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_DATA[3:0]$1200
109/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$726_ADDR[2:0]$1199
110/292: $6\win_valid[2][0:0]
111/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$725_DATA[1:0]$1193
112/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_DATA[3:0]$1190
113/292: $5\win_first[2][2:0]
114/292: $5\win_tile_idx[2][3:0]
115/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_DATA[3:0]$1189
116/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$724_ADDR[2:0]$1188
117/292: $5\win_valid[2][0:0]
118/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$723_DATA[1:0]$1182
119/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_DATA[3:0]$1179
120/292: $4\win_first[2][2:0]
121/292: $4\win_tile_idx[2][3:0]
122/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_DATA[3:0]$1178
123/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$722_ADDR[2:0]$1177
124/292: $4\win_valid[2][0:0]
125/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$721_DATA[1:0]$1171
126/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_DATA[3:0]$1168
127/292: $3\win_first[2][2:0]
128/292: $3\win_tile_idx[2][3:0]
129/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_DATA[3:0]$1167
130/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$720_ADDR[2:0]$1166
131/292: $3\win_valid[2][0:0]
132/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$719_DATA[1:0]$1160
133/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_DATA[3:0]$1157
134/292: $2\win_first[2][2:0]
135/292: $2\win_tile_idx[2][3:0]
136/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_DATA[3:0]$1156
137/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$718_ADDR[2:0]$1155
138/292: $2\win_valid[2][0:0]
139/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$717_DATA[1:0]$1149
140/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_DATA[3:0]$1146
141/292: $1\win_first[2][2:0]
142/292: $1\win_tile_idx[2][3:0]
143/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_DATA[3:0]$1145
144/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$716_ADDR[2:0]$1144
145/292: $1\win_valid[2][0:0]
146/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$715_DATA[1:0]$1138
147/292: $10\ack_comb[7:0] [7]
148/292: $17\ack_comb[6:6]
149/292: $16\ack_comb[5:5]
150/292: $15\ack_comb[4:4]
151/292: $14\ack_comb[3:3]
152/292: $13\ack_comb[2:2]
153/292: $12\ack_comb[1:1]
154/292: $11\ack_comb[0:0]
155/292: $2\i[31:0]
156/292: $10\ack_comb[7:0] [6]
157/292: $10\ack_comb[7:0] [5]
158/292: $10\ack_comb[7:0] [4]
159/292: $10\ack_comb[7:0] [3]
160/292: $10\ack_comb[7:0] [2]
161/292: $10\ack_comb[7:0] [1]
162/292: $10\ack_comb[7:0] [0]
163/292: $18\ack_comb[7:7]
164/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_DATA[3:0]$1103
165/292: $8\win_first[1][2:0]
166/292: $8\win_tile_idx[1][3:0]
167/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_DATA[3:0]$1102
168/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$714_ADDR[2:0]$1101
169/292: $8\win_valid[1][0:0]
170/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$713_DATA[1:0]$1095
171/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_DATA[3:0]$1092
172/292: $7\win_first[1][2:0]
173/292: $7\win_tile_idx[1][3:0]
174/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_DATA[3:0]$1091
175/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$712_ADDR[2:0]$1090
176/292: $7\win_valid[1][0:0]
177/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$711_DATA[1:0]$1084
178/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1081
179/292: $6\win_first[1][2:0]
180/292: $6\win_tile_idx[1][3:0]
181/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1080
182/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_ADDR[2:0]$1079
183/292: $6\win_valid[1][0:0]
184/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$709_DATA[1:0]$1073
185/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$1070
186/292: $5\win_first[1][2:0]
187/292: $5\win_tile_idx[1][3:0]
188/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$1069
189/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_ADDR[2:0]$1068
190/292: $5\win_valid[1][0:0]
191/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$707_DATA[1:0]$1062
192/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$1059
193/292: $4\win_first[1][2:0]
194/292: $4\win_tile_idx[1][3:0]
195/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$1058
196/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_ADDR[2:0]$1057
197/292: $4\win_valid[1][0:0]
198/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$705_DATA[1:0]$1051
199/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$1048
200/292: $3\win_first[1][2:0]
201/292: $3\win_tile_idx[1][3:0]
202/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$1047
203/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_ADDR[2:0]$1046
204/292: $3\win_valid[1][0:0]
205/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$703_DATA[1:0]$1040
206/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$1037
207/292: $2\win_first[1][2:0]
208/292: $2\win_tile_idx[1][3:0]
209/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$1036
210/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_ADDR[2:0]$1035
211/292: $2\win_valid[1][0:0]
212/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$701_DATA[1:0]$1029
213/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$1026
214/292: $1\win_first[1][2:0]
215/292: $1\win_tile_idx[1][3:0]
216/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$1025
217/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_ADDR[2:0]$1024
218/292: $1\win_valid[1][0:0]
219/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$699_DATA[1:0]$1018
220/292: $1\ack_comb[7:0] [7]
221/292: $8\ack_comb[6:6]
222/292: $7\ack_comb[5:5]
223/292: $6\ack_comb[4:4]
224/292: $5\ack_comb[3:3]
225/292: $4\ack_comb[2:2]
226/292: $3\ack_comb[1:1]
227/292: $2\ack_comb[0:0]
228/292: $1\i[31:0]
229/292: $1\ack_comb[7:0] [6]
230/292: $1\ack_comb[7:0] [5]
231/292: $1\ack_comb[7:0] [4]
232/292: $1\ack_comb[7:0] [3]
233/292: $1\ack_comb[7:0] [2]
234/292: $1\ack_comb[7:0] [1]
235/292: $1\ack_comb[7:0] [0]
236/292: $9\ack_comb[7:7]
237/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$983
238/292: $8\win_first[0][2:0]
239/292: $8\win_tile_idx[0][3:0]
240/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$982
241/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_ADDR[2:0]$981
242/292: $8\win_valid[0][0:0]
243/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$697_DATA[1:0]$975
244/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$972
245/292: $7\win_first[0][2:0]
246/292: $7\win_tile_idx[0][3:0]
247/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$971
248/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_ADDR[2:0]$970
249/292: $7\win_valid[0][0:0]
250/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$695_DATA[1:0]$964
251/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$961
252/292: $6\win_first[0][2:0]
253/292: $6\win_tile_idx[0][3:0]
254/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$960
255/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_ADDR[2:0]$959
256/292: $6\win_valid[0][0:0]
257/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$693_DATA[1:0]$953
258/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$950
259/292: $5\win_first[0][2:0]
260/292: $5\win_tile_idx[0][3:0]
261/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$949
262/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_ADDR[2:0]$948
263/292: $5\win_valid[0][0:0]
264/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$691_DATA[1:0]$942
265/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$939
266/292: $4\win_first[0][2:0]
267/292: $4\win_tile_idx[0][3:0]
268/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$938
269/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_ADDR[2:0]$937
270/292: $4\win_valid[0][0:0]
271/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$689_DATA[1:0]$931
272/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$928
273/292: $3\win_first[0][2:0]
274/292: $3\win_tile_idx[0][3:0]
275/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$927
276/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_ADDR[2:0]$926
277/292: $3\win_valid[0][0:0]
278/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$687_DATA[1:0]$920
279/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$917
280/292: $2\win_first[0][2:0]
281/292: $2\win_tile_idx[0][3:0]
282/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$916
283/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_ADDR[2:0]$915
284/292: $2\win_valid[0][0:0]
285/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$685_DATA[1:0]$909
286/292: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$906
287/292: $1\win_first[0][2:0]
288/292: $1\win_tile_idx[0][3:0]
289/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$905
290/292: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_ADDR[2:0]$904
291/292: $1\win_valid[0][0:0]
292/292: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$683_DATA[1:0]$898
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$754_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$753_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$752_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$751_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$750_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$749_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$748_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$747_DATA' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_data_reg[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1436'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_data_reg[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1435'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_data_reg[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1434'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_data_reg[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1433'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\b' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\i' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\ack_comb' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\scan_i' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\cand' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_valid[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_valid[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_valid[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_valid[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_tile_idx[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_tile_idx[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_tile_idx[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_tile_idx[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_first[0]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_first[1]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_first[2]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\win_first[3]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[4]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[5]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[6]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_tile_idx[7]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[4]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[5]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[6]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\req_bank[7]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[4]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[5]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[6]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
No latch inferred for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_comb[7]' from process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\harness_nms_activation_banked.\lfsr' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
created $dff cell `$procdff$3086' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\k' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$3087' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$3088' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk_next' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$3089' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\GEN_BANK[3].rd_data_r' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
created $dff cell `$procdff$3090' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_ADDR' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
created $dff cell `$procdff$3091' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_DATA' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
created $dff cell `$procdff$3092' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
created $dff cell `$procdff$3093' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\GEN_BANK[2].rd_data_r' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
created $dff cell `$procdff$3094' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_ADDR' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
created $dff cell `$procdff$3095' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_DATA' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
created $dff cell `$procdff$3096' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
created $dff cell `$procdff$3097' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\GEN_BANK[1].rd_data_r' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
created $dff cell `$procdff$3098' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_ADDR' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
created $dff cell `$procdff$3099' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_DATA' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
created $dff cell `$procdff$3100' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
created $dff cell `$procdff$3101' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\GEN_BANK[0].rd_data_r' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
created $dff cell `$procdff$3102' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_ADDR' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
created $dff cell `$procdff$3103' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_DATA' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
created $dff cell `$procdff$3104' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
created $dff cell `$procdff$3105' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\b' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3106' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\i' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3107' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\ack' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3108' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\ack_stage1' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3109' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\rr_ptr[0]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3110' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\rr_ptr[1]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3111' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\rr_ptr[2]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3112' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\rr_ptr[3]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3113' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_en_stage1[0]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3114' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_en_stage1[1]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3115' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_en_stage1[2]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3116' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_en_stage1[3]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3117' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_addr_stage1[0]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3118' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_addr_stage1[1]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3119' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_addr_stage1[2]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3120' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\bank_rd_addr_stage1[3]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3121' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[0]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3122' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[1]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3123' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[2]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3124' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[3]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3125' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[4]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3126' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[5]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3127' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[6]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3128' with positive edge clock.
Creating register for signal `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.\slot_bank_stage1[7]' using process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
created $dff cell `$procdff$3129' with positive edge clock.
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1458'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1455'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1452'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1449'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1446'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1443'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1440'.
Found and cleaned up 1 empty switch in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1437'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1436'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1435'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1434'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1433'.
Found and cleaned up 2 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1424'.
Found and cleaned up 2 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1412'.
Found and cleaned up 2 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1400'.
Found and cleaned up 2 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1388'.
Found and cleaned up 5 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1376'.
Found and cleaned up 132 empty switches in `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
Removing empty process `$paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$759'.
Cleaned up 155 empty switches.
4.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~1 debug messages>
Optimizing module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
<suppressed ~100 debug messages>
4.5. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Checking module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked...
Warning: Drivers conflicting with a constant 1'0 driver:
port Q[0] of cell $procdff$3107 ($dff)
port Q[1] of cell $procdff$3107 ($dff)
port Q[2] of cell $procdff$3107 ($dff)
port Q[4] of cell $procdff$3107 ($dff)
port Q[5] of cell $procdff$3107 ($dff)
port Q[6] of cell $procdff$3107 ($dff)
port Q[7] of cell $procdff$3107 ($dff)
port Q[8] of cell $procdff$3107 ($dff)
port Q[9] of cell $procdff$3107 ($dff)
port Q[10] of cell $procdff$3107 ($dff)
port Q[11] of cell $procdff$3107 ($dff)
port Q[12] of cell $procdff$3107 ($dff)
port Q[13] of cell $procdff$3107 ($dff)
port Q[14] of cell $procdff$3107 ($dff)
port Q[15] of cell $procdff$3107 ($dff)
port Q[16] of cell $procdff$3107 ($dff)
port Q[17] of cell $procdff$3107 ($dff)
port Q[18] of cell $procdff$3107 ($dff)
port Q[19] of cell $procdff$3107 ($dff)
port Q[20] of cell $procdff$3107 ($dff)
port Q[21] of cell $procdff$3107 ($dff)
port Q[22] of cell $procdff$3107 ($dff)
port Q[23] of cell $procdff$3107 ($dff)
port Q[24] of cell $procdff$3107 ($dff)
port Q[25] of cell $procdff$3107 ($dff)
port Q[26] of cell $procdff$3107 ($dff)
port Q[27] of cell $procdff$3107 ($dff)
port Q[28] of cell $procdff$3107 ($dff)
port Q[29] of cell $procdff$3107 ($dff)
port Q[30] of cell $procdff$3107 ($dff)
port Q[31] of cell $procdff$3107 ($dff)
port Q[0] of cell $procdff$3106 ($dff)
port Q[1] of cell $procdff$3106 ($dff)
port Q[3] of cell $procdff$3106 ($dff)
port Q[4] of cell $procdff$3106 ($dff)
port Q[5] of cell $procdff$3106 ($dff)
port Q[6] of cell $procdff$3106 ($dff)
port Q[7] of cell $procdff$3106 ($dff)
port Q[8] of cell $procdff$3106 ($dff)
port Q[9] of cell $procdff$3106 ($dff)
port Q[10] of cell $procdff$3106 ($dff)
port Q[11] of cell $procdff$3106 ($dff)
port Q[12] of cell $procdff$3106 ($dff)
port Q[13] of cell $procdff$3106 ($dff)
port Q[14] of cell $procdff$3106 ($dff)
port Q[15] of cell $procdff$3106 ($dff)
port Q[16] of cell $procdff$3106 ($dff)
port Q[17] of cell $procdff$3106 ($dff)
port Q[18] of cell $procdff$3106 ($dff)
port Q[19] of cell $procdff$3106 ($dff)
port Q[20] of cell $procdff$3106 ($dff)
port Q[21] of cell $procdff$3106 ($dff)
port Q[22] of cell $procdff$3106 ($dff)
port Q[23] of cell $procdff$3106 ($dff)
port Q[24] of cell $procdff$3106 ($dff)
port Q[25] of cell $procdff$3106 ($dff)
port Q[26] of cell $procdff$3106 ($dff)
port Q[27] of cell $procdff$3106 ($dff)
port Q[28] of cell $procdff$3106 ($dff)
port Q[29] of cell $procdff$3106 ($dff)
port Q[30] of cell $procdff$3106 ($dff)
port Q[31] of cell $procdff$3106 ($dff)
Warning: Drivers conflicting with a constant 1'1 driver:
port Q[3] of cell $procdff$3107 ($dff)
port Q[2] of cell $procdff$3106 ($dff)
Found and reported 2 problems.
4.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$e90da0f88523154d83ffe829e3503d67df2fa483\nms_activation_banked.
<suppressed ~1 debug messages>
4.7. Executing TRIBUF pass.
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
4.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~108 debug messages>
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 82 unused cells and 1168 unused wires.
<suppressed ~89 debug messages>
4.11. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.12. Executing OPT pass (performing simple optimizations).
4.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1253 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 994 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 991 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~786 debug messages>
Removed a total of 262 cells.
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $flatten\dut.$procmux$1642.
dead port 2/2 on $mux $flatten\dut.$procmux$1648.
dead port 2/2 on $mux $flatten\dut.$procmux$1654.
dead port 2/2 on $mux $flatten\dut.$procmux$1660.
dead port 2/2 on $mux $flatten\dut.$procmux$1666.
dead port 2/2 on $mux $flatten\dut.$procmux$1672.
dead port 2/2 on $mux $flatten\dut.$procmux$1678.
dead port 2/2 on $mux $flatten\dut.$procmux$1708.
dead port 2/2 on $mux $flatten\dut.$procmux$1720.
dead port 2/2 on $mux $flatten\dut.$procmux$1756.
dead port 2/2 on $mux $flatten\dut.$procmux$1792.
dead port 2/2 on $mux $flatten\dut.$procmux$1828.
dead port 2/2 on $mux $flatten\dut.$procmux$1864.
dead port 2/2 on $mux $flatten\dut.$procmux$1900.
dead port 2/2 on $mux $flatten\dut.$procmux$1936.
dead port 2/2 on $mux $flatten\dut.$procmux$1972.
dead port 2/2 on $mux $flatten\dut.$procmux$2005.
dead port 2/2 on $mux $flatten\dut.$procmux$2011.
dead port 2/2 on $mux $flatten\dut.$procmux$2017.
dead port 2/2 on $mux $flatten\dut.$procmux$2023.
dead port 2/2 on $mux $flatten\dut.$procmux$2029.
dead port 2/2 on $mux $flatten\dut.$procmux$2035.
dead port 2/2 on $mux $flatten\dut.$procmux$2041.
dead port 2/2 on $mux $flatten\dut.$procmux$2071.
dead port 2/2 on $mux $flatten\dut.$procmux$2083.
dead port 2/2 on $mux $flatten\dut.$procmux$2119.
dead port 2/2 on $mux $flatten\dut.$procmux$2155.
dead port 2/2 on $mux $flatten\dut.$procmux$2191.
dead port 2/2 on $mux $flatten\dut.$procmux$2227.
dead port 2/2 on $mux $flatten\dut.$procmux$2263.
dead port 2/2 on $mux $flatten\dut.$procmux$2299.
dead port 2/2 on $mux $flatten\dut.$procmux$2335.
dead port 2/2 on $mux $flatten\dut.$procmux$2368.
dead port 2/2 on $mux $flatten\dut.$procmux$2374.
dead port 2/2 on $mux $flatten\dut.$procmux$2380.
dead port 2/2 on $mux $flatten\dut.$procmux$2386.
dead port 2/2 on $mux $flatten\dut.$procmux$2392.
dead port 2/2 on $mux $flatten\dut.$procmux$2398.
dead port 2/2 on $mux $flatten\dut.$procmux$2404.
dead port 2/2 on $mux $flatten\dut.$procmux$2434.
dead port 2/2 on $mux $flatten\dut.$procmux$2446.
dead port 2/2 on $mux $flatten\dut.$procmux$2482.
dead port 2/2 on $mux $flatten\dut.$procmux$2518.
dead port 2/2 on $mux $flatten\dut.$procmux$2554.
dead port 2/2 on $mux $flatten\dut.$procmux$2590.
dead port 2/2 on $mux $flatten\dut.$procmux$2626.
dead port 2/2 on $mux $flatten\dut.$procmux$2662.
dead port 2/2 on $mux $flatten\dut.$procmux$2698.
dead port 2/2 on $mux $flatten\dut.$procmux$2731.
dead port 2/2 on $mux $flatten\dut.$procmux$2737.
dead port 2/2 on $mux $flatten\dut.$procmux$2743.
dead port 2/2 on $mux $flatten\dut.$procmux$2749.
dead port 2/2 on $mux $flatten\dut.$procmux$2755.
dead port 2/2 on $mux $flatten\dut.$procmux$2761.
dead port 2/2 on $mux $flatten\dut.$procmux$2767.
dead port 2/2 on $mux $flatten\dut.$procmux$2796.
dead port 2/2 on $mux $flatten\dut.$procmux$2808.
dead port 2/2 on $mux $flatten\dut.$procmux$2844.
dead port 2/2 on $mux $flatten\dut.$procmux$2880.
dead port 2/2 on $mux $flatten\dut.$procmux$2916.
dead port 2/2 on $mux $flatten\dut.$procmux$2952.
dead port 2/2 on $mux $flatten\dut.$procmux$2988.
dead port 2/2 on $mux $flatten\dut.$procmux$3024.
dead port 2/2 on $mux $flatten\dut.$procmux$3060.
Removed 64 multiplexer ports.
<suppressed ~1012 debug messages>
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1514:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_EN[63:0]$1427 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1525:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_EN[63:0]$1415 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1536:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_EN[63:0]$1403 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1547:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_EN[63:0]$1391 [0] }
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 4 changes.
4.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 927 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 326 unused wires.
<suppressed ~1 debug messages>
4.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~772 debug messages>
4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 927 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
4.13. Executing FSM pass (extract and optimize FSM).
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking harness_nms_activation_banked.dut.ack_stage1 as FSM state register:
Users of register don't seem to benefit from recoding.
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.14. Executing OPT pass (performing simple optimizations).
4.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 927 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~772 debug messages>
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 927 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$3086 ($dff) from module harness_nms_activation_banked (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:26$447_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
Adding SRST signal on $procdff$3088 ($dff) from module harness_nms_activation_banked (D = $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:56$457_Y, Q = \chk, rval = 8'00000000).
Adding SRST signal on $flatten\dut.$procdff$3122 ($dff) from module harness_nms_activation_banked (D = \lfsr [1:0], Q = \dut.slot_bank_stage1[0], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3121 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[3] [3:2], Q = \dut.bank_rd_addr_stage1[3], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3120 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[2] [3:2], Q = \dut.bank_rd_addr_stage1[2], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3119 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[1] [3:2], Q = \dut.bank_rd_addr_stage1[1], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3118 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[0] [3:2], Q = \dut.bank_rd_addr_stage1[0], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3117 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[3], Q = \dut.bank_rd_en_stage1[3], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$3116 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[2], Q = \dut.bank_rd_en_stage1[2], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$3115 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[1], Q = \dut.bank_rd_en_stage1[1], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$3114 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[0], Q = \dut.bank_rd_en_stage1[0], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$3113 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1615_Y, Q = \dut.rr_ptr[3], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$3147 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1384_Y, Q = \dut.rr_ptr[3]).
Adding SRST signal on $flatten\dut.$procdff$3112 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1620_Y, Q = \dut.rr_ptr[2], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$3149 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1382_Y, Q = \dut.rr_ptr[2]).
Adding SRST signal on $flatten\dut.$procdff$3111 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1625_Y, Q = \dut.rr_ptr[1], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$3151 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1380_Y, Q = \dut.rr_ptr[1]).
Adding SRST signal on $flatten\dut.$procdff$3110 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1630_Y, Q = \dut.rr_ptr[0], rval = 3'000).
Adding EN signal on $auto$ff.cc:337:slice$3153 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1378_Y, Q = \dut.rr_ptr[0]).
Adding SRST signal on $flatten\dut.$procdff$3109 ($dff) from module harness_nms_activation_banked (D = \dut.ack_comb, Q = \dut.ack_stage1, rval = 8'00000000).
Adding SRST signal on $flatten\dut.$procdff$3108 ($dff) from module harness_nms_activation_banked (D = \dut.ack_stage1, Q = \dut.ack, rval = 8'00000000).
Adding EN signal on $flatten\dut.$procdff$3102 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1396_DATA, Q = \dut.GEN_BANK[0].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$3098 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1408_DATA, Q = \dut.GEN_BANK[1].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$3094 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1420_DATA, Q = \dut.GEN_BANK[2].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$3090 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1432_DATA, Q = \dut.GEN_BANK[3].rd_data_r).
Adding SRST signal on $flatten\dut.$procdff$3126 ($dff) from module harness_nms_activation_banked (D = \lfsr [17:16], Q = \dut.slot_bank_stage1[4], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3127 ($dff) from module harness_nms_activation_banked (D = \lfsr [21:20], Q = \dut.slot_bank_stage1[5], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3125 ($dff) from module harness_nms_activation_banked (D = \lfsr [13:12], Q = \dut.slot_bank_stage1[3], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3124 ($dff) from module harness_nms_activation_banked (D = \lfsr [9:8], Q = \dut.slot_bank_stage1[2], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3128 ($dff) from module harness_nms_activation_banked (D = \lfsr [25:24], Q = \dut.slot_bank_stage1[6], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3129 ($dff) from module harness_nms_activation_banked (D = \lfsr [29:28], Q = \dut.slot_bank_stage1[7], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$3123 ($dff) from module harness_nms_activation_banked (D = \lfsr [5:4], Q = \dut.slot_bank_stage1[1], rval = 2'00).
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 31 unused cells and 31 unused wires.
<suppressed ~32 debug messages>
4.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~722 debug messages>
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 897 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
4.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$3130 (dut.GEN_BANK[3].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$3131 (dut.GEN_BANK[2].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$3133 (dut.GEN_BANK[0].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$3132 (dut.GEN_BANK[1].mem).
Removed top 7 bits (of 8) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3156 ($sdff).
Removed top 7 bits (of 8) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3155 ($sdff).
Removed top 7 bits (of 8) from port B of cell harness_nms_activation_banked.$xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:54$449 ($xor).
Removed top 24 bits (of 32) from mux cell harness_nms_activation_banked.$procmux$1462 ($mux).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3058_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3057_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3056_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3022_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3021_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$3020_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2986_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2985_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2984_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2950_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2949_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2948_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2914_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2913_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2912_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2878_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2877_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2876_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2842_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2841_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2840_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2806_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2805_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2804_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2696_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2695_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2694_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2660_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2659_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2658_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2624_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2623_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2622_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2588_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2587_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2586_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2552_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2551_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2550_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2516_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2515_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2514_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2480_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2479_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2478_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2444_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2443_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2442_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2333_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2332_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2331_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2297_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2296_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2295_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2261_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2260_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2259_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2225_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2224_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2223_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2189_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2188_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2187_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2153_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2152_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2151_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2117_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2116_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2115_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2081_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2080_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$2079_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1970_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1969_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1968_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1934_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1933_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1932_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1898_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1897_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1896_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1862_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1861_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1860_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1826_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1825_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1824_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1790_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1789_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1788_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1754_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1753_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1752_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1718_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1717_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1716_CMP0 ($eq).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1699 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1696 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1693 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1690 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1687 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1684 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1670 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1664 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1658 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1652 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1646 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1640 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1636 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1553 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1542 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1531 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1520 ($mux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1511_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1508 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1506_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1503 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1501_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1498 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1496_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1493 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1491_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1488 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1486_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1483 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1481_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1478 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1476_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1473 ($pmux).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1336 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1325 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1322 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1322 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1314 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1311 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1311 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1303 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1300 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1300 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1292 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1281 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1270 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1259 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1216 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1213 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1213 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1205 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1202 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1202 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1194 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1191 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1191 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1183 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1180 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1180 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1172 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1161 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1150 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1139 ($shiftx).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1132 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1128 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1124 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1120 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1116 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1112 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1108 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$1104 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1097 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1096 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1093 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1093 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1086 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1085 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1082 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1082 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1075 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1074 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1071 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1071 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1064 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1063 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1060 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1060 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1053 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1052 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1049 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1049 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1042 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1041 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1038 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1038 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1031 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1030 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1027 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1027 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$1020 ($eq).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1019 ($shiftx).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$976 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$973 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$973 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$965 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$962 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$962 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$954 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$951 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$951 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$943 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$940 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$940 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$932 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$929 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$929 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$921 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$918 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$918 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$910 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$907 ($add).
Removed top 29 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$907 ($add).
Removed top 28 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$899 ($shiftx).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3160 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3159 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3158 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$3157 ($dffe).
Removed top 29 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333_Y.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$755_ADDR[31:0]$1389.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$756_ADDR[31:0]$1401.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$757_ADDR[31:0]$1413.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$758_ADDR[31:0]$1425.
Removed top 7 bits (of 8) from wire harness_nms_activation_banked.ack.
Removed top 56 bits (of 512) from wire harness_nms_activation_banked.rd_data_flat.
Removed top 24 bits (of 32) from wire harness_nms_activation_banked.$0\lfsr[31:0].
4.16. Executing PEEPOPT pass (run peephole optimizers).
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 155 unused cells and 176 unused wires.
<suppressed ~156 debug messages>
4.18. Executing SHARE pass (SAT-based resource sharing).
4.19. Executing TECHMAP pass (map to technology primitives).
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
4.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
4.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.22. Executing TECHMAP pass (map to technology primitives).
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
4.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.23. Executing TECHMAP pass (map to technology primitives).
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
4.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
4.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module harness_nms_activation_banked:
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1180 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1191 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$929 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1049 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1202 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1213 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1038 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1071 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1027 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1300 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$940 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1311 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1322 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1093 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1378 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1380 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1382 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$951 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1384 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1082 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$918 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1060 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$962 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$907 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$973 ($add).
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$973.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$907.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$962.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1060.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$918.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1082.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1384.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$951.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1382.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1380.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1378.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1093.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1322.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1311.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$940.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1300.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1027.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1071.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1038.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1213.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1202.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1049.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$929.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1191.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1180.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158.
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1158: $auto$alumacc.cc:548:replace_alu$3177
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1169: $auto$alumacc.cc:548:replace_alu$3180
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1180: $auto$alumacc.cc:548:replace_alu$3183
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1191: $auto$alumacc.cc:548:replace_alu$3186
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$929: $auto$alumacc.cc:548:replace_alu$3189
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1049: $auto$alumacc.cc:548:replace_alu$3192
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1202: $auto$alumacc.cc:548:replace_alu$3195
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1213: $auto$alumacc.cc:548:replace_alu$3198
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1038: $auto$alumacc.cc:548:replace_alu$3201
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1071: $auto$alumacc.cc:548:replace_alu$3204
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1027: $auto$alumacc.cc:548:replace_alu$3207
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1267: $auto$alumacc.cc:548:replace_alu$3210
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1278: $auto$alumacc.cc:548:replace_alu$3213
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1289: $auto$alumacc.cc:548:replace_alu$3216
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1300: $auto$alumacc.cc:548:replace_alu$3219
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$940: $auto$alumacc.cc:548:replace_alu$3222
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1311: $auto$alumacc.cc:548:replace_alu$3225
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1322: $auto$alumacc.cc:548:replace_alu$3228
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1333: $auto$alumacc.cc:548:replace_alu$3231
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1093: $auto$alumacc.cc:548:replace_alu$3234
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1378: $auto$alumacc.cc:548:replace_alu$3237
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1380: $auto$alumacc.cc:548:replace_alu$3240
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1382: $auto$alumacc.cc:548:replace_alu$3243
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$951: $auto$alumacc.cc:548:replace_alu$3246
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1384: $auto$alumacc.cc:548:replace_alu$3249
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1082: $auto$alumacc.cc:548:replace_alu$3252
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$918: $auto$alumacc.cc:548:replace_alu$3255
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1060: $auto$alumacc.cc:548:replace_alu$3258
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$962: $auto$alumacc.cc:548:replace_alu$3261
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1147: $auto$alumacc.cc:548:replace_alu$3264
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$907: $auto$alumacc.cc:548:replace_alu$3267
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$973: $auto$alumacc.cc:548:replace_alu$3270
created 32 $alu and 0 $macc cells.
4.25. Executing OPT pass (performing simple optimizations).
4.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 729 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~330 debug messages>
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 729 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
4.26. Executing MEMORY pass.
4.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing harness_nms_activation_banked.dut.GEN_BANK[0].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[1].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[2].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[3].mem write port 0.
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\dut.GEN_BANK[0].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[1].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_BANK[2].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[3].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 4 unused cells and 32 unused wires.
<suppressed ~5 debug messages>
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory harness_nms_activation_banked.dut.GEN_BANK[0].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[0].mem: $\dut.GEN_BANK[0].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[1].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[1].mem: $\dut.GEN_BANK[1].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[2].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[2].mem: $\dut.GEN_BANK[2].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[3].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[3].mem: $\dut.GEN_BANK[3].mem$rdreg[0]
<suppressed ~1802 debug messages>
4.29. Executing TECHMAP pass (map to technology primitives).
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
4.29.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~82 debug messages>
4.30. Executing OPT pass (performing simple optimizations).
4.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~273 debug messages>
4.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 772 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 771 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 770 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 44 unused cells and 515 unused wires.
<suppressed ~45 debug messages>
4.30.5. Finished fast OPT passes.
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.32. Executing OPT pass (performing simple optimizations).
4.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 726 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~283 debug messages>
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 726 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.9. Finished fast OPT passes. (There is nothing left to do.)
4.33. Executing TECHMAP pass (map to technology primitives).
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
4.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$79fc7abbb3333dbd5736999d565fd903198fb1eb\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$constmap:495c8dc1812f09f0b6f9ecda08e517e7538e08fd$paramod$2cd5a0fc12c713b111b124c014c3805512a5d620\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $not.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
No more expansions possible.
<suppressed ~2117 debug messages>
4.34. Executing OPT pass (performing simple optimizations).
4.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~2514 debug messages>
4.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 6486 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 5336 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 4856 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 4616 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 4520 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 4448 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~6114 debug messages>
Removed a total of 2038 cells.
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 681 unused cells and 3519 unused wires.
<suppressed ~682 debug messages>
4.34.5. Finished fast OPT passes.
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
4.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 3767 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.38. Executing TECHMAP pass (map to technology primitives).
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.38.2. Continuing TECHMAP pass.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
No more expansions possible.
<suppressed ~195 debug messages>
4.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
4.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in harness_nms_activation_banked.
4.42. Executing ATTRMVCP pass (move or copy attributes).
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 515 unused wires.
<suppressed ~1 debug messages>
4.44. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.45. Executing TECHMAP pass (map to technology primitives).
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
4.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.46. Executing ABC9 pass.
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.3. Executing PROC pass (convert processes to netlists).
4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$17542'.
Cleaned up 1 empty switch.
4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.
4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.
4.46.3.4. Executing PROC_INIT pass (extract init attributes).
4.46.3.5. Executing PROC_ARST pass (detect async resets in processes).
4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_EN[3:0]$17549
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_DATA[3:0]$17548
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_ADDR[3:0]$17547
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$17542'.
4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17525_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17526_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17527_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17528_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17529_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17530_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17531_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17532_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17533_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17534_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17535_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17536_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17537_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17538_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17539_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$17540_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$17542'.
4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
created $dff cell `$procdff$17593' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
created $dff cell `$procdff$17594' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$17541_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
created $dff cell `$procdff$17595' with positive edge clock.
4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$17567'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$17543'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$17542'.
Cleaned up 1 empty switch.
4.46.4. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module harness_nms_activation_banked.
Found 0 SCCs.
4.46.5. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.6. Executing TECHMAP pass (map to technology primitives).
4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~167 debug messages>
4.46.7. Executing OPT pass (performing simple optimizations).
4.46.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.
4.46.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
4.46.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.8. Executing TECHMAP pass (map to technology primitives).
4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
4.46.8.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~11 debug messages>
4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.13. Executing TECHMAP pass (map to technology primitives).
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.13.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~171 debug messages>
4.46.14. Executing OPT pass (performing simple optimizations).
4.46.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.46.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.46.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.15. Executing AIGMAP pass (map logic to AIG).
4.46.16. Executing AIGMAP pass (map logic to AIG).
Module harness_nms_activation_banked: replaced 2098 cells with 10426 new cells, skipped 1677 cells.
replaced 3 cell types:
554 $_MUX_
1420 $_OR_
124 $_XOR_
not replaced 6 cell types:
1168 $_AND_
390 $_NOT_
1 $scopeinfo
102 TRELLIS_FF
8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 4622 AND gates and 12224 wires from module `harness_nms_activation_banked' to a netlist network with 144 inputs and 129 outputs.
4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
4.46.16.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 144/ 129 and = 4497 lev = 51 (5.53) mem = 0.06 MB box = 8 bb = 8
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 144/ 129 and = 5685 lev = 23 (3.10) mem = 0.07 MB ch = 616 box = 8 bb = 8
ABC: cst = 0 cls = 506 lit = 616 unused = 4739 proof = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 5685. Ch = 506. Total mem = 0.99 MB. Peak cut mem = 0.14 MB.
ABC: P: Del = 4617.00. Ar = 3807.0. Edge = 4935. Cut = 84833. T = 0.01 sec
ABC: P: Del = 4532.00. Ar = 3714.0. Edge = 4788. Cut = 84164. T = 0.01 sec
ABC: P: Del = 4532.00. Ar = 2480.0. Edge = 5630. Cut = 140962. T = 0.02 sec
ABC: F: Del = 4532.00. Ar = 1882.0. Edge = 4918. Cut = 105365. T = 0.01 sec
ABC: A: Del = 4532.00. Ar = 1721.0. Edge = 4449. Cut = 98000. T = 0.02 sec
ABC: A: Del = 4532.00. Ar = 1703.0. Edge = 4444. Cut = 100247. T = 0.02 sec
ABC: Total time = 0.08 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 144/ 129 and = 4261 lev = 27 (3.23) mem = 0.06 MB box = 8 bb = 8
ABC: Mapping (K=7) : lut = 1045 edge = 4214 lev = 9 (1.30) levB = 9 mem = 0.04 MB
ABC: LUT = 1045 : 2=85 8.1 % 3=179 17.1 % 4=514 49.2 % 5=188 18.0 % 6=42 4.0 % 7=37 3.5 % Ave = 4.03
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.07 sec
ABC: + time
ABC: elapse: 0.68 seconds, total: 0.68 seconds
4.46.16.6. Executing AIGER frontend.
<suppressed ~10 debug messages>
Removed 6072 unused cells and 6388 unused wires.
4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 1045
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 8
ABC RESULTS: input signals: 25
ABC RESULTS: output signals: 40
<suppressed ~546 debug messages>
Removing temp directory.
4.46.17. Executing TECHMAP pass (map to technology primitives).
4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
4.46.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~23 debug messages>
Removed 25 unused cells and 13680 unused wires.
4.47. Executing TECHMAP pass (map to technology primitives).
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
4.47.2. Continuing TECHMAP pass.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c$lut for cells of type $lut.
Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6$lut for cells of type $lut.
Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514$lut for cells of type $lut.
Using template $paramod$70139e61b94fc9df815c97d49d232cd9e20aa04e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010101 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$7c10da2741b95c679da643f74e8aa9472416631e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$4de58d0b39c40b534f5b79ec3ab08582e2e15ae3$lut for cells of type $lut.
Using template $paramod$99ba7e80fc5077f9a2c5f62d113d8e3ac97ab48f$lut for cells of type $lut.
Using template $paramod$5beb5a5307ad68a081da9451d69410e739b0d8e8$lut for cells of type $lut.
Using template $paramod$4bf0a2b4bf08f3dd5c82169a2a0d9ff5af523709$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb$lut for cells of type $lut.
Using template $paramod$2bde02b8b9e7d4618088fbf4dd7d45ed8df60d20$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
Using template $paramod$ff712943954db7d88d92c25ed924bda7803f5396$lut for cells of type $lut.
Using template $paramod$4440f25cf172665494cf9c9e87096623181eba7a$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0$lut for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602$lut for cells of type $lut.
Using template $paramod$18ad3de3968c5ce716c12250162d2bab5b105642$lut for cells of type $lut.
Using template $paramod$d65cf6bfeb53a6d070b30473d781c3c6332b3889$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366$lut for cells of type $lut.
Using template $paramod$ad4e5430959f8049278ae2a67344bcf27fb0e38b$lut for cells of type $lut.
Using template $paramod$e75a64b32945ef9ce22be23ef3e6054e0adbafe0$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146$lut for cells of type $lut.
Using template $paramod$6842b8b2a2a38d0fdb35de972b4ce1a464745b17$lut for cells of type $lut.
Using template $paramod$f6e6717391ec9a1cbe38997b8a3b6c11e8abbc85$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111$lut for cells of type $lut.
Using template $paramod$be0d52b4adde38396aa8d181484c99080ee57661$lut for cells of type $lut.
Using template $paramod$8ff99ede53974a864c6332a7dd06f69eb3a45d17$lut for cells of type $lut.
Using template $paramod$adee7bb43ee3a3b0f8309c2b93b6c71f8f8a135c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
Using template $paramod$f6e433380915940dbf9c6bdc43a69c04657519e4$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67$lut for cells of type $lut.
Using template $paramod$99546ee11a916b115686976f4cdde498b5bd3621$lut for cells of type $lut.
Using template $paramod$d58242a4d834586ae74b4a159ac15b073ed6930a$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut.
Using template $paramod$8c2c1e59c8876a3c2b20cc33cb8585da498e9286$lut for cells of type $lut.
Using template $paramod$7ed32d8f92905118de993096479955c8ad02068d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut.
Using template $paramod$34e9fa1d25f4c105f358cf716fd5df0eae34726b$lut for cells of type $lut.
Using template $paramod$91f78a6f0aec6749f00fd8881bb164016ba22465$lut for cells of type $lut.
Using template $paramod$8e224a63a74b6daf8fc2e441cb0688a65e7a4073$lut for cells of type $lut.
Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9$lut for cells of type $lut.
Using template $paramod$f8c95f1db01b45869ea1c725fd241c12476ca257$lut for cells of type $lut.
Using template $paramod$a894de351e53d7e73e2e99ab40b3e5bfd9247d08$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f$lut for cells of type $lut.
Using template $paramod$5cdd6c45be1730619480254670476c4ed2df25cf$lut for cells of type $lut.
Using template $paramod$f40957607749706d7aef426e2d36c4dfe9d0afe6$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$316f378fe0a4aea2766c9f492a57cce43ee2b261$lut for cells of type $lut.
Using template $paramod$31b4ebd1981d715dd0ebbd25b08832bf1be3a22f$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e$lut for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476$lut for cells of type $lut.
Using template $paramod$c145f84e6b9aba2d7bbf6cd4a827e636b5fa3ae0$lut for cells of type $lut.
Using template $paramod$2464a83c5fa0756567dcd6fc332bd7e12d602fa5$lut for cells of type $lut.
Using template $paramod$c6386220a7a54c5098c7b9e80f8ba5bc42999efa$lut for cells of type $lut.
Using template $paramod$bc260dd524b5c5e85379bcf61d6b7381cee0bede$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
Using template $paramod$e6a85936eaa7a3305cad23523bc966430b038ac6$lut for cells of type $lut.
Using template $paramod$fe1ec7d7c9a7a665ba4e9eab2eb62acaa32de27d$lut for cells of type $lut.
Using template $paramod$1ef7e0d3a5353ce3a849812c226c3e9f8c0dc5ea$lut for cells of type $lut.
Using template $paramod$01d1badebdb17f5d737fb2d89d208cb7f0ffab68$lut for cells of type $lut.
Using template $paramod$640e10d7f9727389f81b6b069694604347b96216$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336$lut for cells of type $lut.
Using template $paramod$a56a39c0f6a5a7dc6beed165205ecc9aaf916f10$lut for cells of type $lut.
Using template $paramod$6b7b6dcc6025c4418d933c05b8ad409f9a39b293$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$8c0aa4283e004d7e549a2fa42300002224408629$lut for cells of type $lut.
Using template $paramod$95a9b71ad4cf3b95a0a448ddd8414cc53c2076c6$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea$lut for cells of type $lut.
Using template $paramod$a7e97ee24f37fdb6f32da1dc32004a95c94c4923$lut for cells of type $lut.
Using template $paramod$c4fd8ed8a3f2fa4b44e4f56ed8c119b29df21157$lut for cells of type $lut.
Using template $paramod$faca62a87ed5a4db787ab8f942484ecddc722116$lut for cells of type $lut.
Using template $paramod$92922acd4af5fcdb810a76e112db148d04d4cd9a$lut for cells of type $lut.
Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0$lut for cells of type $lut.
Using template $paramod$6786213342169f46cbca44284df298da11653c08$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89$lut for cells of type $lut.
Using template $paramod$14c3c060d7c65589530e332c915e3e8c18083c1f$lut for cells of type $lut.
Using template $paramod$9dbe36982f6b8ca20db05cfcd5650178f13179f3$lut for cells of type $lut.
Using template $paramod$024bdf06dd4dc504e197f6fa695bfaf9eb9873a8$lut for cells of type $lut.
Using template $paramod$c9ac2be49a400c6b773aa5b957bf963d13cda23b$lut for cells of type $lut.
Using template $paramod$3bcdd2bd63391fcd2716e3508058516cabb6445c$lut for cells of type $lut.
Using template $paramod$52c9553941e16376dac81a87101264bd52a1cb06$lut for cells of type $lut.
Using template $paramod$e404657311533b75656f9839634336e7afd6e2ec$lut for cells of type $lut.
Using template $paramod$4644b082e095f76d14f260ebce753a03cdd93c87$lut for cells of type $lut.
Using template $paramod$70ee1c32bf59574bb0876122a9b7dc66d9084a99$lut for cells of type $lut.
Using template $paramod$dd9047df8afc1543e47f4200533bb1ad5f56e5fc$lut for cells of type $lut.
Using template $paramod$436f5b2a701f46b4f2c40432561ff700e1d0a2c0$lut for cells of type $lut.
Using template $paramod$d42ed43f2b7059cb68d537b427953501442b9d3e$lut for cells of type $lut.
Using template $paramod$771dfc8c7366921c8db1bbddc41f23f7948f1330$lut for cells of type $lut.
Using template $paramod$67537c0f32e810720d794df252a58924033186d8$lut for cells of type $lut.
Using template $paramod$0169eb4949898e841c25bb571c240875d67e3d25$lut for cells of type $lut.
Using template $paramod$e496e1ebaf8968b0448781d0c7b4fab8e5e7c961$lut for cells of type $lut.
Using template $paramod$9ac2c92f3a82ed012dffb0da642230f52f6da074$lut for cells of type $lut.
Using template $paramod$4763ec711636c05abb61ae476b01b0c2cdbf0ed0$lut for cells of type $lut.
Using template $paramod$7253e5fc2a7d83e984df5eea7a36ff218e740e65$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc$lut for cells of type $lut.
Using template $paramod$f8fac4090406134f9dc7d61926209d22431f2864$lut for cells of type $lut.
Using template $paramod$e2e912974c5c1b33f627a119acb537034c5914b5$lut for cells of type $lut.
Using template $paramod$ba018f3c1db23c1fcd588964e4ab8c0cb933066c$lut for cells of type $lut.
Using template $paramod$150ef1cc573a226e51e94d04ec24cdad3a5c60a3$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
Using template $paramod$0b6f7aee816c7487d009e2f17e0e7e7021bdaea8$lut for cells of type $lut.
Using template $paramod$d8a851edf04260eb28aaaf93d5a60542d6e72d32$lut for cells of type $lut.
Using template $paramod$912cf622adc9bd99771a3792f165476315a967eb$lut for cells of type $lut.
Using template $paramod$7b262993d3e336593550c8d6c67d205a5a563bc9$lut for cells of type $lut.
Using template $paramod$c59707ab08318bfd58176cb3e6246f3aa3ea4b9d$lut for cells of type $lut.
Using template $paramod$a4f0b4ecc1d1e48ac1002e77e81103ea4555b2b4$lut for cells of type $lut.
Using template $paramod$e5cf5e6a6d0ba844a5e20d53ccf87490cf030b08$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$80d119b846de9eb67cf123b4d4c105633f15e6f8$lut for cells of type $lut.
Using template $paramod$e00d03686849cf5e50e9f0c13f0f78958ff5e7ae$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2$lut for cells of type $lut.
Using template $paramod$e035640c5400ebc6b1db9018dbf7e784b8617ead$lut for cells of type $lut.
Using template $paramod$0d5e420ccfc2dddc13533c0817d1e17e68a2c136$lut for cells of type $lut.
Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b$lut for cells of type $lut.
Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d$lut for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575$lut for cells of type $lut.
Using template $paramod$a1cfe99817bd6d57a83efd5e1c3fc26a743b692f$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b$lut for cells of type $lut.
Using template $paramod$22a17f102d8eb29f9e3f67afc5da9acc7c1e8867$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d$lut for cells of type $lut.
Using template $paramod$293464f994386c0554e4c5ea1c2666f7f1be997b$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75$lut for cells of type $lut.
Using template $paramod$344fdd08c01615c9d0d358fb7cafd6a9fdb44cb0$lut for cells of type $lut.
Using template $paramod$d71b174febd328244d15e5a4bbdf51181cbf5883$lut for cells of type $lut.
Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037$lut for cells of type $lut.
Using template $paramod$da0cb6493c2e027d83a205b77890b4e04f75e457$lut for cells of type $lut.
Using template $paramod$660a72f63d46a844bb0ddab189b65027c878fc6b$lut for cells of type $lut.
Using template $paramod$12ef31446fd6f1fa9ed73d48ce76ac19cf9ea31d$lut for cells of type $lut.
Using template $paramod$d05a3bbccbc409a20e2454567b47cde24c5fbaff$lut for cells of type $lut.
Using template $paramod$cd4e8cfa0a9a21169cc6b9b62e2a43fc1442ddc1$lut for cells of type $lut.
Using template $paramod$cabe1255f99912a50f8be6297337467146b8a928$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$b20b44b7ecee5be956e2b152bbe403b0db4146a7$lut for cells of type $lut.
Using template $paramod$52341f6017db69268706bfd5a5ad5f208704cdde$lut for cells of type $lut.
Using template $paramod$5858ed474fc0c464e0ca49e0c518902abae33077$lut for cells of type $lut.
Using template $paramod$85b4ba175592613a542d4add18c5edce24285b1b$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$17b153d14b41e603006522fbb750416cb9a5d1e2$lut for cells of type $lut.
Using template $paramod$bd69e3c0d2d96276ad348367b782c97ebfbc49e8$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163$lut for cells of type $lut.
Using template $paramod$8eb9acb53b9a2a4286f94cea69fcf759806384fc$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db$lut for cells of type $lut.
Using template $paramod$be0bb5404e584419b3509538c513c84717bf10c4$lut for cells of type $lut.
Using template $paramod$4a5cb9a6822416135c3ccf2a28bcf23a857f7920$lut for cells of type $lut.
Using template $paramod$14cd598b0991520a75cb7d594d92ff21d9cbe499$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2$lut for cells of type $lut.
Using template $paramod$09b01244f3a39f3296728bdce9fc5a763ddd081b$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c$lut for cells of type $lut.
Using template $paramod$88d94c4769121c16d1c13d55d3930427fe66580e$lut for cells of type $lut.
Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b$lut for cells of type $lut.
Using template $paramod$0a07dcad1d0abe026716861fdbb185ec11e2ae9c$lut for cells of type $lut.
Using template $paramod$78a6bcc0ecc911dbb88618a1e3d5c3dd94de986a$lut for cells of type $lut.
Using template $paramod$44af68a5b1f9e5de124d9b6b621c2b31b07d9b48$lut for cells of type $lut.
Using template $paramod$80c57506599e789c4765758c4a3d41a728771aaf$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730$lut for cells of type $lut.
Using template $paramod$aa569d89e9c8462354297a37f09bc519483c7133$lut for cells of type $lut.
Using template $paramod$68eab1cc6901dc28cf976ab6b8c4942e68212063$lut for cells of type $lut.
Using template $paramod$091d2b842bd2cdaa071dc3a4f18c7b64d81ea902$lut for cells of type $lut.
Using template $paramod$b83a741bc8c97ed8f652e3e9bfabc38e9f5bd5f9$lut for cells of type $lut.
Using template $paramod$f708b7057af81b2f8c1afe1f7353a41e38939997$lut for cells of type $lut.
Using template $paramod$144be6f575ecc4be7ff83d3a352b1059ce5ade9a$lut for cells of type $lut.
Using template $paramod$c4a97cf0b46779df8741d618ac94cb76d112af85$lut for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$979794232a1b12010187e90e68ca43f80b43cf7f$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32$lut for cells of type $lut.
Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87$lut for cells of type $lut.
Using template $paramod$e072fe3ca6403414a47480bcf08a558c05201da4$lut for cells of type $lut.
Using template $paramod$e0bb302abce11ed2533e814e32f4feeac6ffe4e2$lut for cells of type $lut.
Using template $paramod$58ec3c2aac760defbce0d44018162bde3065d820$lut for cells of type $lut.
Using template $paramod$41f83160fd9ddddeafa9bdd425e3bc0fce6db68c$lut for cells of type $lut.
Using template $paramod$b1fd6c9319078b96b28a79dcb88571e7a653f001$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52$lut for cells of type $lut.
Using template $paramod$c25d2e475b8ee8c57a7b4afc2cbee88797c20177$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4$lut for cells of type $lut.
Using template $paramod$a1c549668590c836889cc563312a3a4d1f1b6e6b$lut for cells of type $lut.
Using template $paramod$0e29f0164a2ad363572ce02be0688ae5b861bd5c$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$73dc5c0a4a40df28594f928fdbecb669d67e7800$lut for cells of type $lut.
Using template $paramod$68519e2903a6f67431388c1c4052cdd6f7d01102$lut for cells of type $lut.
Using template $paramod$0189d933eed523b159b35d60915e80e53d803bc2$lut for cells of type $lut.
Using template $paramod$55c5aeef8decf5e0c0eb5302796f5cf51ce4d871$lut for cells of type $lut.
Using template $paramod$61699a6f08deb5824a25f71ca99e9870d20b8b3d$lut for cells of type $lut.
Using template $paramod$cfb358f856b2bbc5111d7ab620523d1162e2c203$lut for cells of type $lut.
Using template $paramod$52f521ea1f86a0ec060d6e289c8b42d90737a6cd$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut.
Using template $paramod$e6a4aac14b366f7770f6afc50867b3b8176ebb96$lut for cells of type $lut.
Using template $paramod$6665b39ceac26e0ab2d4c34094b2005de33923b9$lut for cells of type $lut.
Using template $paramod$4ac7e64f31a3c0de225e9c9b5cc7397a41149e40$lut for cells of type $lut.
Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut.
Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c$lut for cells of type $lut.
Using template $paramod$1991535f046958f08b1b21aaa00798da301e3910$lut for cells of type $lut.
Using template $paramod$9fbb9489db5be7c374c97304498ed6ae7a9caa09$lut for cells of type $lut.
Using template $paramod$c56c1ae839fab11d81c8aeefe5ce4707e798b248$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288$lut for cells of type $lut.
Using template $paramod$71780946553cf4f012cf430f27c1f53f2aea690e$lut for cells of type $lut.
Using template $paramod$96f6b4094ea1411d7c9aea8d540e6f5abc44a64f$lut for cells of type $lut.
Using template $paramod$9c8034312613383a60fd318871077c7959d5deee$lut for cells of type $lut.
Using template $paramod$b2794a3e8b357e5c64aa940489bf9fcc708dab84$lut for cells of type $lut.
Using template $paramod$946e4ba6cc6d5f643745e6b56089375901ce6d2c$lut for cells of type $lut.
Using template $paramod$7da97d7abff86da1fd188e66d8e751501206dab4$lut for cells of type $lut.
Using template $paramod$2a2420bf2df78ddd7f890007a54291794d05b62e$lut for cells of type $lut.
Using template $paramod$0eb24ed179a6f2d1f1d565c9c5e6aeda108280ac$lut for cells of type $lut.
No more expansions possible.
<suppressed ~4653 debug messages>
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in harness_nms_activation_banked.
Optimizing lut $abc$38608$lut$aiger$o111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger$o98.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger$o98.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger$o114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$4006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$3361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o77.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger$o77.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o77.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger$o77.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$3274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$4377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$4344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$4270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$2559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o98.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$3270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$4099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$4085.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3693.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$2408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$1522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger$o114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$3651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$4006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$2852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$2356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$3599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$1342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$3309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$38608$lut$aiger38607$1833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$38608$lut$aiger38607$3973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$38608$lut$aiger38607$1839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger38607$787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger$o76.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$38632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$38608$lut$aiger$o111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Removed 0 unused cells and 2721 unused wires.
4.49. Executing AUTONAME pass.
Renamed 3825 objects in module harness_nms_activation_banked.
<suppressed ~3825 debug messages>
4.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `harness_nms_activation_banked'. Setting top module to harness_nms_activation_banked.
4.50.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
4.50.2. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Removed 0 unused modules.
4.51. Printing statistics.
=== harness_nms_activation_banked ===
+----------Local Count, excluding submodules.
|
1624 wires
5118 wire bits
1624 public wires
5118 public wire bits
4 ports
18 port bits
1 cells
1 $scopeinfo
2301 submodules
153 L6MUX21
1618 LUT4
420 PFUMX
8 TRELLIS_DPR16X4
102 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
1 harness_nms_activation_banked
+----------Count including submodules.
|
1624 wires
5118 wire bits
1624 public wires
5118 public wire bits
4 ports
18 port bits
- memories
- memory bits
- processes
1 cells
1 $scopeinfo
2301 submodules
153 L6MUX21
1618 LUT4
420 PFUMX
8 TRELLIS_DPR16X4
102 TRELLIS_FF
4.52. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.53. Executing JSON backend.
Warnings: 12 unique messages, 22 total
End of script. Logfile hash: 5a6470f6da, time: 1.50s, user: 0.83s, system: 0.03s, MEM: 125.91 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 44% 1x abc9_exe (0 sec), 12% 22x read_verilog (0 sec), ...
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