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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Running command `read_verilog hardware/v2/nms/rtl/nms_activation_banked.v hardware/v2/nms/synthesis/harness_nms_activation_banked.v; chparam -set N_SLOTS 4 -set N_BANKS 4 -set MAX_TILES 16 harness_nms_activation_banked; synth_ecp5 -json hardware/v2/nms/synthesis/act_bank_n4_b4/top.json -top harness_nms_activation_banked' --
1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/rtl/nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_activation_banked.v
Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_activation_banked.v' to AST representation.
Generating RTLIL representation for module `\harness_nms_activation_banked'.
Successfully finished Verilog frontend.
Parameter \N_SLOTS = 4
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_activation_banked'.
Parameter \N_SLOTS = 4
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$8325aece989b4f042a1e20a8292c26fe95972a9c\harness_nms_activation_banked'.
4. Executing SYNTH_LATTICE pass.
4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
4.3. Executing HIERARCHY pass (managing design hierarchy).
4.3.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: \nms_activation_banked
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 4
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_banked'.
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 4
Parameter \N_BANKS = 4
Parameter \MAX_TILES = 16
Generating RTLIL representation for module `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked'.
Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
4.3.3. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked
4.3.4. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Used module: $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked
Removing unused module `\nms_activation_banked'.
Removed 1 unused modules.
4.4. Executing PROC pass (convert processes to netlists).
4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443 in module harness_nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448 in module harness_nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Removed 32 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Marked 68 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719 in module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
Removed a total of 36 dead cases.
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 16 redundant assignments.
Promoted 117 assignments to connections.
4.4.4. Executing PROC_INIT pass (extract init attributes).
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~87 debug messages>
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
1/1: $0\lfsr[31:0]
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
1/3: $0\chk[7:0]
2/3: $1\chk_next[7:0]
3/3: $1\k[31:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$714_DATA[63:0]$1100
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$713_DATA[63:0]$1097
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$712_DATA[63:0]$1094
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089'.
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$711_DATA[63:0]$1091
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1088'.
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1087'.
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1086'.
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1085'.
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
1/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1082
2/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_DATA[63:0]$1081
3/4: $1$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_ADDR[31:0]$1080
4/4: $0\GEN_BANK[3].rd_data_r[63:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
1/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1070
2/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_DATA[63:0]$1069
3/4: $1$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_ADDR[31:0]$1068
4/4: $0\GEN_BANK[2].rd_data_r[63:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
1/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1058
2/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_DATA[63:0]$1057
3/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_ADDR[31:0]$1056
4/4: $0\GEN_BANK[1].rd_data_r[63:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
1/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1046
2/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_DATA[63:0]$1045
3/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_ADDR[31:0]$1044
4/4: $0\GEN_BANK[0].rd_data_r[63:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
1/20: $6\i[31:0]
2/20: $0\slot_bank_stage1[3][1:0]
3/20: $0\slot_bank_stage1[2][1:0]
4/20: $0\slot_bank_stage1[1][1:0]
5/20: $0\slot_bank_stage1[0][1:0]
6/20: $0\ack[3:0]
7/20: $0\ack_stage1[3:0]
8/20: $2\b[31:0]
9/20: $0\bank_rd_addr_stage1[3][1:0]
10/20: $0\bank_rd_en_stage1[3][0:0]
11/20: $0\bank_rd_addr_stage1[2][1:0]
12/20: $0\bank_rd_en_stage1[2][0:0]
13/20: $0\bank_rd_addr_stage1[1][1:0]
14/20: $0\bank_rd_en_stage1[1][0:0]
15/20: $0\bank_rd_addr_stage1[0][1:0]
16/20: $0\bank_rd_en_stage1[0][0:0]
17/20: $0\rr_ptr[3][1:0]
18/20: $0\rr_ptr[2][1:0]
19/20: $0\rr_ptr[1][1:0]
20/20: $0\rr_ptr[0][1:0]
Creating decoders for process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
1/148: $16\ack_comb[3:0] [3]
2/148: $19\ack_comb[2:2]
3/148: $18\ack_comb[1:1]
4/148: $17\ack_comb[0:0]
5/148: $4\i[31:0]
6/148: $16\ack_comb[3:0] [2]
7/148: $16\ack_comb[3:0] [1]
8/148: $16\ack_comb[3:0] [0]
9/148: $20\ack_comb[3:3]
10/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1011
11/148: $4\win_first[3][1:0]
12/148: $4\win_tile_idx[3][3:0]
13/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_DATA[3:0]$1010
14/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$710_ADDR[1:0]$1009
15/148: $4\win_valid[3][0:0]
16/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$709_DATA[1:0]$1003
17/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$1000
18/148: $3\win_first[3][1:0]
19/148: $3\win_tile_idx[3][3:0]
20/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_DATA[3:0]$999
21/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$708_ADDR[1:0]$998
22/148: $3\win_valid[3][0:0]
23/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$707_DATA[1:0]$992
24/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$989
25/148: $2\win_first[3][1:0]
26/148: $2\win_tile_idx[3][3:0]
27/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_DATA[3:0]$988
28/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$706_ADDR[1:0]$987
29/148: $2\win_valid[3][0:0]
30/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$705_DATA[1:0]$981
31/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$978
32/148: $1\win_first[3][1:0]
33/148: $1\win_tile_idx[3][3:0]
34/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_DATA[3:0]$977
35/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$704_ADDR[1:0]$976
36/148: $1\win_valid[3][0:0]
37/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$703_DATA[1:0]$970
38/148: $11\ack_comb[3:0] [3]
39/148: $14\ack_comb[2:2]
40/148: $13\ack_comb[1:1]
41/148: $12\ack_comb[0:0]
42/148: $3\i[31:0]
43/148: $11\ack_comb[3:0] [2]
44/148: $11\ack_comb[3:0] [1]
45/148: $11\ack_comb[3:0] [0]
46/148: $15\ack_comb[3:3]
47/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$951
48/148: $4\win_first[2][1:0]
49/148: $4\win_tile_idx[2][3:0]
50/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_DATA[3:0]$950
51/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$702_ADDR[1:0]$949
52/148: $4\win_valid[2][0:0]
53/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$701_DATA[1:0]$943
54/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$940
55/148: $3\win_first[2][1:0]
56/148: $3\win_tile_idx[2][3:0]
57/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_DATA[3:0]$939
58/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$700_ADDR[1:0]$938
59/148: $3\win_valid[2][0:0]
60/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$699_DATA[1:0]$932
61/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$929
62/148: $2\win_first[2][1:0]
63/148: $2\win_tile_idx[2][3:0]
64/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_DATA[3:0]$928
65/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$698_ADDR[1:0]$927
66/148: $2\win_valid[2][0:0]
67/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$697_DATA[1:0]$921
68/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$918
69/148: $1\win_first[2][1:0]
70/148: $1\win_tile_idx[2][3:0]
71/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_DATA[3:0]$917
72/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$696_ADDR[1:0]$916
73/148: $1\win_valid[2][0:0]
74/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$695_DATA[1:0]$910
75/148: $6\ack_comb[3:0] [3]
76/148: $9\ack_comb[2:2]
77/148: $8\ack_comb[1:1]
78/148: $7\ack_comb[0:0]
79/148: $2\i[31:0]
80/148: $6\ack_comb[3:0] [2]
81/148: $6\ack_comb[3:0] [1]
82/148: $6\ack_comb[3:0] [0]
83/148: $10\ack_comb[3:3]
84/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$891
85/148: $4\win_first[1][1:0]
86/148: $4\win_tile_idx[1][3:0]
87/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_DATA[3:0]$890
88/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$694_ADDR[1:0]$889
89/148: $4\win_valid[1][0:0]
90/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$693_DATA[1:0]$883
91/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$880
92/148: $3\win_first[1][1:0]
93/148: $3\win_tile_idx[1][3:0]
94/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_DATA[3:0]$879
95/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$692_ADDR[1:0]$878
96/148: $3\win_valid[1][0:0]
97/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$691_DATA[1:0]$872
98/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$869
99/148: $2\win_first[1][1:0]
100/148: $2\win_tile_idx[1][3:0]
101/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_DATA[3:0]$868
102/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$690_ADDR[1:0]$867
103/148: $2\win_valid[1][0:0]
104/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$689_DATA[1:0]$861
105/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$858
106/148: $1\win_first[1][1:0]
107/148: $1\win_tile_idx[1][3:0]
108/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_DATA[3:0]$857
109/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$688_ADDR[1:0]$856
110/148: $1\win_valid[1][0:0]
111/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$687_DATA[1:0]$850
112/148: $1\ack_comb[3:0] [3]
113/148: $4\ack_comb[2:2]
114/148: $3\ack_comb[1:1]
115/148: $2\ack_comb[0:0]
116/148: $1\i[31:0]
117/148: $1\ack_comb[3:0] [2]
118/148: $1\ack_comb[3:0] [1]
119/148: $1\ack_comb[3:0] [0]
120/148: $5\ack_comb[3:3]
121/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$831
122/148: $4\win_first[0][1:0]
123/148: $4\win_tile_idx[0][3:0]
124/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_DATA[3:0]$830
125/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$686_ADDR[1:0]$829
126/148: $4\win_valid[0][0:0]
127/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$685_DATA[1:0]$823
128/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$820
129/148: $3\win_first[0][1:0]
130/148: $3\win_tile_idx[0][3:0]
131/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$819
132/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_ADDR[1:0]$818
133/148: $3\win_valid[0][0:0]
134/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$683_DATA[1:0]$812
135/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_DATA[3:0]$809
136/148: $2\win_first[0][1:0]
137/148: $2\win_tile_idx[0][3:0]
138/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_DATA[3:0]$808
139/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_ADDR[1:0]$807
140/148: $2\win_valid[0][0:0]
141/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$681_DATA[1:0]$801
142/148: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_DATA[3:0]$798
143/148: $1\win_first[0][1:0]
144/148: $1\win_tile_idx[0][3:0]
145/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_DATA[3:0]$797
146/148: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_ADDR[1:0]$796
147/148: $1\win_valid[0][0:0]
148/148: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$679_DATA[1:0]$790
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$714_DATA' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$713_DATA' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$712_DATA' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$711_DATA' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_data_reg[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1088'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_data_reg[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1087'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_data_reg[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1086'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_data_reg[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1085'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\b' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\i' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\ack_comb' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\scan_i' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\cand' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_tile_idx[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_tile_idx[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_tile_idx[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_tile_idx[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_bank[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_bank[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_bank[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\req_bank[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_comb[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_comb[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_comb[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_comb[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_valid[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_valid[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_valid[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_valid[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_tile_idx[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_tile_idx[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_tile_idx[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_tile_idx[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_first[0]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_first[1]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_first[2]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
No latch inferred for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\win_first[3]' from process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\harness_nms_activation_banked.\lfsr' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
created $dff cell `$procdff$1846' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\k' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$1847' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$1848' with positive edge clock.
Creating register for signal `\harness_nms_activation_banked.\chk_next' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
created $dff cell `$procdff$1849' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\GEN_BANK[3].rd_data_r' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
created $dff cell `$procdff$1850' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_ADDR' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
created $dff cell `$procdff$1851' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_DATA' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
created $dff cell `$procdff$1852' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
created $dff cell `$procdff$1853' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\GEN_BANK[2].rd_data_r' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
created $dff cell `$procdff$1854' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_ADDR' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
created $dff cell `$procdff$1855' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_DATA' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
created $dff cell `$procdff$1856' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
created $dff cell `$procdff$1857' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\GEN_BANK[1].rd_data_r' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
created $dff cell `$procdff$1858' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_ADDR' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
created $dff cell `$procdff$1859' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_DATA' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
created $dff cell `$procdff$1860' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
created $dff cell `$procdff$1861' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\GEN_BANK[0].rd_data_r' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
created $dff cell `$procdff$1862' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_ADDR' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
created $dff cell `$procdff$1863' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_DATA' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
created $dff cell `$procdff$1864' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
created $dff cell `$procdff$1865' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\b' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1866' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\i' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1867' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\ack' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1868' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\ack_stage1' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1869' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\rr_ptr[0]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1870' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\rr_ptr[1]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1871' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\rr_ptr[2]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1872' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\rr_ptr[3]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1873' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_en_stage1[0]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1874' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_en_stage1[1]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1875' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_en_stage1[2]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1876' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_en_stage1[3]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1877' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_addr_stage1[0]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1878' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_addr_stage1[1]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1879' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_addr_stage1[2]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1880' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\bank_rd_addr_stage1[3]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1881' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_stage1[0]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1882' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_stage1[1]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1883' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_stage1[2]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1884' with positive edge clock.
Creating register for signal `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.\slot_bank_stage1[3]' using process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
created $dff cell `$procdff$1885' with positive edge clock.
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
Found and cleaned up 1 empty switch in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1098'.
Found and cleaned up 1 empty switch in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1095'.
Found and cleaned up 1 empty switch in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1092'.
Found and cleaned up 1 empty switch in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$1089'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1088'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1087'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1086'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$1085'.
Found and cleaned up 2 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1076'.
Found and cleaned up 2 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1064'.
Found and cleaned up 2 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1052'.
Found and cleaned up 2 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$1040'.
Found and cleaned up 5 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$1028'.
Found and cleaned up 68 empty switches in `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
Removing empty process `$paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$719'.
Cleaned up 87 empty switches.
4.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~1 debug messages>
Optimizing module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
<suppressed ~56 debug messages>
4.5. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Checking module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked...
Warning: Drivers conflicting with a constant 1'0 driver:
port Q[0] of cell $procdff$1867 ($dff)
port Q[1] of cell $procdff$1867 ($dff)
port Q[3] of cell $procdff$1867 ($dff)
port Q[4] of cell $procdff$1867 ($dff)
port Q[5] of cell $procdff$1867 ($dff)
port Q[6] of cell $procdff$1867 ($dff)
port Q[7] of cell $procdff$1867 ($dff)
port Q[8] of cell $procdff$1867 ($dff)
port Q[9] of cell $procdff$1867 ($dff)
port Q[10] of cell $procdff$1867 ($dff)
port Q[11] of cell $procdff$1867 ($dff)
port Q[12] of cell $procdff$1867 ($dff)
port Q[13] of cell $procdff$1867 ($dff)
port Q[14] of cell $procdff$1867 ($dff)
port Q[15] of cell $procdff$1867 ($dff)
port Q[16] of cell $procdff$1867 ($dff)
port Q[17] of cell $procdff$1867 ($dff)
port Q[18] of cell $procdff$1867 ($dff)
port Q[19] of cell $procdff$1867 ($dff)
port Q[20] of cell $procdff$1867 ($dff)
port Q[21] of cell $procdff$1867 ($dff)
port Q[22] of cell $procdff$1867 ($dff)
port Q[23] of cell $procdff$1867 ($dff)
port Q[24] of cell $procdff$1867 ($dff)
port Q[25] of cell $procdff$1867 ($dff)
port Q[26] of cell $procdff$1867 ($dff)
port Q[27] of cell $procdff$1867 ($dff)
port Q[28] of cell $procdff$1867 ($dff)
port Q[29] of cell $procdff$1867 ($dff)
port Q[30] of cell $procdff$1867 ($dff)
port Q[31] of cell $procdff$1867 ($dff)
port Q[0] of cell $procdff$1866 ($dff)
port Q[1] of cell $procdff$1866 ($dff)
port Q[3] of cell $procdff$1866 ($dff)
port Q[4] of cell $procdff$1866 ($dff)
port Q[5] of cell $procdff$1866 ($dff)
port Q[6] of cell $procdff$1866 ($dff)
port Q[7] of cell $procdff$1866 ($dff)
port Q[8] of cell $procdff$1866 ($dff)
port Q[9] of cell $procdff$1866 ($dff)
port Q[10] of cell $procdff$1866 ($dff)
port Q[11] of cell $procdff$1866 ($dff)
port Q[12] of cell $procdff$1866 ($dff)
port Q[13] of cell $procdff$1866 ($dff)
port Q[14] of cell $procdff$1866 ($dff)
port Q[15] of cell $procdff$1866 ($dff)
port Q[16] of cell $procdff$1866 ($dff)
port Q[17] of cell $procdff$1866 ($dff)
port Q[18] of cell $procdff$1866 ($dff)
port Q[19] of cell $procdff$1866 ($dff)
port Q[20] of cell $procdff$1866 ($dff)
port Q[21] of cell $procdff$1866 ($dff)
port Q[22] of cell $procdff$1866 ($dff)
port Q[23] of cell $procdff$1866 ($dff)
port Q[24] of cell $procdff$1866 ($dff)
port Q[25] of cell $procdff$1866 ($dff)
port Q[26] of cell $procdff$1866 ($dff)
port Q[27] of cell $procdff$1866 ($dff)
port Q[28] of cell $procdff$1866 ($dff)
port Q[29] of cell $procdff$1866 ($dff)
port Q[30] of cell $procdff$1866 ($dff)
port Q[31] of cell $procdff$1866 ($dff)
Warning: Drivers conflicting with a constant 1'1 driver:
port Q[2] of cell $procdff$1867 ($dff)
port Q[2] of cell $procdff$1866 ($dff)
Found and reported 2 problems.
4.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$1de78acdffab0a6e74eb5bd854df9bf8e2901c69\nms_activation_banked.
<suppressed ~1 debug messages>
4.7. Executing TRIBUF pass.
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
4.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~68 debug messages>
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 50 unused cells and 676 unused wires.
<suppressed ~57 debug messages>
4.11. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.12. Executing OPT pass (performing simple optimizations).
4.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 533 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 466 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 463 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~210 debug messages>
Removed a total of 70 cells.
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $flatten\dut.$procmux$1250.
dead port 2/2 on $mux $flatten\dut.$procmux$1256.
dead port 2/2 on $mux $flatten\dut.$procmux$1262.
dead port 2/2 on $mux $flatten\dut.$procmux$1280.
dead port 2/2 on $mux $flatten\dut.$procmux$1288.
dead port 2/2 on $mux $flatten\dut.$procmux$1316.
dead port 2/2 on $mux $flatten\dut.$procmux$1344.
dead port 2/2 on $mux $flatten\dut.$procmux$1372.
dead port 2/2 on $mux $flatten\dut.$procmux$1401.
dead port 2/2 on $mux $flatten\dut.$procmux$1407.
dead port 2/2 on $mux $flatten\dut.$procmux$1413.
dead port 2/2 on $mux $flatten\dut.$procmux$1431.
dead port 2/2 on $mux $flatten\dut.$procmux$1439.
dead port 2/2 on $mux $flatten\dut.$procmux$1467.
dead port 2/2 on $mux $flatten\dut.$procmux$1495.
dead port 2/2 on $mux $flatten\dut.$procmux$1523.
dead port 2/2 on $mux $flatten\dut.$procmux$1552.
dead port 2/2 on $mux $flatten\dut.$procmux$1558.
dead port 2/2 on $mux $flatten\dut.$procmux$1564.
dead port 2/2 on $mux $flatten\dut.$procmux$1582.
dead port 2/2 on $mux $flatten\dut.$procmux$1590.
dead port 2/2 on $mux $flatten\dut.$procmux$1618.
dead port 2/2 on $mux $flatten\dut.$procmux$1646.
dead port 2/2 on $mux $flatten\dut.$procmux$1674.
dead port 2/2 on $mux $flatten\dut.$procmux$1703.
dead port 2/2 on $mux $flatten\dut.$procmux$1709.
dead port 2/2 on $mux $flatten\dut.$procmux$1715.
dead port 2/2 on $mux $flatten\dut.$procmux$1732.
dead port 2/2 on $mux $flatten\dut.$procmux$1740.
dead port 2/2 on $mux $flatten\dut.$procmux$1768.
dead port 2/2 on $mux $flatten\dut.$procmux$1796.
dead port 2/2 on $mux $flatten\dut.$procmux$1824.
Removed 32 multiplexer ports.
<suppressed ~544 debug messages>
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1134:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] $flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_EN[63:0]$1079 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1145:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] $flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_EN[63:0]$1067 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1156:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_EN[63:0]$1055 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1167:
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0]
New connections: $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_EN[63:0]$1043 [0] }
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 4 changes.
4.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 431 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 102 unused wires.
<suppressed ~1 debug messages>
4.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~424 debug messages>
4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 431 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
4.13. Executing FSM pass (extract and optimize FSM).
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking harness_nms_activation_banked.dut.ack_stage1 as FSM state register:
Users of register don't seem to benefit from recoding.
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.14. Executing OPT pass (performing simple optimizations).
4.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 431 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~424 debug messages>
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 431 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$1846 ($dff) from module harness_nms_activation_banked (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:26$447_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
Adding SRST signal on $procdff$1848 ($dff) from module harness_nms_activation_banked (D = $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:56$453_Y, Q = \chk, rval = 8'00000000).
Adding SRST signal on $flatten\dut.$procdff$1878 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[0] [3:2], Q = \dut.bank_rd_addr_stage1[0], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1877 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[3], Q = \dut.bank_rd_en_stage1[3], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$1876 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[2], Q = \dut.bank_rd_en_stage1[2], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$1875 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[1], Q = \dut.bank_rd_en_stage1[1], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$1874 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[0], Q = \dut.bank_rd_en_stage1[0], rval = 1'0).
Adding SRST signal on $flatten\dut.$procdff$1873 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1223_Y, Q = \dut.rr_ptr[3], rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$1899 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1036_Y, Q = \dut.rr_ptr[3]).
Adding SRST signal on $flatten\dut.$procdff$1872 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1228_Y, Q = \dut.rr_ptr[2], rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$1901 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1034_Y, Q = \dut.rr_ptr[2]).
Adding SRST signal on $flatten\dut.$procdff$1871 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1233_Y, Q = \dut.rr_ptr[1], rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$1903 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1032_Y, Q = \dut.rr_ptr[1]).
Adding SRST signal on $flatten\dut.$procdff$1870 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$1238_Y, Q = \dut.rr_ptr[0], rval = 2'00).
Adding EN signal on $auto$ff.cc:337:slice$1905 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1030_Y, Q = \dut.rr_ptr[0]).
Adding SRST signal on $flatten\dut.$procdff$1869 ($dff) from module harness_nms_activation_banked (D = \dut.ack_comb, Q = \dut.ack_stage1, rval = 4'0000).
Adding SRST signal on $flatten\dut.$procdff$1868 ($dff) from module harness_nms_activation_banked (D = \dut.ack_stage1, Q = \dut.ack, rval = 4'0000).
Adding EN signal on $flatten\dut.$procdff$1862 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1048_DATA, Q = \dut.GEN_BANK[0].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$1858 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1060_DATA, Q = \dut.GEN_BANK[1].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$1854 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1072_DATA, Q = \dut.GEN_BANK[2].rd_data_r).
Adding EN signal on $flatten\dut.$procdff$1850 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$1084_DATA, Q = \dut.GEN_BANK[3].rd_data_r).
Adding SRST signal on $flatten\dut.$procdff$1882 ($dff) from module harness_nms_activation_banked (D = \lfsr [1:0], Q = \dut.slot_bank_stage1[0], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1883 ($dff) from module harness_nms_activation_banked (D = \lfsr [5:4], Q = \dut.slot_bank_stage1[1], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1881 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[3] [3:2], Q = \dut.bank_rd_addr_stage1[3], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1880 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[2] [3:2], Q = \dut.bank_rd_addr_stage1[2], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1884 ($dff) from module harness_nms_activation_banked (D = \lfsr [9:8], Q = \dut.slot_bank_stage1[2], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1885 ($dff) from module harness_nms_activation_banked (D = \lfsr [13:12], Q = \dut.slot_bank_stage1[3], rval = 2'00).
Adding SRST signal on $flatten\dut.$procdff$1879 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[1] [3:2], Q = \dut.bank_rd_addr_stage1[1], rval = 2'00).
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 27 unused cells and 27 unused wires.
<suppressed ~28 debug messages>
4.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~378 debug messages>
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 405 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
4.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1888 (dut.GEN_BANK[1].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1889 (dut.GEN_BANK[0].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1886 (dut.GEN_BANK[3].mem).
Removed top 30 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1887 (dut.GEN_BANK[2].mem).
Removed top 3 bits (of 4) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1908 ($sdff).
Removed top 3 bits (of 4) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1907 ($sdff).
Removed top 7 bits (of 8) from port B of cell harness_nms_activation_banked.$xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:54$449 ($xor).
Removed top 24 bits (of 32) from mux cell harness_nms_activation_banked.$procmux$1102 ($mux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1822_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1794_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1766_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1738_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1672_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1644_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1616_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1588_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1521_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1493_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1465_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1437_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1370_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1342_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1314_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1286_CMP0 ($eq).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1271 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1268 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1254 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1248 ($mux).
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$1244 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1173 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1162 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1151 ($mux).
Removed top 30 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1140 ($mux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1131_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1128 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1126_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1123 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1121_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1118 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$procmux$1116_CMP0 ($eq).
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$1113 ($pmux).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:66$1050 ($eq).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$1004 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$993 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$990 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$990 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$982 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$979 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$979 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$971 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$944 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$941 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$941 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$933 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$930 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$930 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$922 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$919 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$919 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$911 ($shiftx).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$904 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$900 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:112$896 ($eq).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$885 ($eq).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$884 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$881 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$881 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$874 ($eq).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$873 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$870 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$870 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$863 ($eq).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$862 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$859 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$859 ($add).
Removed top 1 bits (of 2) from port B of cell harness_nms_activation_banked.$flatten\dut.$eq$hardware/v2/nms/rtl/nms_activation_banked.v:104$852 ($eq).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$851 ($shiftx).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$824 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$821 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$821 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$813 ($shiftx).
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$810 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$810 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$802 ($shiftx).
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$799 ($add).
Removed top 30 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$799 ($add).
Removed top 29 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$791 ($shiftx).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1912 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1911 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1910 ($dffe).
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1909 ($dffe).
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001_Y.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$715_ADDR[31:0]$1041.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$716_ADDR[31:0]$1053.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[2].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$717_ADDR[31:0]$1065.
Removed top 30 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[3].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$718_ADDR[31:0]$1077.
Removed top 3 bits (of 4) from wire harness_nms_activation_banked.ack.
Removed top 56 bits (of 256) from wire harness_nms_activation_banked.rd_data_flat.
Removed top 24 bits (of 32) from wire harness_nms_activation_banked.$0\lfsr[31:0].
4.16. Executing PEEPOPT pass (run peephole optimizers).
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 67 unused cells and 80 unused wires.
<suppressed ~68 debug messages>
4.18. Executing SHARE pass (SAT-based resource sharing).
4.19. Executing TECHMAP pass (map to technology primitives).
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
4.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
4.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.22. Executing TECHMAP pass (map to technology primitives).
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
4.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.23. Executing TECHMAP pass (map to technology primitives).
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
4.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
4.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module harness_nms_activation_banked:
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$821 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$919 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$930 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$941 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$799 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$881 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$870 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1030 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1032 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1034 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$979 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1036 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$859 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$990 ($add).
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$810 ($add).
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$810.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$990.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$859.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1036.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$979.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1034.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1032.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1030.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$870.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$881.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$799.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$941.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$930.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$919.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001.
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$821.
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$821: $auto$alumacc.cc:548:replace_alu$1929
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$1001: $auto$alumacc.cc:548:replace_alu$1932
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$919: $auto$alumacc.cc:548:replace_alu$1935
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$930: $auto$alumacc.cc:548:replace_alu$1938
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$941: $auto$alumacc.cc:548:replace_alu$1941
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$799: $auto$alumacc.cc:548:replace_alu$1944
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$881: $auto$alumacc.cc:548:replace_alu$1947
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$870: $auto$alumacc.cc:548:replace_alu$1950
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1030: $auto$alumacc.cc:548:replace_alu$1953
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1032: $auto$alumacc.cc:548:replace_alu$1956
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1034: $auto$alumacc.cc:548:replace_alu$1959
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$979: $auto$alumacc.cc:548:replace_alu$1962
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$1036: $auto$alumacc.cc:548:replace_alu$1965
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$859: $auto$alumacc.cc:548:replace_alu$1968
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$990: $auto$alumacc.cc:548:replace_alu$1971
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$810: $auto$alumacc.cc:548:replace_alu$1974
created 16 $alu and 0 $macc cells.
4.25. Executing OPT pass (performing simple optimizations).
4.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 333 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~210 debug messages>
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 333 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
4.26. Executing MEMORY pass.
4.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing harness_nms_activation_banked.dut.GEN_BANK[0].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[1].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[2].mem write port 0.
Analyzing harness_nms_activation_banked.dut.GEN_BANK[3].mem write port 0.
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\dut.GEN_BANK[0].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[1].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_BANK[2].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: don't care on collision.
Checking read port `\dut.GEN_BANK[3].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
Write port 0: non-transparent.
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 4 unused cells and 32 unused wires.
<suppressed ~5 debug messages>
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory harness_nms_activation_banked.dut.GEN_BANK[3].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[3].mem: $\dut.GEN_BANK[3].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[0].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[0].mem: $\dut.GEN_BANK[0].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[1].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[1].mem: $\dut.GEN_BANK[1].mem$rdreg[0]
mapping memory harness_nms_activation_banked.dut.GEN_BANK[2].mem via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[2].mem: $\dut.GEN_BANK[2].mem$rdreg[0]
<suppressed ~1802 debug messages>
4.29. Executing TECHMAP pass (map to technology primitives).
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
4.29.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~82 debug messages>
4.30. Executing OPT pass (performing simple optimizations).
4.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~227 debug messages>
4.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 376 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 375 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 374 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 24 unused cells and 495 unused wires.
<suppressed ~25 debug messages>
4.30.5. Finished fast OPT passes.
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.32. Executing OPT pass (performing simple optimizations).
4.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 350 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~163 debug messages>
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 350 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.32.9. Finished fast OPT passes. (There is nothing left to do.)
4.33. Executing TECHMAP pass (map to technology primitives).
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
4.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$constmap:6eb06c7c7782671176f994104588177b22dcb4d2$paramod$4a9668f7e2c7c2af552980dad1b48191d692468c\_90_shift_shiftx for cells of type $shiftx.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $not.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
No more expansions possible.
<suppressed ~1128 debug messages>
4.34. Executing OPT pass (performing simple optimizations).
4.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
<suppressed ~590 debug messages>
4.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1910 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1688 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1632 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1592 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Computing hashes of 1560 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
<suppressed ~1050 debug messages>
Removed a total of 350 cells.
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 365 unused cells and 1221 unused wires.
<suppressed ~366 debug messages>
4.34.5. Finished fast OPT passes.
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
4.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 1195 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.38. Executing TECHMAP pass (map to technology primitives).
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.38.2. Continuing TECHMAP pass.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
No more expansions possible.
<suppressed ~191 debug messages>
4.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
4.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in harness_nms_activation_banked.
4.42. Executing ATTRMVCP pass (move or copy attributes).
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
Removed 0 unused cells and 491 unused wires.
<suppressed ~1 debug messages>
4.44. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.45. Executing TECHMAP pass (map to technology primitives).
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
4.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.46. Executing ABC9 pass.
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.3. Executing PROC pass (convert processes to netlists).
4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$6299'.
Cleaned up 1 empty switch.
4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.
4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.
4.46.3.4. Executing PROC_INIT pass (extract init attributes).
4.46.3.5. Executing PROC_ARST pass (detect async resets in processes).
4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_EN[3:0]$6306
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_DATA[3:0]$6305
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_ADDR[3:0]$6304
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$6299'.
4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6282_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6283_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6284_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6285_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6286_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6287_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6288_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6289_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6290_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6291_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6292_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6293_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6294_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6295_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6296_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$6297_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$6299'.
4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
created $dff cell `$procdff$6350' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
created $dff cell `$procdff$6351' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$6298_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
created $dff cell `$procdff$6352' with positive edge clock.
4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$6324'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$6300'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$6299'.
Cleaned up 1 empty switch.
4.46.4. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module harness_nms_activation_banked.
Found 0 SCCs.
4.46.5. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.6. Executing TECHMAP pass (map to technology primitives).
4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~167 debug messages>
4.46.7. Executing OPT pass (performing simple optimizations).
4.46.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.
4.46.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.
4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
4.46.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
4.46.7.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.8. Executing TECHMAP pass (map to technology primitives).
4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
4.46.8.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~11 debug messages>
4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.13. Executing TECHMAP pass (map to technology primitives).
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.13.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~171 debug messages>
4.46.14. Executing OPT pass (performing simple optimizations).
4.46.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_activation_banked..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_activation_banked.
Performed a total of 0 changes.
4.46.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_activation_banked'.
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
Finding duplicate cells in `\harness_nms_activation_banked'.
Removed a total of 0 cells.
4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_activation_banked..
4.46.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_activation_banked.
4.46.14.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.15. Executing AIGMAP pass (map logic to AIG).
4.46.16. Executing AIGMAP pass (map logic to AIG).
Module harness_nms_activation_banked: replaced 630 cells with 3462 new cells, skipped 573 cells.
replaced 3 cell types:
250 $_MUX_
316 $_OR_
64 $_XOR_
not replaced 6 cell types:
324 $_AND_
134 $_NOT_
1 $scopeinfo
98 TRELLIS_FF
8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
8 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.16.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 1582 AND gates and 4152 wires from module `harness_nms_activation_banked' to a netlist network with 140 inputs and 125 outputs.
4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
4.46.16.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 140/ 125 and = 1501 lev = 37 (2.99) mem = 0.02 MB box = 8 bb = 8
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 140/ 125 and = 1674 lev = 17 (1.89) mem = 0.03 MB ch = 239 box = 8 bb = 8
ABC: cst = 0 cls = 203 lit = 239 unused = 1404 proof = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 1674. Ch = 203. Total mem = 0.33 MB. Peak cut mem = 0.07 MB.
ABC: P: Del = 3224.00. Ar = 798.0. Edge = 1031. Cut = 24193. T = 0.00 sec
ABC: P: Del = 3224.00. Ar = 798.0. Edge = 1031. Cut = 24112. T = 0.00 sec
ABC: P: Del = 3224.00. Ar = 675.0. Edge = 1512. Cut = 36472. T = 0.00 sec
ABC: F: Del = 3217.00. Ar = 505.0. Edge = 1221. Cut = 32203. T = 0.00 sec
ABC: A: Del = 3217.00. Ar = 446.0. Edge = 1121. Cut = 32445. T = 0.00 sec
ABC: A: Del = 3217.00. Ar = 442.0. Edge = 1120. Cut = 33315. T = 0.00 sec
ABC: Total time = 0.02 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 140/ 125 and = 1287 lev = 19 (2.07) mem = 0.02 MB box = 8 bb = 8
ABC: Mapping (K=7) : lut = 258 edge = 1039 lev = 6 (0.79) levB = 6 mem = 0.01 MB
ABC: LUT = 258 : 2=28 10.9 % 3=48 18.6 % 4=83 32.2 % 5=90 34.9 % 6=6 2.3 % 7=3 1.2 % Ave = 4.03
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.02 sec
ABC: + time
ABC: elapse: 0.13 seconds, total: 0.13 seconds
4.46.16.6. Executing AIGER frontend.
<suppressed ~10 debug messages>
Removed 2054 unused cells and 2362 unused wires.
4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 258
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 8
ABC RESULTS: input signals: 25
ABC RESULTS: output signals: 40
<suppressed ~530 debug messages>
Removing temp directory.
4.46.17. Executing TECHMAP pass (map to technology primitives).
4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
4.46.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~23 debug messages>
Removed 17 unused cells and 4830 unused wires.
4.47. Executing TECHMAP pass (map to technology primitives).
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
4.47.2. Continuing TECHMAP pass.
Using template $paramod$0acebc852fafe7c7c44c11b7043c255fbfee532e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$74190755306950a81a07803293f7549508f6f157$lut for cells of type $lut.
Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111101 for cells of type $lut.
Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75$lut for cells of type $lut.
Using template $paramod$af5e0def74f338efac564afc8f9d69aed50886ca$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$562742778950be5e64a32ee62d1969df5be2f6d8$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9$lut for cells of type $lut.
Using template $paramod$bc12de5d7b0c241eb511092a42ca864d66eb88ba$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba$lut for cells of type $lut.
Using template $paramod$72d04cda0ad63fcea17225ad4256bc664683b513$lut for cells of type $lut.
Using template $paramod$636489ee6fd9daecee952e374b74ebd4427c62b5$lut for cells of type $lut.
Using template $paramod$183411b9f3e5024c6a705a0305ebc2718a42952d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31$lut for cells of type $lut.
Using template $paramod$13c050192196a3c10406083ef415168b5135cd0e$lut for cells of type $lut.
Using template $paramod$ebdfc07f371983eb68dd70ec63edee869ba600bd$lut for cells of type $lut.
Using template $paramod$fd5d53ef63174a0b662c49e3b29545d399c7a8d1$lut for cells of type $lut.
Using template $paramod$23b135911b7c14b5b19b5329e5903bcf58b44188$lut for cells of type $lut.
Using template $paramod$9aa7751d7e54864227371e1d1c41b38bd70cff17$lut for cells of type $lut.
Using template $paramod$9862b1430429ca4c11ef326294d5f0ec3a8a8e38$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$11caa309d440b13bda12e5784cdc3cdbee2b9cb9$lut for cells of type $lut.
Using template $paramod$134f0147e531c28322eb1e5f2adc0709b9c01756$lut for cells of type $lut.
Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b$lut for cells of type $lut.
Using template $paramod$d575de8e588b46dbb00e03e414e3303cf809cb33$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$90453044f54ff374897f04f3086f002f3dda8f22$lut for cells of type $lut.
Using template $paramod$70e649cff31ac39ffa7544751d17e54df9788341$lut for cells of type $lut.
Using template $paramod$207a8c4d93741aaa7c0381d27584ba6e6d12dd2d$lut for cells of type $lut.
Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$44adbaeba8aebac00b5b76c0c821287bd76a54f4$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$506e03709b10468255f3d8819b486cd1340ca5e5$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da$lut for cells of type $lut.
Using template $paramod$be01ff1fe191f262a5e6228029151f6170c867de$lut for cells of type $lut.
Using template $paramod$ef423ce8bffc6b734abf7282a22c7b6c0518dbb1$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775$lut for cells of type $lut.
Using template $paramod$ed9544c6d588b1539e517a0479eaaa5314b479af$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$992d51102bf1c202cf3e67979aa062595af82d5f$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$a745274df8f514565625fa7fee7a9fb864a85f2f$lut for cells of type $lut.
Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991$lut for cells of type $lut.
Using template $paramod$29442795ef2e10dd90e3826e90a6d7a832893bba$lut for cells of type $lut.
Using template $paramod$0eddca28013e351d02684296cedef58454610cb5$lut for cells of type $lut.
Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4$lut for cells of type $lut.
Using template $paramod$5a60a2ac5fa0ff621c08e76879e9692734937783$lut for cells of type $lut.
Using template $paramod$e7fa813675354f20c694ab2d4d9ecca5b21f170c$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8$lut for cells of type $lut.
Using template $paramod$af4085f793a5006bfe4450d67d0a7562868b122c$lut for cells of type $lut.
Using template $paramod$80a6e42bd275186e6d6f4594bfd9b17c8c6a1a4f$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d$lut for cells of type $lut.
Using template $paramod$8d682dd07ca5cb3ab18b18c4b7aed2342a1e5cff$lut for cells of type $lut.
Using template $paramod$35747c4193cc59c2095f0a415365bd2a443730a2$lut for cells of type $lut.
Using template $paramod$26670e8b83c71ee9c0ff9ca0059dae6147c8faae$lut for cells of type $lut.
Using template $paramod$a0f67318f1c24388c545d8c57553aed79a7a9a84$lut for cells of type $lut.
Using template $paramod$54ef21ccddfa27629768f219f304bb4163ac6894$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut.
Using template $paramod$73e4a15f82f06533f46c76304a5571433fbe757d$lut for cells of type $lut.
Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c$lut for cells of type $lut.
Using template $paramod$82abb8f9ddaac453e6ee24bf456879be259b8e87$lut for cells of type $lut.
Using template $paramod$80c57506599e789c4765758c4a3d41a728771aaf$lut for cells of type $lut.
Using template $paramod$144be6f575ecc4be7ff83d3a352b1059ce5ade9a$lut for cells of type $lut.
Using template $paramod$c6b00b6e5a45587dd2a405086c5dc32a5a05c4c3$lut for cells of type $lut.
Using template $paramod$a986a11bb2f8a11c95413116adc9f6f403b3979e$lut for cells of type $lut.
Using template $paramod$e773918a138fafa01ebb204178d7bc22db22e9a2$lut for cells of type $lut.
Using template $paramod$89ea009ef34e783366f9a952d0fba206c9b289f9$lut for cells of type $lut.
Using template $paramod$0d2a91788a3f0f49e8d6381c2f6df042d669b113$lut for cells of type $lut.
Using template $paramod$aa569d89e9c8462354297a37f09bc519483c7133$lut for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$c4a97cf0b46779df8741d618ac94cb76d112af85$lut for cells of type $lut.
Using template $paramod$28217f2cfc8d694374c1af6d33c650ee529a0f08$lut for cells of type $lut.
Using template $paramod$9b742027133b4fde85a5459539c0c07da9610d18$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912$lut for cells of type $lut.
Using template $paramod$1d2e7c7f362f4451ffeeaa6416a310579e8441e4$lut for cells of type $lut.
Using template $paramod$66f4e42f6ecc06064dc14df2d3ed673c4ae6d667$lut for cells of type $lut.
Using template $paramod$718d75761d1aecc0b984e2c28120a43b4f7ad413$lut for cells of type $lut.
Using template $paramod$2519369102810c93a6a374dd0894f7db48965952$lut for cells of type $lut.
Using template $paramod$1b21bfe3f0f701f19b91b9d9f4b2cb25c52e0379$lut for cells of type $lut.
Using template $paramod$b55f45c6dc20e6c434e3ecfaac16a92e424cd4fe$lut for cells of type $lut.
Using template $paramod$e55d30bd73d1c73c33e74b555b9deb1f770c02f0$lut for cells of type $lut.
Using template $paramod$6e44b1cf69ddb13fc3664878b882e409a07d4154$lut for cells of type $lut.
Using template $paramod$f37c73d4705d9fa255ffe268edca27725711e62e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$5f87a93ef4cf35c280d95d6ee0abe4a24b1120ad$lut for cells of type $lut.
Using template $paramod$77d6c852c4fa46d427070381e5194d5f2c61af9e$lut for cells of type $lut.
Using template $paramod$68eab1cc6901dc28cf976ab6b8c4942e68212063$lut for cells of type $lut.
Using template $paramod$33dc5bf1fdf3778a5ed9e08799e1ccd14fabecb6$lut for cells of type $lut.
Using template $paramod$3fc3ee795a765be3f9cf73127e7c09a95188fa5b$lut for cells of type $lut.
Using template $paramod$2da9328813dbaa8b1d0552f8bc0422a364dafd8d$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$923a34bca12d215b7d61635060bb4ef616b5625f$lut for cells of type $lut.
Using template $paramod$004ef71df503bd2d805b38e6c8272ea7fd03c07c$lut for cells of type $lut.
Using template $paramod$63fed8d9ecc0f29cfe1900d13ef587de5f7a224e$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
Using template $paramod$65e23693bd421f4d05f34934a9fe1379e8afc8e0$lut for cells of type $lut.
Using template $paramod$a9a0d3da8e2570975000fd954dff796c3807df01$lut for cells of type $lut.
Using template $paramod$87e90b9986185e21356ab65f6d502d6db445599a$lut for cells of type $lut.
Using template $paramod$38ec732ccd2132d1906041d0a658b5217ba9b394$lut for cells of type $lut.
Using template $paramod$1076d5b96410dc32bbe68df15017559464728316$lut for cells of type $lut.
Using template $paramod$a0585ddafc46a4180d5790c1e0a93d8469cb93b1$lut for cells of type $lut.
Using template $paramod$afa13e20ea6849a4eb5f94bed44ee14b6298248f$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$f708b7057af81b2f8c1afe1f7353a41e38939997$lut for cells of type $lut.
Using template $paramod$e072fe3ca6403414a47480bcf08a558c05201da4$lut for cells of type $lut.
Using template $paramod$65eb2e57495c9219b79c2deeff8a6f521289df69$lut for cells of type $lut.
Using template $paramod$e33313994699420877bfc29e16fadeb5c81d8913$lut for cells of type $lut.
Using template $paramod$04fb42c7edd896b5bccceeca764e8909f4bc256e$lut for cells of type $lut.
Using template $paramod$01695681df8d64ee3d7c51f206c04ed4c2291450$lut for cells of type $lut.
No more expansions possible.
<suppressed ~2073 debug messages>
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in harness_nms_activation_banked.
Optimizing lut $abc$13437$lut$aiger13436$1429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger$o106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger$o75.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$1216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o74.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o72.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$805.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$342.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger$o104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger$o73.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$901.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$1237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$13437$lut$aiger13436$1016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$13437$lut$aiger13436$317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$1096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$13437$lut$aiger13436$1230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$13437$lut$aiger13436$777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Removed 0 unused cells and 624 unused wires.
4.49. Executing AUTONAME pass.
Renamed 1002 objects in module harness_nms_activation_banked.
<suppressed ~1002 debug messages>
4.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `harness_nms_activation_banked'. Setting top module to harness_nms_activation_banked.
4.50.1. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
4.50.2. Analyzing design hierarchy..
Top module: \harness_nms_activation_banked
Removed 0 unused modules.
4.51. Printing statistics.
=== harness_nms_activation_banked ===
+----------Local Count, excluding submodules.
|
463 wires
2458 wire bits
463 public wires
2458 public wire bits
4 ports
18 port bits
1 cells
1 $scopeinfo
623 submodules
15 L6MUX21
388 LUT4
114 PFUMX
8 TRELLIS_DPR16X4
98 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
1 harness_nms_activation_banked
+----------Count including submodules.
|
463 wires
2458 wire bits
463 public wires
2458 public wire bits
4 ports
18 port bits
- memories
- memory bits
- processes
1 cells
1 $scopeinfo
623 submodules
15 L6MUX21
388 LUT4
114 PFUMX
8 TRELLIS_DPR16X4
98 TRELLIS_FF
4.52. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_activation_banked...
Found and reported 0 problems.
4.53. Executing JSON backend.
Warnings: 12 unique messages, 22 total
End of script. Logfile hash: e3dff1e6df, time: 0.61s, user: 0.45s, system: 0.02s, MEM: 73.11 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 31% 22x read_verilog (0 sec), 23% 1x abc9_exe (0 sec), ...
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