micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
1729 lines
125 KiB
Plaintext
1729 lines
125 KiB
Plaintext
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| Distributed under an ISC-like license, type "license" to see terms |
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\----------------------------------------------------------------------------/
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Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
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-- Running command `read_verilog hardware/v2/nms/rtl/nms_activation_banked.v hardware/v2/nms/synthesis/harness_nms_activation_banked.v; chparam -set N_SLOTS 2 -set N_BANKS 2 -set MAX_TILES 16 harness_nms_activation_banked; synth_ecp5 -json hardware/v2/nms/synthesis/act_bank_n2_b2/top.json -top harness_nms_activation_banked' --
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1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_activation_banked.v
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Parsing Verilog input from `hardware/v2/nms/rtl/nms_activation_banked.v' to AST representation.
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Generating RTLIL representation for module `\nms_activation_banked'.
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Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
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Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
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Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
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Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
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Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
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Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
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Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
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Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
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Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
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Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_activation_banked.v
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Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_activation_banked.v' to AST representation.
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Generating RTLIL representation for module `\harness_nms_activation_banked'.
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Successfully finished Verilog frontend.
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Parameter \N_SLOTS = 2
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Parameter \N_BANKS = 2
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Parameter \MAX_TILES = 16
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3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_activation_banked'.
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Parameter \N_SLOTS = 2
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Parameter \N_BANKS = 2
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Parameter \MAX_TILES = 16
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Generating RTLIL representation for module `$paramod$3ef1f58798a9d7b76f4d95b3374528853c53d09a\harness_nms_activation_banked'.
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4. Executing SYNTH_LATTICE pass.
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4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_COMB'.
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Generating RTLIL representation for module `\VLO'.
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Generating RTLIL representation for module `\VHI'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\DP16KD'.
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Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
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Generating RTLIL representation for module `\FD1P3AX'.
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Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
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Generating RTLIL representation for module `\FD1P3AY'.
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Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
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Generating RTLIL representation for module `\FD1P3BX'.
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Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
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Generating RTLIL representation for module `\FD1P3DX'.
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Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
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Generating RTLIL representation for module `\FD1P3IX'.
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Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
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Generating RTLIL representation for module `\FD1P3JX'.
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Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
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Generating RTLIL representation for module `\FD1S3AX'.
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Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
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Generating RTLIL representation for module `\FD1S3AY'.
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Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
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Generating RTLIL representation for module `\FD1S3BX'.
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Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
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Generating RTLIL representation for module `\FD1S3DX'.
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Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
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Generating RTLIL representation for module `\FD1S3IX'.
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Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
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Generating RTLIL representation for module `\FD1S3JX'.
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Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
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Generating RTLIL representation for module `\IB'.
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Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
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Generating RTLIL representation for module `\IBPU'.
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Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
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Generating RTLIL representation for module `\IBPD'.
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Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
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Generating RTLIL representation for module `\OB'.
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Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
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Generating RTLIL representation for module `\OBZ'.
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Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
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Generating RTLIL representation for module `\OBZPU'.
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Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
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Generating RTLIL representation for module `\OBZPD'.
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Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
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Generating RTLIL representation for module `\OBCO'.
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Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
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Generating RTLIL representation for module `\BB'.
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Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
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Generating RTLIL representation for module `\BBPU'.
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Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
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Generating RTLIL representation for module `\BBPD'.
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Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
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Generating RTLIL representation for module `\ILVDS'.
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Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
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Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DCUA'.
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Successfully finished Verilog frontend.
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4.3. Executing HIERARCHY pass (managing design hierarchy).
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4.3.1. Analyzing design hierarchy..
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Top module: \harness_nms_activation_banked
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Used module: \nms_activation_banked
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \N_SLOTS = 2
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Parameter \N_BANKS = 2
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Parameter \MAX_TILES = 16
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4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_activation_banked'.
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Parameter \DATA_WIDTH = 8
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Parameter \P_IN = 8
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Parameter \N_SLOTS = 2
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Parameter \N_BANKS = 2
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Parameter \MAX_TILES = 16
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Generating RTLIL representation for module `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked'.
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Warning: Replacing memory \slot_bank_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:135
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Warning: Replacing memory \bank_rd_addr_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:130
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Warning: Replacing memory \bank_rd_en_stage1 with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:129
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Warning: Replacing memory \rr_ptr with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:128
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Warning: Replacing memory \win_first with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:101
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Warning: Replacing memory \win_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:112, hardware/v2/nms/rtl/nms_activation_banked.v:100
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Warning: Replacing memory \win_valid with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:104, hardware/v2/nms/rtl/nms_activation_banked.v:99
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Warning: Replacing memory \slot_bank_comb with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95
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Warning: Replacing memory \req_bank with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:95, hardware/v2/nms/rtl/nms_activation_banked.v:94
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Warning: Replacing memory \req_tile_idx with list of registers. See hardware/v2/nms/rtl/nms_activation_banked.v:94, hardware/v2/nms/rtl/nms_activation_banked.v:93
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4.3.3. Analyzing design hierarchy..
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Top module: \harness_nms_activation_banked
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Used module: $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked
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4.3.4. Analyzing design hierarchy..
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Top module: \harness_nms_activation_banked
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Used module: $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked
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Removing unused module `\nms_activation_banked'.
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Removed 1 unused modules.
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4.4. Executing PROC pass (convert processes to netlists).
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4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443 in module harness_nms_activation_banked.
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Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448 in module harness_nms_activation_banked.
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|
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
|
|
Removed 1 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Removed 8 dead cases from process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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Marked 18 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689 in module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
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|
Removed a total of 10 dead cases.
|
|
|
|
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 10 redundant assignments.
|
|
Promoted 47 assignments to connections.
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|
|
|
4.4.4. Executing PROC_INIT pass (extract init attributes).
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|
|
|
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
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|
|
|
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~29 debug messages>
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|
|
|
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
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|
1/1: $0\lfsr[31:0]
|
|
Creating decoders for process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
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|
1/3: $0\chk[7:0]
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|
2/3: $1\chk_next[7:0]
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|
3/3: $1\k[31:0]
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802'.
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|
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$686_DATA[63:0]$804
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799'.
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|
1/1: $1$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$685_DATA[63:0]$801
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$798'.
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|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$797'.
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
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|
1/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$794
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|
2/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_DATA[63:0]$793
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|
3/4: $1$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_ADDR[31:0]$792
|
|
4/4: $0\GEN_BANK[1].rd_data_r[63:0]
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
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|
1/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$782
|
|
2/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_DATA[63:0]$781
|
|
3/4: $1$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_ADDR[31:0]$780
|
|
4/4: $0\GEN_BANK[0].rd_data_r[63:0]
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
1/12: $4\i[31:0]
|
|
2/12: $0\slot_bank_stage1[1][0:0]
|
|
3/12: $0\slot_bank_stage1[0][0:0]
|
|
4/12: $0\ack[1:0]
|
|
5/12: $0\ack_stage1[1:0]
|
|
6/12: $2\b[31:0]
|
|
7/12: $0\bank_rd_addr_stage1[1][2:0]
|
|
8/12: $0\bank_rd_en_stage1[1][0:0]
|
|
9/12: $0\bank_rd_addr_stage1[0][2:0]
|
|
10/12: $0\bank_rd_en_stage1[0][0:0]
|
|
11/12: $0\rr_ptr[1][0:0]
|
|
12/12: $0\rr_ptr[0][0:0]
|
|
Creating decoders for process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
1/38: $4\ack_comb[1:0] [1]
|
|
2/38: $5\ack_comb[0:0]
|
|
3/38: $2\i[31:0]
|
|
4/38: $4\ack_comb[1:0] [0]
|
|
5/38: $6\ack_comb[1:1]
|
|
6/38: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$759
|
|
7/38: $2\win_first[1][0:0]
|
|
8/38: $2\win_tile_idx[1][3:0]
|
|
9/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_DATA[3:0]$758
|
|
10/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$684_ADDR[0:0]$757
|
|
11/38: $2\win_valid[1][0:0]
|
|
12/38: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$683_DATA[0:0]$751
|
|
13/38: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_DATA[3:0]$748
|
|
14/38: $1\win_first[1][0:0]
|
|
15/38: $1\win_tile_idx[1][3:0]
|
|
16/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_DATA[3:0]$747
|
|
17/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$682_ADDR[0:0]$746
|
|
18/38: $1\win_valid[1][0:0]
|
|
19/38: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$681_DATA[0:0]$740
|
|
20/38: $1\ack_comb[1:0] [1]
|
|
21/38: $2\ack_comb[0:0]
|
|
22/38: $1\i[31:0]
|
|
23/38: $1\ack_comb[1:0] [0]
|
|
24/38: $3\ack_comb[1:1]
|
|
25/38: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_DATA[3:0]$729
|
|
26/38: $2\win_first[0][0:0]
|
|
27/38: $2\win_tile_idx[0][3:0]
|
|
28/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_DATA[3:0]$728
|
|
29/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$680_ADDR[0:0]$727
|
|
30/38: $2\win_valid[0][0:0]
|
|
31/38: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$679_DATA[0:0]$721
|
|
32/38: $2$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$678_DATA[3:0]$718
|
|
33/38: $1\win_first[0][0:0]
|
|
34/38: $1\win_tile_idx[0][3:0]
|
|
35/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$678_DATA[3:0]$717
|
|
36/38: $1$mem2reg_rd$\req_tile_idx$hardware/v2/nms/rtl/nms_activation_banked.v:106$678_ADDR[0:0]$716
|
|
37/38: $1\win_valid[0][0:0]
|
|
38/38: $1$mem2reg_rd$\req_bank$hardware/v2/nms/rtl/nms_activation_banked.v:104$677_DATA[0:0]$710
|
|
|
|
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$686_DATA' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$mem2reg_rd$\bank_rd_data_reg$hardware/v2/nms/rtl/nms_activation_banked.v:160$685_DATA' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_data_reg[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$798'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_data_reg[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$797'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\b' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\i' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\ack_comb' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\scan_i' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\cand' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\req_tile_idx[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\req_tile_idx[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\req_bank[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\req_bank[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\slot_bank_comb[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\slot_bank_comb[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_valid[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_valid[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_tile_idx[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_tile_idx[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_first[0]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
No latch inferred for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\win_first[1]' from process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
|
|
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `\harness_nms_activation_banked.\lfsr' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
|
|
created $dff cell `$procdff$1020' with positive edge clock.
|
|
Creating register for signal `\harness_nms_activation_banked.\k' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
|
|
created $dff cell `$procdff$1021' with positive edge clock.
|
|
Creating register for signal `\harness_nms_activation_banked.\chk' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
|
|
created $dff cell `$procdff$1022' with positive edge clock.
|
|
Creating register for signal `\harness_nms_activation_banked.\chk_next' using process `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
|
|
created $dff cell `$procdff$1023' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\GEN_BANK[1].rd_data_r' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
created $dff cell `$procdff$1024' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_ADDR' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
created $dff cell `$procdff$1025' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_DATA' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
created $dff cell `$procdff$1026' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
created $dff cell `$procdff$1027' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\GEN_BANK[0].rd_data_r' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
created $dff cell `$procdff$1028' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_ADDR' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
created $dff cell `$procdff$1029' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_DATA' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
created $dff cell `$procdff$1030' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
created $dff cell `$procdff$1031' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\b' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1032' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\i' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1033' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\ack' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1034' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\ack_stage1' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1035' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\rr_ptr[0]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1036' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\rr_ptr[1]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1037' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_en_stage1[0]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1038' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_en_stage1[1]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1039' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_addr_stage1[0]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1040' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\bank_rd_addr_stage1[1]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1041' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\slot_bank_stage1[0]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1042' with positive edge clock.
|
|
Creating register for signal `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.\slot_bank_stage1[1]' using process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
created $dff cell `$procdff$1043' with positive edge clock.
|
|
|
|
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
|
|
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:24$443'.
|
|
Found and cleaned up 1 empty switch in `\harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
|
|
Removing empty process `harness_nms_activation_banked.$proc$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:50$448'.
|
|
Found and cleaned up 1 empty switch in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$802'.
|
|
Found and cleaned up 1 empty switch in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:160$799'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$798'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:74$797'.
|
|
Found and cleaned up 2 empty switches in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$788'.
|
|
Found and cleaned up 2 empty switches in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:68$776'.
|
|
Found and cleaned up 3 empty switches in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:125$768'.
|
|
Found and cleaned up 18 empty switches in `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
Removing empty process `$paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.$proc$hardware/v2/nms/rtl/nms_activation_banked.v:91$689'.
|
|
Cleaned up 29 empty switches.
|
|
|
|
4.4.12. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~1 debug messages>
|
|
Optimizing module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
|
|
<suppressed ~24 debug messages>
|
|
|
|
4.5. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_activation_banked...
|
|
Checking module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked...
|
|
Warning: Drivers conflicting with a constant 1'0 driver:
|
|
port Q[0] of cell $procdff$1033 ($dff)
|
|
port Q[2] of cell $procdff$1033 ($dff)
|
|
port Q[3] of cell $procdff$1033 ($dff)
|
|
port Q[4] of cell $procdff$1033 ($dff)
|
|
port Q[5] of cell $procdff$1033 ($dff)
|
|
port Q[6] of cell $procdff$1033 ($dff)
|
|
port Q[7] of cell $procdff$1033 ($dff)
|
|
port Q[8] of cell $procdff$1033 ($dff)
|
|
port Q[9] of cell $procdff$1033 ($dff)
|
|
port Q[10] of cell $procdff$1033 ($dff)
|
|
port Q[11] of cell $procdff$1033 ($dff)
|
|
port Q[12] of cell $procdff$1033 ($dff)
|
|
port Q[13] of cell $procdff$1033 ($dff)
|
|
port Q[14] of cell $procdff$1033 ($dff)
|
|
port Q[15] of cell $procdff$1033 ($dff)
|
|
port Q[16] of cell $procdff$1033 ($dff)
|
|
port Q[17] of cell $procdff$1033 ($dff)
|
|
port Q[18] of cell $procdff$1033 ($dff)
|
|
port Q[19] of cell $procdff$1033 ($dff)
|
|
port Q[20] of cell $procdff$1033 ($dff)
|
|
port Q[21] of cell $procdff$1033 ($dff)
|
|
port Q[22] of cell $procdff$1033 ($dff)
|
|
port Q[23] of cell $procdff$1033 ($dff)
|
|
port Q[24] of cell $procdff$1033 ($dff)
|
|
port Q[25] of cell $procdff$1033 ($dff)
|
|
port Q[26] of cell $procdff$1033 ($dff)
|
|
port Q[27] of cell $procdff$1033 ($dff)
|
|
port Q[28] of cell $procdff$1033 ($dff)
|
|
port Q[29] of cell $procdff$1033 ($dff)
|
|
port Q[30] of cell $procdff$1033 ($dff)
|
|
port Q[31] of cell $procdff$1033 ($dff)
|
|
port Q[0] of cell $procdff$1032 ($dff)
|
|
port Q[2] of cell $procdff$1032 ($dff)
|
|
port Q[3] of cell $procdff$1032 ($dff)
|
|
port Q[4] of cell $procdff$1032 ($dff)
|
|
port Q[5] of cell $procdff$1032 ($dff)
|
|
port Q[6] of cell $procdff$1032 ($dff)
|
|
port Q[7] of cell $procdff$1032 ($dff)
|
|
port Q[8] of cell $procdff$1032 ($dff)
|
|
port Q[9] of cell $procdff$1032 ($dff)
|
|
port Q[10] of cell $procdff$1032 ($dff)
|
|
port Q[11] of cell $procdff$1032 ($dff)
|
|
port Q[12] of cell $procdff$1032 ($dff)
|
|
port Q[13] of cell $procdff$1032 ($dff)
|
|
port Q[14] of cell $procdff$1032 ($dff)
|
|
port Q[15] of cell $procdff$1032 ($dff)
|
|
port Q[16] of cell $procdff$1032 ($dff)
|
|
port Q[17] of cell $procdff$1032 ($dff)
|
|
port Q[18] of cell $procdff$1032 ($dff)
|
|
port Q[19] of cell $procdff$1032 ($dff)
|
|
port Q[20] of cell $procdff$1032 ($dff)
|
|
port Q[21] of cell $procdff$1032 ($dff)
|
|
port Q[22] of cell $procdff$1032 ($dff)
|
|
port Q[23] of cell $procdff$1032 ($dff)
|
|
port Q[24] of cell $procdff$1032 ($dff)
|
|
port Q[25] of cell $procdff$1032 ($dff)
|
|
port Q[26] of cell $procdff$1032 ($dff)
|
|
port Q[27] of cell $procdff$1032 ($dff)
|
|
port Q[28] of cell $procdff$1032 ($dff)
|
|
port Q[29] of cell $procdff$1032 ($dff)
|
|
port Q[30] of cell $procdff$1032 ($dff)
|
|
port Q[31] of cell $procdff$1032 ($dff)
|
|
Warning: Drivers conflicting with a constant 1'1 driver:
|
|
port Q[1] of cell $procdff$1033 ($dff)
|
|
port Q[1] of cell $procdff$1032 ($dff)
|
|
Found and reported 2 problems.
|
|
|
|
4.6. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$4e295cf24eb4aa44cac244149cf5c3fa133a7890\nms_activation_banked.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.7. Executing TRIBUF pass.
|
|
|
|
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
4.9. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~30 debug messages>
|
|
|
|
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 22 unused cells and 260 unused wires.
|
|
<suppressed ~27 debug messages>
|
|
|
|
4.11. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_activation_banked...
|
|
Found and reported 0 problems.
|
|
|
|
4.12. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.12.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.12.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 123 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Computing hashes of 119 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
<suppressed ~12 debug messages>
|
|
Removed a total of 4 cells.
|
|
|
|
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Replacing known input bits on port B of cell $flatten\dut.$procmux$827: { \lfsr \lfsr } -> { \lfsr [31:1] 1'1 \lfsr [31:1] 1'1 }
|
|
Analyzing evaluation results.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$890.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$902.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$908.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$932.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$959.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$970.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$976.
|
|
dead port 2/2 on $mux $flatten\dut.$procmux$1000.
|
|
Removed 8 multiplexer ports.
|
|
<suppressed ~105 debug messages>
|
|
|
|
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$824:
|
|
Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791
|
|
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0]
|
|
New connections: $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] $flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_EN[63:0]$791 [0] }
|
|
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$835:
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Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779
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New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0]
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New connections: $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [63:1] = { $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] $flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_EN[63:0]$779 [0] }
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Optimizing cells in module \harness_nms_activation_banked.
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Performed a total of 3 changes.
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4.12.5. Executing OPT_MERGE pass (detect identical cells).
|
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Finding identical cells in module `\harness_nms_activation_banked'.
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Computing hashes of 110 cells of `\harness_nms_activation_banked'.
|
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Finding duplicate cells in `\harness_nms_activation_banked'.
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Removed a total of 0 cells.
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4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
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4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
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Finding unused cells or wires in module \harness_nms_activation_banked..
|
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Removed 0 unused cells and 13 unused wires.
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<suppressed ~1 debug messages>
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4.12.8. Executing OPT_EXPR pass (perform const folding).
|
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Optimizing module harness_nms_activation_banked.
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4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
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4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
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Running muxtree optimizer on module \harness_nms_activation_banked..
|
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Creating internal representation of mux trees.
|
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Evaluating internal representation of mux trees.
|
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Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
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<suppressed ~89 debug messages>
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4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
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Optimizing cells in module \harness_nms_activation_banked.
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Performed a total of 0 changes.
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4.12.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 110 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
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|
|
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.12.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.13. Executing FSM pass (extract and optimize FSM).
|
|
|
|
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
Not marking harness_nms_activation_banked.dut.ack_stage1 as FSM state register:
|
|
Users of register don't seem to benefit from recoding.
|
|
|
|
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
4.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 110 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~89 debug messages>
|
|
|
|
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Performed a total of 0 changes.
|
|
|
|
4.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 110 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
Adding SRST signal on $flatten\dut.$procdff$1039 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[1], Q = \dut.bank_rd_en_stage1[1], rval = 1'0).
|
|
Adding SRST signal on $procdff$1020 ($dff) from module harness_nms_activation_banked (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:26$447_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
|
|
Adding SRST signal on $procdff$1022 ($dff) from module harness_nms_activation_banked (D = $xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:56$451_Y, Q = \chk, rval = 8'00000000).
|
|
Adding SRST signal on $flatten\dut.$procdff$1036 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$878_Y, Q = \dut.rr_ptr[0], rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1051 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$770_Y, Q = \dut.rr_ptr[0]).
|
|
Adding SRST signal on $flatten\dut.$procdff$1035 ($dff) from module harness_nms_activation_banked (D = \dut.ack_comb [1], Q = \dut.ack_stage1 [1], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1035 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$5\ack_comb[0:0], Q = \dut.ack_stage1 [0], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1034 ($dff) from module harness_nms_activation_banked (D = \dut.ack_stage1, Q = \dut.ack, rval = 2'00).
|
|
Adding EN signal on $flatten\dut.$procdff$1028 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$784_DATA, Q = \dut.GEN_BANK[0].rd_data_r).
|
|
Adding SRST signal on $flatten\dut.$procdff$1043 ($dff) from module harness_nms_activation_banked (D = \lfsr [4], Q = \dut.slot_bank_stage1[1], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1042 ($dff) from module harness_nms_activation_banked (D = \lfsr [0], Q = \dut.slot_bank_stage1[0], rval = 1'0).
|
|
Adding EN signal on $flatten\dut.$procdff$1024 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$memrd$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:72$796_DATA, Q = \dut.GEN_BANK[1].rd_data_r).
|
|
Adding SRST signal on $flatten\dut.$procdff$1041 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[1] [3:1], Q = \dut.bank_rd_addr_stage1[1], rval = 3'000).
|
|
Adding SRST signal on $flatten\dut.$procdff$1040 ($dff) from module harness_nms_activation_banked (D = \dut.win_tile_idx[0] [3:1], Q = \dut.bank_rd_addr_stage1[0], rval = 3'000).
|
|
Adding SRST signal on $flatten\dut.$procdff$1038 ($dff) from module harness_nms_activation_banked (D = \dut.win_valid[0], Q = \dut.bank_rd_en_stage1[0], rval = 1'0).
|
|
Adding SRST signal on $flatten\dut.$procdff$1037 ($dff) from module harness_nms_activation_banked (D = $flatten\dut.$procmux$873_Y, Q = \dut.rr_ptr[1], rval = 1'0).
|
|
Adding EN signal on $auto$ff.cc:337:slice$1067 ($sdff) from module harness_nms_activation_banked (D = $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$772_Y, Q = \dut.rr_ptr[1]).
|
|
|
|
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 16 unused cells and 15 unused wires.
|
|
<suppressed ~17 debug messages>
|
|
|
|
4.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
|
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~62 debug messages>
|
|
|
|
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Performed a total of 0 changes.
|
|
|
|
4.14.12. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 98 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.14.15. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.15. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 29 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1045 (dut.GEN_BANK[0].mem).
|
|
Removed top 29 address bits (of 32) from memory init port harness_nms_activation_banked.$flatten\dut.$auto$proc_memwr.cc:45:proc_memwr$1044 (dut.GEN_BANK[1].mem).
|
|
Removed top 1 bits (of 2) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1059 ($sdff).
|
|
Removed cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1053 ($sdff).
|
|
Removed top 7 bits (of 8) from port B of cell harness_nms_activation_banked.$xor$hardware/v2/nms/synthesis/harness_nms_activation_banked.v:54$449 ($xor).
|
|
Removed top 24 bits (of 32) from mux cell harness_nms_activation_banked.$procmux$806 ($mux).
|
|
Removed cell harness_nms_activation_banked.$flatten\dut.$procmux$884 ($mux).
|
|
Removed top 29 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$841 ($mux).
|
|
Removed top 29 bits (of 32) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$830 ($mux).
|
|
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$820 ($pmux).
|
|
Removed top 56 bits (of 64) from mux cell harness_nms_activation_banked.$flatten\dut.$procmux$817 ($pmux).
|
|
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$752 ($shiftx).
|
|
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749 ($add).
|
|
Removed top 31 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$741 ($shiftx).
|
|
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$722 ($shiftx).
|
|
Removed top 31 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$719 ($add).
|
|
Removed top 31 bits (of 32) from port Y of cell harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$719 ($add).
|
|
Removed top 30 bits (of 32) from port B of cell harness_nms_activation_banked.$flatten\dut.$shiftx$hardware/v2/nms/rtl/nms_activation_banked.v:104$711 ($shiftx).
|
|
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1063 ($dffe).
|
|
Removed top 56 bits (of 64) from FF cell harness_nms_activation_banked.$auto$ff.cc:337:slice$1060 ($dffe).
|
|
Removed top 29 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[0].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$687_ADDR[31:0]$777.
|
|
Removed top 29 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$0$memwr$\GEN_BANK[1].mem$hardware/v2/nms/rtl/nms_activation_banked.v:70$688_ADDR[31:0]$789.
|
|
Removed top 31 bits (of 32) from wire harness_nms_activation_banked.$flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749_Y.
|
|
Removed top 1 bits (of 2) from wire harness_nms_activation_banked.ack.
|
|
Removed top 56 bits (of 128) from wire harness_nms_activation_banked.rd_data_flat.
|
|
Removed top 24 bits (of 32) from wire harness_nms_activation_banked.$0\lfsr[31:0].
|
|
|
|
4.16. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 10 unused cells and 18 unused wires.
|
|
<suppressed ~11 debug messages>
|
|
|
|
4.18. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
4.19. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.19.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
4.20. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.22. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.22.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.23. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
|
|
Generating RTLIL representation for module `$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.23.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
4.24. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module harness_nms_activation_banked:
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$770 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$772 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$719 ($add).
|
|
creating $macc model for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749 ($add).
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$719.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$772.
|
|
creating $alu model for $macc $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$770.
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$770: $auto$alumacc.cc:548:replace_alu$1076
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:141$772: $auto$alumacc.cc:548:replace_alu$1079
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$719: $auto$alumacc.cc:548:replace_alu$1082
|
|
creating $alu cell for $flatten\dut.$add$hardware/v2/nms/rtl/nms_activation_banked.v:103$749: $auto$alumacc.cc:548:replace_alu$1085
|
|
created 4 $alu and 0 $macc cells.
|
|
|
|
4.25. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.25.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.25.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 86 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~52 debug messages>
|
|
|
|
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Performed a total of 0 changes.
|
|
|
|
4.25.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 86 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.25.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.26. Executing MEMORY pass.
|
|
|
|
4.26.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
Analyzing harness_nms_activation_banked.dut.GEN_BANK[0].mem write port 0.
|
|
Analyzing harness_nms_activation_banked.dut.GEN_BANK[1].mem write port 0.
|
|
|
|
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
|
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\dut.GEN_BANK[0].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
|
|
Write port 0: don't care on collision.
|
|
Checking read port `\dut.GEN_BANK[1].mem'[0] in module `\harness_nms_activation_banked': merging output FF to cell.
|
|
Write port 0: non-transparent.
|
|
|
|
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 2 unused cells and 16 unused wires.
|
|
<suppressed ~3 debug messages>
|
|
|
|
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
|
|
mapping memory harness_nms_activation_banked.dut.GEN_BANK[0].mem via $__TRELLIS_DPR16X4_
|
|
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[0].mem: $\dut.GEN_BANK[0].mem$rdreg[0]
|
|
mapping memory harness_nms_activation_banked.dut.GEN_BANK[1].mem via $__TRELLIS_DPR16X4_
|
|
Extracted data FF from read port 0 of harness_nms_activation_banked.dut.GEN_BANK[1].mem: $\dut.GEN_BANK[1].mem$rdreg[0]
|
|
<suppressed ~901 debug messages>
|
|
|
|
4.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DP16KD_'.
|
|
Generating RTLIL representation for module `$__PDPW16KD_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.29.3. Continuing TECHMAP pass.
|
|
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
|
|
No more expansions possible.
|
|
<suppressed ~50 debug messages>
|
|
|
|
4.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~79 debug messages>
|
|
|
|
4.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 105 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 8 unused cells and 245 unused wires.
|
|
<suppressed ~9 debug messages>
|
|
|
|
4.30.5. Finished fast OPT passes.
|
|
|
|
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
4.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 97 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
Evaluating internal representation of mux trees.
|
|
Analyzing evaluation results.
|
|
Removed 0 multiplexer ports.
|
|
<suppressed ~34 debug messages>
|
|
|
|
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Performed a total of 0 changes.
|
|
|
|
4.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 97 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.32.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ccu2c_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $sdffe.
|
|
Using extmapper simplemap for cells of type $sdff.
|
|
Using extmapper simplemap for cells of type $reduce_or.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $eq.
|
|
Using extmapper simplemap for cells of type $logic_not.
|
|
Using template $paramod$constmap:51907c5a9e82c5604e3c8d2219fec4022d62e6a0$paramod$24ada137f3c8fa165ac5de443ed63450859b7f92\_90_shift_shiftx for cells of type $shiftx.
|
|
Using extmapper simplemap for cells of type $dffe.
|
|
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
|
|
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
Using extmapper simplemap for cells of type $or.
|
|
Using extmapper simplemap for cells of type $and.
|
|
No more expansions possible.
|
|
<suppressed ~482 debug messages>
|
|
|
|
4.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~62 debug messages>
|
|
|
|
4.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 338 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Computing hashes of 330 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
<suppressed ~24 debug messages>
|
|
Removed a total of 8 cells.
|
|
|
|
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 147 unused cells and 196 unused wires.
|
|
<suppressed ~148 debug messages>
|
|
|
|
4.34.5. Finished fast OPT passes.
|
|
|
|
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
4.37. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 183 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.38. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.38.2. Continuing TECHMAP pass.
|
|
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
|
|
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
|
|
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
|
|
Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
|
|
No more expansions possible.
|
|
<suppressed ~163 debug messages>
|
|
|
|
4.39. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
4.41. Executing LATTICE_GSR pass (implement FF init values).
|
|
Handling GSR in harness_nms_activation_banked.
|
|
|
|
4.42. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
Removed 0 unused cells and 345 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.44. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_activation_banked...
|
|
Found and reported 0 problems.
|
|
|
|
4.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
4.46. Executing ABC9 pass.
|
|
|
|
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.3. Executing PROC pass (convert processes to netlists).
|
|
|
|
4.46.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1921'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
4.46.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
|
|
Marked 1 switch rules as full_case in process $proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Removed a total of 0 dead cases.
|
|
|
|
4.46.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
|
|
Removed 0 redundant assignments.
|
|
Promoted 22 assignments to connections.
|
|
|
|
4.46.3.4. Executing PROC_INIT pass (extract init attributes).
|
|
|
|
4.46.3.5. Executing PROC_ARST pass (detect async resets in processes).
|
|
|
|
4.46.3.6. Executing PROC_ROM pass (convert switches to ROMs).
|
|
Converted 0 switches.
|
|
<suppressed ~1 debug messages>
|
|
|
|
4.46.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
1/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_EN[3:0]$1928
|
|
2/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_DATA[3:0]$1927
|
|
3/3: $1$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_ADDR[3:0]$1926
|
|
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1921'.
|
|
|
|
4.46.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1904_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1905_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1906_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1907_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1908_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1909_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1910_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1911_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1912_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1913_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1914_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1915_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1916_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1917_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1918_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:145$1919_EN' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
No latch inferred for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' from process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1921'.
|
|
|
|
4.46.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
created $dff cell `$procdff$1972' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
created $dff cell `$procdff$1973' with positive edge clock.
|
|
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:161$1920_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
created $dff cell `$procdff$1974' with positive edge clock.
|
|
|
|
4.46.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
4.46.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:143$1946'.
|
|
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:159$1922'.
|
|
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/opt/homebrew/bin/../share/yosys/lattice/common_sim.vh:151$1921'.
|
|
Cleaned up 1 empty switch.
|
|
|
|
4.46.4. Executing SCC pass (detecting logic loops).
|
|
Found 0 SCCs in module harness_nms_activation_banked.
|
|
Found 0 SCCs.
|
|
|
|
4.46.5. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.6. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.6.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.6.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~167 debug messages>
|
|
|
|
4.46.7. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.46.7.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
4.46.7.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.46.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Performed a total of 0 changes.
|
|
|
|
4.46.7.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Computing hashes of 2 cells of `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Finding duplicate cells in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.7.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.46.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
|
|
|
|
4.46.7.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
|
|
4.46.7.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.46.8. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.8.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.8.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
No more expansions possible.
|
|
<suppressed ~7 debug messages>
|
|
|
|
4.46.9. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
|
|
Generating RTLIL representation for module `$__ABC9_DELAY'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.12. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
<suppressed ~2 debug messages>
|
|
|
|
4.46.13. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `$__div_mod_u'.
|
|
Generating RTLIL representation for module `$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Generating RTLIL representation for module `$connect'.
|
|
Generating RTLIL representation for module `$input_port'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.13.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~171 debug messages>
|
|
|
|
4.46.14. Executing OPT pass (performing simple optimizations).
|
|
|
|
4.46.14.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.46.14.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \harness_nms_activation_banked..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
4.46.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \harness_nms_activation_banked.
|
|
Performed a total of 0 changes.
|
|
|
|
4.46.14.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\harness_nms_activation_banked'.
|
|
Computing hashes of 0 cells of `\harness_nms_activation_banked'.
|
|
Finding duplicate cells in `\harness_nms_activation_banked'.
|
|
Removed a total of 0 cells.
|
|
|
|
4.46.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
4.46.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \harness_nms_activation_banked..
|
|
|
|
4.46.14.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module harness_nms_activation_banked.
|
|
|
|
4.46.14.9. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
|
4.46.15. Executing AIGMAP pass (map logic to AIG).
|
|
|
|
4.46.16. Executing AIGMAP pass (map logic to AIG).
|
|
Module harness_nms_activation_banked: replaced 91 cells with 625 new cells, skipped 96 cells.
|
|
replaced 3 cell types:
|
|
63 $_MUX_
|
|
4 $_OR_
|
|
24 $_XOR_
|
|
not replaced 6 cell types:
|
|
7 $_AND_
|
|
10 $_NOT_
|
|
1 $scopeinfo
|
|
70 TRELLIS_FF
|
|
4 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
|
|
4 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
|
|
|
|
4.46.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
|
|
|
|
4.46.16.3. Executing XAIGER backend.
|
|
<suppressed ~11 debug messages>
|
|
Extracted 272 AND gates and 812 wires from module `harness_nms_activation_banked' to a netlist network with 96 inputs and 92 outputs.
|
|
|
|
4.46.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
|
|
|
|
4.46.16.5. Executing ABC9.
|
|
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
|
|
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
|
ABC: + read_lut <abc-temp-dir>/input.lut
|
|
ABC: + read_box <abc-temp-dir>/input.box
|
|
ABC: + &read <abc-temp-dir>/input.xaig
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 96/ 92 and = 244 lev = 11 (1.18) mem = 0.01 MB box = 4 bb = 4
|
|
ABC: + &scorr
|
|
ABC: Warning: The network is combinational.
|
|
ABC: + &sweep
|
|
ABC: + &dc2
|
|
ABC: + &dch -f -r
|
|
ABC: + &ps
|
|
ABC: <abc-temp-dir>/input : i/o = 96/ 92 and = 319 lev = 10 (0.88) mem = 0.01 MB ch = 47 box = 4 bb = 4
|
|
ABC: cst = 0 cls = 46 lit = 47 unused = 338 proof = 0
|
|
ABC: + &if -W 300 -v
|
|
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
|
|
ABC: Node = 319. Ch = 46. Total mem = 0.09 MB. Peak cut mem = 0.01 MB.
|
|
ABC: P: Del = 1457.00. Ar = 47.0. Edge = 115. Cut = 6113. T = 0.00 sec
|
|
ABC: P: Del = 1457.00. Ar = 47.0. Edge = 115. Cut = 6113. T = 0.00 sec
|
|
ABC: P: Del = 1457.00. Ar = 47.0. Edge = 136. Cut = 6826. T = 0.00 sec
|
|
ABC: F: Del = 1457.00. Ar = 46.0. Edge = 116. Cut = 5648. T = 0.00 sec
|
|
ABC: A: Del = 1457.00. Ar = 46.0. Edge = 111. Cut = 6357. T = 0.00 sec
|
|
ABC: A: Del = 1457.00. Ar = 46.0. Edge = 111. Cut = 6357. T = 0.00 sec
|
|
ABC: Total time = 0.00 sec
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &mfs
|
|
ABC: The network is not changed by "&mfs".
|
|
ABC: + &ps -l
|
|
ABC: <abc-temp-dir>/input : i/o = 96/ 92 and = 213 lev = 10 (0.88) mem = 0.01 MB box = 4 bb = 4
|
|
ABC: Mapping (K=6) : lut = 29 edge = 111 lev = 2 (0.27) levB = 2 mem = 0.00 MB
|
|
ABC: LUT = 29 : 2=6 20.7 % 3=8 27.6 % 4=2 6.9 % 5=11 37.9 % 6=2 6.9 % Ave = 3.83
|
|
ABC: + &write -n <abc-temp-dir>/output.aig
|
|
ABC: + &verify
|
|
ABC: Networks are equivalent. Time = 0.01 sec
|
|
ABC: + time
|
|
ABC: elapse: 0.02 seconds, total: 0.02 seconds
|
|
|
|
4.46.16.6. Executing AIGER frontend.
|
|
<suppressed ~10 debug messages>
|
|
Removed 376 unused cells and 565 unused wires.
|
|
|
|
4.46.16.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
|
|
ABC RESULTS: $lut cells: 30
|
|
ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 4
|
|
ABC RESULTS: input signals: 18
|
|
ABC RESULTS: output signals: 22
|
|
<suppressed ~376 debug messages>
|
|
Removing temp directory.
|
|
|
|
4.46.17. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.46.17.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
|
|
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
|
|
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.46.17.2. Continuing TECHMAP pass.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
|
|
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
|
|
No more expansions possible.
|
|
<suppressed ~15 debug messages>
|
|
Removed 16 unused cells and 967 unused wires.
|
|
|
|
4.47. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
|
|
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
|
|
Generating RTLIL representation for module `$_DFF_N_'.
|
|
Generating RTLIL representation for module `$_DFF_P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
4.47.2. Continuing TECHMAP pass.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
|
|
Using template $paramod$f384ddd9012b2059528f317bbb3723aac50278ce$lut for cells of type $lut.
|
|
Using template $paramod$e2840825a5decb9384733f0751b07380bebda48b$lut for cells of type $lut.
|
|
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
|
|
Using template $paramod$26485d3a30ca73c33c123d5cfc6e1b79b11ecbc1$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
|
|
Using template $paramod$ecabd750cf85d4141a7e44321afac862f85a556c$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
|
|
Using template $paramod$2e91a959072d87efe97818229eac97bc26f6904d$lut for cells of type $lut.
|
|
Using template $paramod$ee2c0b855f3c034b933530466d6ab144dc0dfb85$lut for cells of type $lut.
|
|
Using template $paramod$e6a4aac14b366f7770f6afc50867b3b8176ebb96$lut for cells of type $lut.
|
|
Using template $paramod$34130a2583c0530ca8b8853e64a2a0ddd2e81d2e$lut for cells of type $lut.
|
|
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
|
|
Using template $paramod$effdb7ee88b3986f5c6e21adfd10122f4d64c622$lut for cells of type $lut.
|
|
No more expansions possible.
|
|
<suppressed ~309 debug messages>
|
|
|
|
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in harness_nms_activation_banked.
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $abc$3381$lut$aiger3380$163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$3391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
|
|
Removed 0 unused cells and 58 unused wires.
|
|
|
|
4.49. Executing AUTONAME pass.
|
|
Renamed 176 objects in module harness_nms_activation_banked.
|
|
<suppressed ~176 debug messages>
|
|
|
|
4.50. Executing HIERARCHY pass (managing design hierarchy).
|
|
Attribute `top' found on module `harness_nms_activation_banked'. Setting top module to harness_nms_activation_banked.
|
|
|
|
4.50.1. Analyzing design hierarchy..
|
|
Top module: \harness_nms_activation_banked
|
|
|
|
4.50.2. Analyzing design hierarchy..
|
|
Top module: \harness_nms_activation_banked
|
|
Removed 0 unused modules.
|
|
|
|
4.51. Printing statistics.
|
|
|
|
=== harness_nms_activation_banked ===
|
|
|
|
+----------Local Count, excluding submodules.
|
|
|
|
|
95 wires
|
|
1036 wire bits
|
|
95 public wires
|
|
1036 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
1 cells
|
|
1 $scopeinfo
|
|
136 submodules
|
|
2 L6MUX21
|
|
46 LUT4
|
|
15 PFUMX
|
|
4 TRELLIS_DPR16X4
|
|
69 TRELLIS_FF
|
|
|
|
=== design hierarchy ===
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
1 harness_nms_activation_banked
|
|
|
|
+----------Count including submodules.
|
|
|
|
|
95 wires
|
|
1036 wire bits
|
|
95 public wires
|
|
1036 public wire bits
|
|
4 ports
|
|
18 port bits
|
|
- memories
|
|
- memory bits
|
|
- processes
|
|
1 cells
|
|
1 $scopeinfo
|
|
136 submodules
|
|
2 L6MUX21
|
|
46 LUT4
|
|
15 PFUMX
|
|
4 TRELLIS_DPR16X4
|
|
69 TRELLIS_FF
|
|
|
|
4.52. Executing CHECK pass (checking for obvious problems).
|
|
Checking module harness_nms_activation_banked...
|
|
Found and reported 0 problems.
|
|
|
|
4.53. Executing JSON backend.
|
|
|
|
Warnings: 12 unique messages, 22 total
|
|
End of script. Logfile hash: b822c28c43, time: 0.33s, user: 0.28s, system: 0.01s, MEM: 35.12 MB peak
|
|
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
|
|
Time spent: 60% 22x read_verilog (0 sec), 10% 1x abc9_exe (0 sec), ...
|