micheleandClaude Sonnet 5
175f697ae1
Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
47 lines
2.4 KiB
Plaintext
47 lines
2.4 KiB
Plaintext
# V2 timing log -- solo append, mai troncato/sovrascritto (vedi README.md)
|
|
# Nessuna entry ancora -- popolato incrementalmente man mano che avanza lo sviluppo V2.
|
|
|
|
[2026-09-05] EXP-0001 -- neural_processor (P_IN=8, ACC_WIDTH=32)
|
|
nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80
|
|
--lpf-allow-unconstrained
|
|
Fmax: 183.12 MHz -- PASS at 80 MHz (real place&route measurement)
|
|
Critical path: job_ready -> TRELLIS_IO output pad (i.e. the design's
|
|
own logic is NOT the bottleneck at this Fmax -- an unconstrained
|
|
output pin dominates; a real system-level Fmax will differ once
|
|
this signal is consumed on-chip instead of driven to a pad in
|
|
isolation). Log: hardware/v2/synthesis/neural_processor_p8/nextpnr.log
|
|
WNS/TNS: not reported by this nextpnr version in this invocation.
|
|
|
|
[2026-09-05] EXP-0002 -- neural_processor (P_IN=8, ACC_WIDTH=24)
|
|
Same command as above, ACC_WIDTH=24 build.
|
|
Fmax: 176.21 MHz -- PASS at 80 MHz (real place&route measurement)
|
|
Delta vs ACC_WIDTH=32: -6.91 MHz (-3.8%) despite FEWER resources --
|
|
attributed to placement noise, not a real architectural effect
|
|
(no seed sweep run to confirm either way -- see experiments.log
|
|
EXP-0002 and benchmark.log). Log: hardware/v2/synthesis/
|
|
neural_processor_p8_acc24/nextpnr.log
|
|
|
|
[2026-09-05] EXP-0003 -- N_PROCESSORS sweep (P_IN=8), real nextpnr-ecp5
|
|
--45k --package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
|
|
N=1: Fmax=159.11 MHz PASS MULT18X18D 8/72 (11%)
|
|
N=2: Fmax=149.59 MHz PASS MULT18X18D 16/72 (22%)
|
|
N=4: Fmax=151.01 MHz PASS MULT18X18D 32/72 (44%)
|
|
N=8: Fmax=134.70 MHz PASS MULT18X18D 64/72 (88%)
|
|
TRELLIS_IO stays at 18/245 (7%) throughout (harness has only
|
|
clk/rst/seed/checksum as real pins, by design -- see ERR-0005).
|
|
See decisions.log DEC-0005: DSP, not Fmax or LUT/FF, is the resource
|
|
that will first prevent scaling N_PROCESSORS further at P_IN=8.
|
|
|
|
[2026-09-05] EXP-0004 -- default-depth buffer configs, real nextpnr-ecp5
|
|
activation_buffer (D=4096): Fmax=325.20 MHz PASS
|
|
weight_buffer (D=512): Fmax=339.67 MHz PASS
|
|
result_buffer (D=4096): Fmax=325.20 MHz PASS
|
|
All far above the 80MHz target -- buffers are not a timing concern in
|
|
isolation at these depths.
|
|
|
|
[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (via
|
|
harness_memory_manager.v, see errors.log ERR-0005 for why a harness
|
|
was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8
|
|
--freq 80 --lpf-allow-unconstrained
|
|
Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement)
|