3522 lines
88 KiB
Plaintext
3522 lines
88 KiB
Plaintext
$date
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Wed Sep 2 11:12:31 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb $end
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$var wire 32 ! y_bus [31:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 32 % DATA_WIDTH $end
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$var parameter 32 & N_INPUTS $end
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$var parameter 32 ' N_NEURONS $end
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$var parameter 32 ( PARALLEL $end
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$var reg 32 ) bias_bus [31:0] $end
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$var reg 1 * clk $end
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$var reg 1 + rst $end
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$var reg 1 , start $end
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$var reg 8192 - weights_bus [8191:0] $end
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$var reg 2048 . x_bus [2047:0] $end
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$var integer 32 / errors [31:0] $end
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$var integer 32 0 expected [31:0] $end
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$var integer 32 1 i [31:0] $end
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$scope module dut $end
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$var wire 32 2 bias_bus [31:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 8192 3 weights_bus [8191:0] $end
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$var wire 2048 4 x_bus [2047:0] $end
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$var wire 32 5 y_bus [31:0] $end
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$var wire 4 6 neuron_done [3:0] $end
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$var wire 4 7 neuron_busy [3:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 8 ACC_WIDTH $end
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$var parameter 32 9 DATA_WIDTH $end
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$var parameter 32 : N_INPUTS $end
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$var parameter 32 ; N_NEURONS $end
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$var parameter 32 < PARALLEL $end
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$scope begin GEN_NEURON[0] $end
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$var parameter 2 = n $end
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$scope module u_neuron $end
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$var wire 8 > bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 2048 ? w_bus [2047:0] $end
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$var wire 2048 @ x_bus [2047:0] $end
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$var wire 128 A x_group [127:0] $end
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$var wire 128 B w_group [127:0] $end
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$var wire 32 C final_acc [31:0] $end
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$var wire 32 D bias_ext [31:0] $end
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$var wire 32 E acc_next [31:0] $end
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$var parameter 32 F ACC_WIDTH $end
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$var parameter 32 G DATA_WIDTH $end
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$var parameter 32 H GROUPS $end
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$var parameter 32 I GROUP_INDEX_WIDTH $end
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$var parameter 32 J N_INPUTS $end
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$var parameter 32 K PARALLEL $end
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$var reg 32 L acc [31:0] $end
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$var reg 1 M busy $end
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$var reg 1 N done $end
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$var reg 4 O group_index [3:0] $end
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$var reg 8 P y [7:0] $end
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$scope module u_mac8 $end
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$var wire 32 Q acc_in [31:0] $end
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$var wire 128 R w_bus [127:0] $end
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$var wire 128 S x_bus [127:0] $end
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$var wire 32 T acc_out [31:0] $end
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$var parameter 32 U ACC_WIDTH $end
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$var parameter 32 V DATA_WIDTH $end
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$var parameter 32 W PARALLEL $end
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$var parameter 32 X TREE_LEVELS $end
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$scope begin GEN_MAC[0] $end
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$var parameter 2 Y i $end
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$scope module u_mac $end
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$var wire 32 Z acc_in [31:0] $end
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$var wire 8 [ w [7:0] $end
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$var wire 8 \ x [7:0] $end
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$var wire 32 ] product_ext [31:0] $end
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$var wire 16 ^ product [15:0] $end
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$var wire 32 _ acc_out [31:0] $end
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$var parameter 32 ` ACC_WIDTH $end
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$var parameter 32 a DATA_WIDTH $end
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$var parameter 64 b PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[1] $end
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$var parameter 2 c i $end
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$scope module u_mac $end
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$var wire 32 d acc_in [31:0] $end
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$var wire 8 e w [7:0] $end
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$var wire 8 f x [7:0] $end
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$var wire 32 g product_ext [31:0] $end
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$var wire 16 h product [15:0] $end
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$var wire 32 i acc_out [31:0] $end
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$var parameter 32 j ACC_WIDTH $end
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$var parameter 32 k DATA_WIDTH $end
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$var parameter 64 l PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[2] $end
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$var parameter 3 m i $end
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$scope module u_mac $end
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$var wire 32 n acc_in [31:0] $end
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$var wire 8 o w [7:0] $end
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$var wire 8 p x [7:0] $end
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$var wire 32 q product_ext [31:0] $end
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$var wire 16 r product [15:0] $end
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$var wire 32 s acc_out [31:0] $end
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$var parameter 32 t ACC_WIDTH $end
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$var parameter 32 u DATA_WIDTH $end
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$var parameter 64 v PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[3] $end
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$var parameter 3 w i $end
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$scope module u_mac $end
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$var wire 32 x acc_in [31:0] $end
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$var wire 8 y w [7:0] $end
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$var wire 8 z x [7:0] $end
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$var wire 32 { product_ext [31:0] $end
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$var wire 16 | product [15:0] $end
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$var wire 32 } acc_out [31:0] $end
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$var parameter 32 ~ ACC_WIDTH $end
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$var parameter 32 !" DATA_WIDTH $end
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$var parameter 64 "" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[4] $end
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$var parameter 4 #" i $end
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$scope module u_mac $end
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$var wire 32 $" acc_in [31:0] $end
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$var wire 8 %" w [7:0] $end
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$var wire 8 &" x [7:0] $end
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$var wire 32 '" product_ext [31:0] $end
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$var wire 16 (" product [15:0] $end
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$var wire 32 )" acc_out [31:0] $end
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$var parameter 32 *" ACC_WIDTH $end
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$var parameter 32 +" DATA_WIDTH $end
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$var parameter 64 ," PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[5] $end
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$var parameter 4 -" i $end
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$scope module u_mac $end
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$var wire 32 ." acc_in [31:0] $end
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$var wire 8 /" w [7:0] $end
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$var wire 8 0" x [7:0] $end
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$var wire 32 1" product_ext [31:0] $end
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$var wire 16 2" product [15:0] $end
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$var wire 32 3" acc_out [31:0] $end
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$var parameter 32 4" ACC_WIDTH $end
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$var parameter 32 5" DATA_WIDTH $end
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$var parameter 64 6" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[6] $end
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$var parameter 4 7" i $end
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$scope module u_mac $end
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$var wire 32 8" acc_in [31:0] $end
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$var wire 8 9" w [7:0] $end
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$var wire 8 :" x [7:0] $end
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$var wire 32 ;" product_ext [31:0] $end
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$var wire 16 <" product [15:0] $end
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$var wire 32 =" acc_out [31:0] $end
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$var parameter 32 >" ACC_WIDTH $end
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$var parameter 32 ?" DATA_WIDTH $end
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$var parameter 64 @" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[7] $end
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$var parameter 4 A" i $end
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$scope module u_mac $end
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$var wire 32 B" acc_in [31:0] $end
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$var wire 8 C" w [7:0] $end
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$var wire 8 D" x [7:0] $end
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$var wire 32 E" product_ext [31:0] $end
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$var wire 16 F" product [15:0] $end
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$var wire 32 G" acc_out [31:0] $end
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$var parameter 32 H" ACC_WIDTH $end
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$var parameter 32 I" DATA_WIDTH $end
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$var parameter 64 J" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[8] $end
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$var parameter 5 K" i $end
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$scope module u_mac $end
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$var wire 32 L" acc_in [31:0] $end
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$var wire 8 M" w [7:0] $end
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$var wire 8 N" x [7:0] $end
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$var wire 32 O" product_ext [31:0] $end
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$var wire 16 P" product [15:0] $end
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$var wire 32 Q" acc_out [31:0] $end
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$var parameter 32 R" ACC_WIDTH $end
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$var parameter 32 S" DATA_WIDTH $end
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$var parameter 64 T" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[9] $end
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$var parameter 5 U" i $end
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$scope module u_mac $end
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$var wire 32 V" acc_in [31:0] $end
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$var wire 8 W" w [7:0] $end
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$var wire 8 X" x [7:0] $end
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$var wire 32 Y" product_ext [31:0] $end
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$var wire 16 Z" product [15:0] $end
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$var wire 32 [" acc_out [31:0] $end
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$var parameter 32 \" ACC_WIDTH $end
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$var parameter 32 ]" DATA_WIDTH $end
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$var parameter 64 ^" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[10] $end
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$var parameter 5 _" i $end
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$scope module u_mac $end
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$var wire 32 `" acc_in [31:0] $end
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$var wire 8 a" w [7:0] $end
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$var wire 8 b" x [7:0] $end
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$var wire 32 c" product_ext [31:0] $end
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$var wire 16 d" product [15:0] $end
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$var wire 32 e" acc_out [31:0] $end
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$var parameter 32 f" ACC_WIDTH $end
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$var parameter 32 g" DATA_WIDTH $end
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$var parameter 64 h" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[11] $end
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$var parameter 5 i" i $end
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$scope module u_mac $end
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$var wire 32 j" acc_in [31:0] $end
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$var wire 8 k" w [7:0] $end
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$var wire 8 l" x [7:0] $end
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$var wire 32 m" product_ext [31:0] $end
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$var wire 16 n" product [15:0] $end
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$var wire 32 o" acc_out [31:0] $end
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$var parameter 32 p" ACC_WIDTH $end
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$var parameter 32 q" DATA_WIDTH $end
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$var parameter 64 r" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[12] $end
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$var parameter 5 s" i $end
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$scope module u_mac $end
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$var wire 32 t" acc_in [31:0] $end
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$var wire 8 u" w [7:0] $end
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$var wire 8 v" x [7:0] $end
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$var wire 32 w" product_ext [31:0] $end
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$var wire 16 x" product [15:0] $end
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$var wire 32 y" acc_out [31:0] $end
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$var parameter 32 z" ACC_WIDTH $end
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$var parameter 32 {" DATA_WIDTH $end
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$var parameter 64 |" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[13] $end
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$var parameter 5 }" i $end
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$scope module u_mac $end
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$var wire 32 ~" acc_in [31:0] $end
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$var wire 8 !# w [7:0] $end
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$var wire 8 "# x [7:0] $end
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$var wire 32 ## product_ext [31:0] $end
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$var wire 16 $# product [15:0] $end
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$var wire 32 %# acc_out [31:0] $end
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$var parameter 32 &# ACC_WIDTH $end
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$var parameter 32 '# DATA_WIDTH $end
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$var parameter 64 (# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[14] $end
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$var parameter 5 )# i $end
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$scope module u_mac $end
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$var wire 32 *# acc_in [31:0] $end
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$var wire 8 +# w [7:0] $end
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$var wire 8 ,# x [7:0] $end
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$var wire 32 -# product_ext [31:0] $end
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$var wire 16 .# product [15:0] $end
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$var wire 32 /# acc_out [31:0] $end
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$var parameter 32 0# ACC_WIDTH $end
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$var parameter 32 1# DATA_WIDTH $end
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$var parameter 64 2# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_MAC[15] $end
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$var parameter 5 3# i $end
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$scope module u_mac $end
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$var wire 32 4# acc_in [31:0] $end
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$var wire 8 5# w [7:0] $end
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$var wire 8 6# x [7:0] $end
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$var wire 32 7# product_ext [31:0] $end
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$var wire 16 8# product [15:0] $end
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$var wire 32 9# acc_out [31:0] $end
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$var parameter 32 :# ACC_WIDTH $end
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$var parameter 32 ;# DATA_WIDTH $end
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$var parameter 64 <# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[0] $end
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$var parameter 2 =# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[1] $end
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$var parameter 2 ># i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[2] $end
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$var parameter 3 ?# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[3] $end
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$var parameter 3 @# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[4] $end
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$var parameter 4 A# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[5] $end
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$var parameter 4 B# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[6] $end
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$var parameter 4 C# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[7] $end
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$var parameter 4 D# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[8] $end
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$var parameter 5 E# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[9] $end
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$var parameter 5 F# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[10] $end
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$var parameter 5 G# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[11] $end
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$var parameter 5 H# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[12] $end
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$var parameter 5 I# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[13] $end
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$var parameter 5 J# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[14] $end
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$var parameter 5 K# i $end
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$upscope $end
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$scope begin GEN_TREE_INPUT[15] $end
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$var parameter 5 L# i $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[0] $end
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$var parameter 2 M# level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 N# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 O# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 P# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 Q# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[4] $end
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$var parameter 4 R# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[5] $end
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$var parameter 4 S# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[6] $end
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$var parameter 4 T# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[7] $end
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$var parameter 4 U# node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[1] $end
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$var parameter 2 V# level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 W# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 X# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[2] $end
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$var parameter 3 Y# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[3] $end
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$var parameter 3 Z# node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[2] $end
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$var parameter 3 [# level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 \# node $end
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$upscope $end
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$scope begin GEN_TREE_NODE[1] $end
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$var parameter 2 ]# node $end
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$upscope $end
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$upscope $end
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$scope begin GEN_TREE_LEVEL[3] $end
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$var parameter 3 ^# level $end
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$scope begin GEN_TREE_NODE[0] $end
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$var parameter 2 _# node $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin GEN_NEURON[1] $end
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$var parameter 2 `# n $end
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$scope module u_neuron $end
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$var wire 8 a# bias [7:0] $end
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$var wire 1 * clk $end
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$var wire 1 + rst $end
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$var wire 1 , start $end
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$var wire 2048 b# w_bus [2047:0] $end
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$var wire 2048 c# x_bus [2047:0] $end
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$var wire 128 d# x_group [127:0] $end
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$var wire 128 e# w_group [127:0] $end
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$var wire 32 f# final_acc [31:0] $end
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$var wire 32 g# bias_ext [31:0] $end
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$var wire 32 h# acc_next [31:0] $end
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$var parameter 32 i# ACC_WIDTH $end
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$var parameter 32 j# DATA_WIDTH $end
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$var parameter 32 k# GROUPS $end
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$var parameter 32 l# GROUP_INDEX_WIDTH $end
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$var parameter 32 m# N_INPUTS $end
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$var parameter 32 n# PARALLEL $end
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$var reg 32 o# acc [31:0] $end
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$var reg 1 p# busy $end
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$var reg 1 q# done $end
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$var reg 4 r# group_index [3:0] $end
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$var reg 8 s# y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 t# acc_in [31:0] $end
|
|
$var wire 128 u# w_bus [127:0] $end
|
|
$var wire 128 v# x_bus [127:0] $end
|
|
$var wire 32 w# acc_out [31:0] $end
|
|
$var parameter 32 x# ACC_WIDTH $end
|
|
$var parameter 32 y# DATA_WIDTH $end
|
|
$var parameter 32 z# PARALLEL $end
|
|
$var parameter 32 {# TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 |# i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 }# acc_in [31:0] $end
|
|
$var wire 8 ~# w [7:0] $end
|
|
$var wire 8 !$ x [7:0] $end
|
|
$var wire 32 "$ product_ext [31:0] $end
|
|
$var wire 16 #$ product [15:0] $end
|
|
$var wire 32 $$ acc_out [31:0] $end
|
|
$var parameter 32 %$ ACC_WIDTH $end
|
|
$var parameter 32 &$ DATA_WIDTH $end
|
|
$var parameter 64 '$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 ($ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 )$ acc_in [31:0] $end
|
|
$var wire 8 *$ w [7:0] $end
|
|
$var wire 8 +$ x [7:0] $end
|
|
$var wire 32 ,$ product_ext [31:0] $end
|
|
$var wire 16 -$ product [15:0] $end
|
|
$var wire 32 .$ acc_out [31:0] $end
|
|
$var parameter 32 /$ ACC_WIDTH $end
|
|
$var parameter 32 0$ DATA_WIDTH $end
|
|
$var parameter 64 1$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 2$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 3$ acc_in [31:0] $end
|
|
$var wire 8 4$ w [7:0] $end
|
|
$var wire 8 5$ x [7:0] $end
|
|
$var wire 32 6$ product_ext [31:0] $end
|
|
$var wire 16 7$ product [15:0] $end
|
|
$var wire 32 8$ acc_out [31:0] $end
|
|
$var parameter 32 9$ ACC_WIDTH $end
|
|
$var parameter 32 :$ DATA_WIDTH $end
|
|
$var parameter 64 ;$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 <$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 =$ acc_in [31:0] $end
|
|
$var wire 8 >$ w [7:0] $end
|
|
$var wire 8 ?$ x [7:0] $end
|
|
$var wire 32 @$ product_ext [31:0] $end
|
|
$var wire 16 A$ product [15:0] $end
|
|
$var wire 32 B$ acc_out [31:0] $end
|
|
$var parameter 32 C$ ACC_WIDTH $end
|
|
$var parameter 32 D$ DATA_WIDTH $end
|
|
$var parameter 64 E$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 F$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 G$ acc_in [31:0] $end
|
|
$var wire 8 H$ w [7:0] $end
|
|
$var wire 8 I$ x [7:0] $end
|
|
$var wire 32 J$ product_ext [31:0] $end
|
|
$var wire 16 K$ product [15:0] $end
|
|
$var wire 32 L$ acc_out [31:0] $end
|
|
$var parameter 32 M$ ACC_WIDTH $end
|
|
$var parameter 32 N$ DATA_WIDTH $end
|
|
$var parameter 64 O$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 P$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 Q$ acc_in [31:0] $end
|
|
$var wire 8 R$ w [7:0] $end
|
|
$var wire 8 S$ x [7:0] $end
|
|
$var wire 32 T$ product_ext [31:0] $end
|
|
$var wire 16 U$ product [15:0] $end
|
|
$var wire 32 V$ acc_out [31:0] $end
|
|
$var parameter 32 W$ ACC_WIDTH $end
|
|
$var parameter 32 X$ DATA_WIDTH $end
|
|
$var parameter 64 Y$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 Z$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 [$ acc_in [31:0] $end
|
|
$var wire 8 \$ w [7:0] $end
|
|
$var wire 8 ]$ x [7:0] $end
|
|
$var wire 32 ^$ product_ext [31:0] $end
|
|
$var wire 16 _$ product [15:0] $end
|
|
$var wire 32 `$ acc_out [31:0] $end
|
|
$var parameter 32 a$ ACC_WIDTH $end
|
|
$var parameter 32 b$ DATA_WIDTH $end
|
|
$var parameter 64 c$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 d$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e$ acc_in [31:0] $end
|
|
$var wire 8 f$ w [7:0] $end
|
|
$var wire 8 g$ x [7:0] $end
|
|
$var wire 32 h$ product_ext [31:0] $end
|
|
$var wire 16 i$ product [15:0] $end
|
|
$var wire 32 j$ acc_out [31:0] $end
|
|
$var parameter 32 k$ ACC_WIDTH $end
|
|
$var parameter 32 l$ DATA_WIDTH $end
|
|
$var parameter 64 m$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 n$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o$ acc_in [31:0] $end
|
|
$var wire 8 p$ w [7:0] $end
|
|
$var wire 8 q$ x [7:0] $end
|
|
$var wire 32 r$ product_ext [31:0] $end
|
|
$var wire 16 s$ product [15:0] $end
|
|
$var wire 32 t$ acc_out [31:0] $end
|
|
$var parameter 32 u$ ACC_WIDTH $end
|
|
$var parameter 32 v$ DATA_WIDTH $end
|
|
$var parameter 64 w$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 x$ i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y$ acc_in [31:0] $end
|
|
$var wire 8 z$ w [7:0] $end
|
|
$var wire 8 {$ x [7:0] $end
|
|
$var wire 32 |$ product_ext [31:0] $end
|
|
$var wire 16 }$ product [15:0] $end
|
|
$var wire 32 ~$ acc_out [31:0] $end
|
|
$var parameter 32 !% ACC_WIDTH $end
|
|
$var parameter 32 "% DATA_WIDTH $end
|
|
$var parameter 64 #% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 $% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %% acc_in [31:0] $end
|
|
$var wire 8 &% w [7:0] $end
|
|
$var wire 8 '% x [7:0] $end
|
|
$var wire 32 (% product_ext [31:0] $end
|
|
$var wire 16 )% product [15:0] $end
|
|
$var wire 32 *% acc_out [31:0] $end
|
|
$var parameter 32 +% ACC_WIDTH $end
|
|
$var parameter 32 ,% DATA_WIDTH $end
|
|
$var parameter 64 -% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 .% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 /% acc_in [31:0] $end
|
|
$var wire 8 0% w [7:0] $end
|
|
$var wire 8 1% x [7:0] $end
|
|
$var wire 32 2% product_ext [31:0] $end
|
|
$var wire 16 3% product [15:0] $end
|
|
$var wire 32 4% acc_out [31:0] $end
|
|
$var parameter 32 5% ACC_WIDTH $end
|
|
$var parameter 32 6% DATA_WIDTH $end
|
|
$var parameter 64 7% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 8% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 9% acc_in [31:0] $end
|
|
$var wire 8 :% w [7:0] $end
|
|
$var wire 8 ;% x [7:0] $end
|
|
$var wire 32 <% product_ext [31:0] $end
|
|
$var wire 16 =% product [15:0] $end
|
|
$var wire 32 >% acc_out [31:0] $end
|
|
$var parameter 32 ?% ACC_WIDTH $end
|
|
$var parameter 32 @% DATA_WIDTH $end
|
|
$var parameter 64 A% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 B% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 C% acc_in [31:0] $end
|
|
$var wire 8 D% w [7:0] $end
|
|
$var wire 8 E% x [7:0] $end
|
|
$var wire 32 F% product_ext [31:0] $end
|
|
$var wire 16 G% product [15:0] $end
|
|
$var wire 32 H% acc_out [31:0] $end
|
|
$var parameter 32 I% ACC_WIDTH $end
|
|
$var parameter 32 J% DATA_WIDTH $end
|
|
$var parameter 64 K% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 L% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 M% acc_in [31:0] $end
|
|
$var wire 8 N% w [7:0] $end
|
|
$var wire 8 O% x [7:0] $end
|
|
$var wire 32 P% product_ext [31:0] $end
|
|
$var wire 16 Q% product [15:0] $end
|
|
$var wire 32 R% acc_out [31:0] $end
|
|
$var parameter 32 S% ACC_WIDTH $end
|
|
$var parameter 32 T% DATA_WIDTH $end
|
|
$var parameter 64 U% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 V% i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 W% acc_in [31:0] $end
|
|
$var wire 8 X% w [7:0] $end
|
|
$var wire 8 Y% x [7:0] $end
|
|
$var wire 32 Z% product_ext [31:0] $end
|
|
$var wire 16 [% product [15:0] $end
|
|
$var wire 32 \% acc_out [31:0] $end
|
|
$var parameter 32 ]% ACC_WIDTH $end
|
|
$var parameter 32 ^% DATA_WIDTH $end
|
|
$var parameter 64 _% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 `% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 a% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 b% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 c% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 d% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 e% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 f% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 g% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 h% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 i% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 j% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 k% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 l% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 m% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 n% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 o% i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 p% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 q% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 r% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 s% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 t% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 u% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 v% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 w% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 x% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 y% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 z% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 {% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 |% node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 }% node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 ~% level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 !& node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 "& node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 #& level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 $& node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[2] $end
|
|
$var parameter 3 %& n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 && bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 2048 '& w_bus [2047:0] $end
|
|
$var wire 2048 (& x_bus [2047:0] $end
|
|
$var wire 128 )& x_group [127:0] $end
|
|
$var wire 128 *& w_group [127:0] $end
|
|
$var wire 32 +& final_acc [31:0] $end
|
|
$var wire 32 ,& bias_ext [31:0] $end
|
|
$var wire 32 -& acc_next [31:0] $end
|
|
$var parameter 32 .& ACC_WIDTH $end
|
|
$var parameter 32 /& DATA_WIDTH $end
|
|
$var parameter 32 0& GROUPS $end
|
|
$var parameter 32 1& GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 2& N_INPUTS $end
|
|
$var parameter 32 3& PARALLEL $end
|
|
$var reg 32 4& acc [31:0] $end
|
|
$var reg 1 5& busy $end
|
|
$var reg 1 6& done $end
|
|
$var reg 4 7& group_index [3:0] $end
|
|
$var reg 8 8& y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 9& acc_in [31:0] $end
|
|
$var wire 128 :& w_bus [127:0] $end
|
|
$var wire 128 ;& x_bus [127:0] $end
|
|
$var wire 32 <& acc_out [31:0] $end
|
|
$var parameter 32 =& ACC_WIDTH $end
|
|
$var parameter 32 >& DATA_WIDTH $end
|
|
$var parameter 32 ?& PARALLEL $end
|
|
$var parameter 32 @& TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 A& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 B& acc_in [31:0] $end
|
|
$var wire 8 C& w [7:0] $end
|
|
$var wire 8 D& x [7:0] $end
|
|
$var wire 32 E& product_ext [31:0] $end
|
|
$var wire 16 F& product [15:0] $end
|
|
$var wire 32 G& acc_out [31:0] $end
|
|
$var parameter 32 H& ACC_WIDTH $end
|
|
$var parameter 32 I& DATA_WIDTH $end
|
|
$var parameter 64 J& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 K& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 L& acc_in [31:0] $end
|
|
$var wire 8 M& w [7:0] $end
|
|
$var wire 8 N& x [7:0] $end
|
|
$var wire 32 O& product_ext [31:0] $end
|
|
$var wire 16 P& product [15:0] $end
|
|
$var wire 32 Q& acc_out [31:0] $end
|
|
$var parameter 32 R& ACC_WIDTH $end
|
|
$var parameter 32 S& DATA_WIDTH $end
|
|
$var parameter 64 T& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 U& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 V& acc_in [31:0] $end
|
|
$var wire 8 W& w [7:0] $end
|
|
$var wire 8 X& x [7:0] $end
|
|
$var wire 32 Y& product_ext [31:0] $end
|
|
$var wire 16 Z& product [15:0] $end
|
|
$var wire 32 [& acc_out [31:0] $end
|
|
$var parameter 32 \& ACC_WIDTH $end
|
|
$var parameter 32 ]& DATA_WIDTH $end
|
|
$var parameter 64 ^& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 _& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 `& acc_in [31:0] $end
|
|
$var wire 8 a& w [7:0] $end
|
|
$var wire 8 b& x [7:0] $end
|
|
$var wire 32 c& product_ext [31:0] $end
|
|
$var wire 16 d& product [15:0] $end
|
|
$var wire 32 e& acc_out [31:0] $end
|
|
$var parameter 32 f& ACC_WIDTH $end
|
|
$var parameter 32 g& DATA_WIDTH $end
|
|
$var parameter 64 h& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 i& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 j& acc_in [31:0] $end
|
|
$var wire 8 k& w [7:0] $end
|
|
$var wire 8 l& x [7:0] $end
|
|
$var wire 32 m& product_ext [31:0] $end
|
|
$var wire 16 n& product [15:0] $end
|
|
$var wire 32 o& acc_out [31:0] $end
|
|
$var parameter 32 p& ACC_WIDTH $end
|
|
$var parameter 32 q& DATA_WIDTH $end
|
|
$var parameter 64 r& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 s& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 t& acc_in [31:0] $end
|
|
$var wire 8 u& w [7:0] $end
|
|
$var wire 8 v& x [7:0] $end
|
|
$var wire 32 w& product_ext [31:0] $end
|
|
$var wire 16 x& product [15:0] $end
|
|
$var wire 32 y& acc_out [31:0] $end
|
|
$var parameter 32 z& ACC_WIDTH $end
|
|
$var parameter 32 {& DATA_WIDTH $end
|
|
$var parameter 64 |& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 }& i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ~& acc_in [31:0] $end
|
|
$var wire 8 !' w [7:0] $end
|
|
$var wire 8 "' x [7:0] $end
|
|
$var wire 32 #' product_ext [31:0] $end
|
|
$var wire 16 $' product [15:0] $end
|
|
$var wire 32 %' acc_out [31:0] $end
|
|
$var parameter 32 &' ACC_WIDTH $end
|
|
$var parameter 32 '' DATA_WIDTH $end
|
|
$var parameter 64 (' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 )' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 *' acc_in [31:0] $end
|
|
$var wire 8 +' w [7:0] $end
|
|
$var wire 8 ,' x [7:0] $end
|
|
$var wire 32 -' product_ext [31:0] $end
|
|
$var wire 16 .' product [15:0] $end
|
|
$var wire 32 /' acc_out [31:0] $end
|
|
$var parameter 32 0' ACC_WIDTH $end
|
|
$var parameter 32 1' DATA_WIDTH $end
|
|
$var parameter 64 2' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 3' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 4' acc_in [31:0] $end
|
|
$var wire 8 5' w [7:0] $end
|
|
$var wire 8 6' x [7:0] $end
|
|
$var wire 32 7' product_ext [31:0] $end
|
|
$var wire 16 8' product [15:0] $end
|
|
$var wire 32 9' acc_out [31:0] $end
|
|
$var parameter 32 :' ACC_WIDTH $end
|
|
$var parameter 32 ;' DATA_WIDTH $end
|
|
$var parameter 64 <' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 =' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 >' acc_in [31:0] $end
|
|
$var wire 8 ?' w [7:0] $end
|
|
$var wire 8 @' x [7:0] $end
|
|
$var wire 32 A' product_ext [31:0] $end
|
|
$var wire 16 B' product [15:0] $end
|
|
$var wire 32 C' acc_out [31:0] $end
|
|
$var parameter 32 D' ACC_WIDTH $end
|
|
$var parameter 32 E' DATA_WIDTH $end
|
|
$var parameter 64 F' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 G' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 H' acc_in [31:0] $end
|
|
$var wire 8 I' w [7:0] $end
|
|
$var wire 8 J' x [7:0] $end
|
|
$var wire 32 K' product_ext [31:0] $end
|
|
$var wire 16 L' product [15:0] $end
|
|
$var wire 32 M' acc_out [31:0] $end
|
|
$var parameter 32 N' ACC_WIDTH $end
|
|
$var parameter 32 O' DATA_WIDTH $end
|
|
$var parameter 64 P' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 Q' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 R' acc_in [31:0] $end
|
|
$var wire 8 S' w [7:0] $end
|
|
$var wire 8 T' x [7:0] $end
|
|
$var wire 32 U' product_ext [31:0] $end
|
|
$var wire 16 V' product [15:0] $end
|
|
$var wire 32 W' acc_out [31:0] $end
|
|
$var parameter 32 X' ACC_WIDTH $end
|
|
$var parameter 32 Y' DATA_WIDTH $end
|
|
$var parameter 64 Z' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 [' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 \' acc_in [31:0] $end
|
|
$var wire 8 ]' w [7:0] $end
|
|
$var wire 8 ^' x [7:0] $end
|
|
$var wire 32 _' product_ext [31:0] $end
|
|
$var wire 16 `' product [15:0] $end
|
|
$var wire 32 a' acc_out [31:0] $end
|
|
$var parameter 32 b' ACC_WIDTH $end
|
|
$var parameter 32 c' DATA_WIDTH $end
|
|
$var parameter 64 d' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 e' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 f' acc_in [31:0] $end
|
|
$var wire 8 g' w [7:0] $end
|
|
$var wire 8 h' x [7:0] $end
|
|
$var wire 32 i' product_ext [31:0] $end
|
|
$var wire 16 j' product [15:0] $end
|
|
$var wire 32 k' acc_out [31:0] $end
|
|
$var parameter 32 l' ACC_WIDTH $end
|
|
$var parameter 32 m' DATA_WIDTH $end
|
|
$var parameter 64 n' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 o' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 p' acc_in [31:0] $end
|
|
$var wire 8 q' w [7:0] $end
|
|
$var wire 8 r' x [7:0] $end
|
|
$var wire 32 s' product_ext [31:0] $end
|
|
$var wire 16 t' product [15:0] $end
|
|
$var wire 32 u' acc_out [31:0] $end
|
|
$var parameter 32 v' ACC_WIDTH $end
|
|
$var parameter 32 w' DATA_WIDTH $end
|
|
$var parameter 64 x' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 y' i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 z' acc_in [31:0] $end
|
|
$var wire 8 {' w [7:0] $end
|
|
$var wire 8 |' x [7:0] $end
|
|
$var wire 32 }' product_ext [31:0] $end
|
|
$var wire 16 ~' product [15:0] $end
|
|
$var wire 32 !( acc_out [31:0] $end
|
|
$var parameter 32 "( ACC_WIDTH $end
|
|
$var parameter 32 #( DATA_WIDTH $end
|
|
$var parameter 64 $( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 %( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 &( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 '( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 (( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 )( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 *( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 +( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 ,( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 -( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 .( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 /( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 0( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 1( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 2( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 3( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 4( i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 5( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 6( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 7( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 8( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 9( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 :( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 ;( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 <( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 =( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 >( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 ?( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 @( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 A( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 B( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 C( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 D( node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 E( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 F( level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 G( node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[3] $end
|
|
$var parameter 3 H( n $end
|
|
$scope module u_neuron $end
|
|
$var wire 8 I( bias [7:0] $end
|
|
$var wire 1 * clk $end
|
|
$var wire 1 + rst $end
|
|
$var wire 1 , start $end
|
|
$var wire 2048 J( w_bus [2047:0] $end
|
|
$var wire 2048 K( x_bus [2047:0] $end
|
|
$var wire 128 L( x_group [127:0] $end
|
|
$var wire 128 M( w_group [127:0] $end
|
|
$var wire 32 N( final_acc [31:0] $end
|
|
$var wire 32 O( bias_ext [31:0] $end
|
|
$var wire 32 P( acc_next [31:0] $end
|
|
$var parameter 32 Q( ACC_WIDTH $end
|
|
$var parameter 32 R( DATA_WIDTH $end
|
|
$var parameter 32 S( GROUPS $end
|
|
$var parameter 32 T( GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 U( N_INPUTS $end
|
|
$var parameter 32 V( PARALLEL $end
|
|
$var reg 32 W( acc [31:0] $end
|
|
$var reg 1 X( busy $end
|
|
$var reg 1 Y( done $end
|
|
$var reg 4 Z( group_index [3:0] $end
|
|
$var reg 8 [( y [7:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 32 \( acc_in [31:0] $end
|
|
$var wire 128 ]( w_bus [127:0] $end
|
|
$var wire 128 ^( x_bus [127:0] $end
|
|
$var wire 32 _( acc_out [31:0] $end
|
|
$var parameter 32 `( ACC_WIDTH $end
|
|
$var parameter 32 a( DATA_WIDTH $end
|
|
$var parameter 32 b( PARALLEL $end
|
|
$var parameter 32 c( TREE_LEVELS $end
|
|
$scope begin GEN_MAC[0] $end
|
|
$var parameter 2 d( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 e( acc_in [31:0] $end
|
|
$var wire 8 f( w [7:0] $end
|
|
$var wire 8 g( x [7:0] $end
|
|
$var wire 32 h( product_ext [31:0] $end
|
|
$var wire 16 i( product [15:0] $end
|
|
$var wire 32 j( acc_out [31:0] $end
|
|
$var parameter 32 k( ACC_WIDTH $end
|
|
$var parameter 32 l( DATA_WIDTH $end
|
|
$var parameter 64 m( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[1] $end
|
|
$var parameter 2 n( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 o( acc_in [31:0] $end
|
|
$var wire 8 p( w [7:0] $end
|
|
$var wire 8 q( x [7:0] $end
|
|
$var wire 32 r( product_ext [31:0] $end
|
|
$var wire 16 s( product [15:0] $end
|
|
$var wire 32 t( acc_out [31:0] $end
|
|
$var parameter 32 u( ACC_WIDTH $end
|
|
$var parameter 32 v( DATA_WIDTH $end
|
|
$var parameter 64 w( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[2] $end
|
|
$var parameter 3 x( i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 y( acc_in [31:0] $end
|
|
$var wire 8 z( w [7:0] $end
|
|
$var wire 8 {( x [7:0] $end
|
|
$var wire 32 |( product_ext [31:0] $end
|
|
$var wire 16 }( product [15:0] $end
|
|
$var wire 32 ~( acc_out [31:0] $end
|
|
$var parameter 32 !) ACC_WIDTH $end
|
|
$var parameter 32 ") DATA_WIDTH $end
|
|
$var parameter 64 #) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[3] $end
|
|
$var parameter 3 $) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 %) acc_in [31:0] $end
|
|
$var wire 8 &) w [7:0] $end
|
|
$var wire 8 ') x [7:0] $end
|
|
$var wire 32 () product_ext [31:0] $end
|
|
$var wire 16 )) product [15:0] $end
|
|
$var wire 32 *) acc_out [31:0] $end
|
|
$var parameter 32 +) ACC_WIDTH $end
|
|
$var parameter 32 ,) DATA_WIDTH $end
|
|
$var parameter 64 -) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[4] $end
|
|
$var parameter 4 .) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 /) acc_in [31:0] $end
|
|
$var wire 8 0) w [7:0] $end
|
|
$var wire 8 1) x [7:0] $end
|
|
$var wire 32 2) product_ext [31:0] $end
|
|
$var wire 16 3) product [15:0] $end
|
|
$var wire 32 4) acc_out [31:0] $end
|
|
$var parameter 32 5) ACC_WIDTH $end
|
|
$var parameter 32 6) DATA_WIDTH $end
|
|
$var parameter 64 7) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[5] $end
|
|
$var parameter 4 8) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 9) acc_in [31:0] $end
|
|
$var wire 8 :) w [7:0] $end
|
|
$var wire 8 ;) x [7:0] $end
|
|
$var wire 32 <) product_ext [31:0] $end
|
|
$var wire 16 =) product [15:0] $end
|
|
$var wire 32 >) acc_out [31:0] $end
|
|
$var parameter 32 ?) ACC_WIDTH $end
|
|
$var parameter 32 @) DATA_WIDTH $end
|
|
$var parameter 64 A) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[6] $end
|
|
$var parameter 4 B) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 C) acc_in [31:0] $end
|
|
$var wire 8 D) w [7:0] $end
|
|
$var wire 8 E) x [7:0] $end
|
|
$var wire 32 F) product_ext [31:0] $end
|
|
$var wire 16 G) product [15:0] $end
|
|
$var wire 32 H) acc_out [31:0] $end
|
|
$var parameter 32 I) ACC_WIDTH $end
|
|
$var parameter 32 J) DATA_WIDTH $end
|
|
$var parameter 64 K) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[7] $end
|
|
$var parameter 4 L) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 M) acc_in [31:0] $end
|
|
$var wire 8 N) w [7:0] $end
|
|
$var wire 8 O) x [7:0] $end
|
|
$var wire 32 P) product_ext [31:0] $end
|
|
$var wire 16 Q) product [15:0] $end
|
|
$var wire 32 R) acc_out [31:0] $end
|
|
$var parameter 32 S) ACC_WIDTH $end
|
|
$var parameter 32 T) DATA_WIDTH $end
|
|
$var parameter 64 U) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[8] $end
|
|
$var parameter 5 V) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 W) acc_in [31:0] $end
|
|
$var wire 8 X) w [7:0] $end
|
|
$var wire 8 Y) x [7:0] $end
|
|
$var wire 32 Z) product_ext [31:0] $end
|
|
$var wire 16 [) product [15:0] $end
|
|
$var wire 32 \) acc_out [31:0] $end
|
|
$var parameter 32 ]) ACC_WIDTH $end
|
|
$var parameter 32 ^) DATA_WIDTH $end
|
|
$var parameter 64 _) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[9] $end
|
|
$var parameter 5 `) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 a) acc_in [31:0] $end
|
|
$var wire 8 b) w [7:0] $end
|
|
$var wire 8 c) x [7:0] $end
|
|
$var wire 32 d) product_ext [31:0] $end
|
|
$var wire 16 e) product [15:0] $end
|
|
$var wire 32 f) acc_out [31:0] $end
|
|
$var parameter 32 g) ACC_WIDTH $end
|
|
$var parameter 32 h) DATA_WIDTH $end
|
|
$var parameter 64 i) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[10] $end
|
|
$var parameter 5 j) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 k) acc_in [31:0] $end
|
|
$var wire 8 l) w [7:0] $end
|
|
$var wire 8 m) x [7:0] $end
|
|
$var wire 32 n) product_ext [31:0] $end
|
|
$var wire 16 o) product [15:0] $end
|
|
$var wire 32 p) acc_out [31:0] $end
|
|
$var parameter 32 q) ACC_WIDTH $end
|
|
$var parameter 32 r) DATA_WIDTH $end
|
|
$var parameter 64 s) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[11] $end
|
|
$var parameter 5 t) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 u) acc_in [31:0] $end
|
|
$var wire 8 v) w [7:0] $end
|
|
$var wire 8 w) x [7:0] $end
|
|
$var wire 32 x) product_ext [31:0] $end
|
|
$var wire 16 y) product [15:0] $end
|
|
$var wire 32 z) acc_out [31:0] $end
|
|
$var parameter 32 {) ACC_WIDTH $end
|
|
$var parameter 32 |) DATA_WIDTH $end
|
|
$var parameter 64 }) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[12] $end
|
|
$var parameter 5 ~) i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 !* acc_in [31:0] $end
|
|
$var wire 8 "* w [7:0] $end
|
|
$var wire 8 #* x [7:0] $end
|
|
$var wire 32 $* product_ext [31:0] $end
|
|
$var wire 16 %* product [15:0] $end
|
|
$var wire 32 &* acc_out [31:0] $end
|
|
$var parameter 32 '* ACC_WIDTH $end
|
|
$var parameter 32 (* DATA_WIDTH $end
|
|
$var parameter 64 )* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[13] $end
|
|
$var parameter 5 ** i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 +* acc_in [31:0] $end
|
|
$var wire 8 ,* w [7:0] $end
|
|
$var wire 8 -* x [7:0] $end
|
|
$var wire 32 .* product_ext [31:0] $end
|
|
$var wire 16 /* product [15:0] $end
|
|
$var wire 32 0* acc_out [31:0] $end
|
|
$var parameter 32 1* ACC_WIDTH $end
|
|
$var parameter 32 2* DATA_WIDTH $end
|
|
$var parameter 64 3* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[14] $end
|
|
$var parameter 5 4* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 5* acc_in [31:0] $end
|
|
$var wire 8 6* w [7:0] $end
|
|
$var wire 8 7* x [7:0] $end
|
|
$var wire 32 8* product_ext [31:0] $end
|
|
$var wire 16 9* product [15:0] $end
|
|
$var wire 32 :* acc_out [31:0] $end
|
|
$var parameter 32 ;* ACC_WIDTH $end
|
|
$var parameter 32 <* DATA_WIDTH $end
|
|
$var parameter 64 =* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_MAC[15] $end
|
|
$var parameter 5 >* i $end
|
|
$scope module u_mac $end
|
|
$var wire 32 ?* acc_in [31:0] $end
|
|
$var wire 8 @* w [7:0] $end
|
|
$var wire 8 A* x [7:0] $end
|
|
$var wire 32 B* product_ext [31:0] $end
|
|
$var wire 16 C* product [15:0] $end
|
|
$var wire 32 D* acc_out [31:0] $end
|
|
$var parameter 32 E* ACC_WIDTH $end
|
|
$var parameter 32 F* DATA_WIDTH $end
|
|
$var parameter 64 G* PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[0] $end
|
|
$var parameter 2 H* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[1] $end
|
|
$var parameter 2 I* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[2] $end
|
|
$var parameter 3 J* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[3] $end
|
|
$var parameter 3 K* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[4] $end
|
|
$var parameter 4 L* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[5] $end
|
|
$var parameter 4 M* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[6] $end
|
|
$var parameter 4 N* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[7] $end
|
|
$var parameter 4 O* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[8] $end
|
|
$var parameter 5 P* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[9] $end
|
|
$var parameter 5 Q* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[10] $end
|
|
$var parameter 5 R* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[11] $end
|
|
$var parameter 5 S* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[12] $end
|
|
$var parameter 5 T* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[13] $end
|
|
$var parameter 5 U* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[14] $end
|
|
$var parameter 5 V* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_INPUT[15] $end
|
|
$var parameter 5 W* i $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[0] $end
|
|
$var parameter 2 X* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 Y* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 Z* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 [* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 \* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[4] $end
|
|
$var parameter 4 ]* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[5] $end
|
|
$var parameter 4 ^* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[6] $end
|
|
$var parameter 4 _* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[7] $end
|
|
$var parameter 4 `* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[1] $end
|
|
$var parameter 2 a* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 b* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 c* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[2] $end
|
|
$var parameter 3 d* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[3] $end
|
|
$var parameter 3 e* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[2] $end
|
|
$var parameter 3 f* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 g* node $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_NODE[1] $end
|
|
$var parameter 2 h* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_TREE_LEVEL[3] $end
|
|
$var parameter 3 i* level $end
|
|
$scope begin GEN_TREE_NODE[0] $end
|
|
$var parameter 2 j* node $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope task run_layer $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$comment Show the parameter values. $end
|
|
$dumpall
|
|
b0 j*
|
|
b11 i*
|
|
b1 h*
|
|
b0 g*
|
|
b10 f*
|
|
b11 e*
|
|
b10 d*
|
|
b1 c*
|
|
b0 b*
|
|
b1 a*
|
|
b111 `*
|
|
b110 _*
|
|
b101 ^*
|
|
b100 ]*
|
|
b11 \*
|
|
b10 [*
|
|
b1 Z*
|
|
b0 Y*
|
|
b0 X*
|
|
b1111 W*
|
|
b1110 V*
|
|
b1101 U*
|
|
b1100 T*
|
|
b1011 S*
|
|
b1010 R*
|
|
b1001 Q*
|
|
b1000 P*
|
|
b111 O*
|
|
b110 N*
|
|
b101 M*
|
|
b100 L*
|
|
b11 K*
|
|
b10 J*
|
|
b1 I*
|
|
b0 H*
|
|
b10000 G*
|
|
b1000 F*
|
|
b100000 E*
|
|
b1111 >*
|
|
b10000 =*
|
|
b1000 <*
|
|
b100000 ;*
|
|
b1110 4*
|
|
b10000 3*
|
|
b1000 2*
|
|
b100000 1*
|
|
b1101 **
|
|
b10000 )*
|
|
b1000 (*
|
|
b100000 '*
|
|
b1100 ~)
|
|
b10000 })
|
|
b1000 |)
|
|
b100000 {)
|
|
b1011 t)
|
|
b10000 s)
|
|
b1000 r)
|
|
b100000 q)
|
|
b1010 j)
|
|
b10000 i)
|
|
b1000 h)
|
|
b100000 g)
|
|
b1001 `)
|
|
b10000 _)
|
|
b1000 ^)
|
|
b100000 ])
|
|
b1000 V)
|
|
b10000 U)
|
|
b1000 T)
|
|
b100000 S)
|
|
b111 L)
|
|
b10000 K)
|
|
b1000 J)
|
|
b100000 I)
|
|
b110 B)
|
|
b10000 A)
|
|
b1000 @)
|
|
b100000 ?)
|
|
b101 8)
|
|
b10000 7)
|
|
b1000 6)
|
|
b100000 5)
|
|
b100 .)
|
|
b10000 -)
|
|
b1000 ,)
|
|
b100000 +)
|
|
b11 $)
|
|
b10000 #)
|
|
b1000 ")
|
|
b100000 !)
|
|
b10 x(
|
|
b10000 w(
|
|
b1000 v(
|
|
b100000 u(
|
|
b1 n(
|
|
b10000 m(
|
|
b1000 l(
|
|
b100000 k(
|
|
b0 d(
|
|
b100 c(
|
|
b10000 b(
|
|
b1000 a(
|
|
b100000 `(
|
|
b10000 V(
|
|
b100000000 U(
|
|
b100 T(
|
|
b10000 S(
|
|
b1000 R(
|
|
b100000 Q(
|
|
b11 H(
|
|
b0 G(
|
|
b11 F(
|
|
b1 E(
|
|
b0 D(
|
|
b10 C(
|
|
b11 B(
|
|
b10 A(
|
|
b1 @(
|
|
b0 ?(
|
|
b1 >(
|
|
b111 =(
|
|
b110 <(
|
|
b101 ;(
|
|
b100 :(
|
|
b11 9(
|
|
b10 8(
|
|
b1 7(
|
|
b0 6(
|
|
b0 5(
|
|
b1111 4(
|
|
b1110 3(
|
|
b1101 2(
|
|
b1100 1(
|
|
b1011 0(
|
|
b1010 /(
|
|
b1001 .(
|
|
b1000 -(
|
|
b111 ,(
|
|
b110 +(
|
|
b101 *(
|
|
b100 )(
|
|
b11 ((
|
|
b10 '(
|
|
b1 &(
|
|
b0 %(
|
|
b10000 $(
|
|
b1000 #(
|
|
b100000 "(
|
|
b1111 y'
|
|
b10000 x'
|
|
b1000 w'
|
|
b100000 v'
|
|
b1110 o'
|
|
b10000 n'
|
|
b1000 m'
|
|
b100000 l'
|
|
b1101 e'
|
|
b10000 d'
|
|
b1000 c'
|
|
b100000 b'
|
|
b1100 ['
|
|
b10000 Z'
|
|
b1000 Y'
|
|
b100000 X'
|
|
b1011 Q'
|
|
b10000 P'
|
|
b1000 O'
|
|
b100000 N'
|
|
b1010 G'
|
|
b10000 F'
|
|
b1000 E'
|
|
b100000 D'
|
|
b1001 ='
|
|
b10000 <'
|
|
b1000 ;'
|
|
b100000 :'
|
|
b1000 3'
|
|
b10000 2'
|
|
b1000 1'
|
|
b100000 0'
|
|
b111 )'
|
|
b10000 ('
|
|
b1000 ''
|
|
b100000 &'
|
|
b110 }&
|
|
b10000 |&
|
|
b1000 {&
|
|
b100000 z&
|
|
b101 s&
|
|
b10000 r&
|
|
b1000 q&
|
|
b100000 p&
|
|
b100 i&
|
|
b10000 h&
|
|
b1000 g&
|
|
b100000 f&
|
|
b11 _&
|
|
b10000 ^&
|
|
b1000 ]&
|
|
b100000 \&
|
|
b10 U&
|
|
b10000 T&
|
|
b1000 S&
|
|
b100000 R&
|
|
b1 K&
|
|
b10000 J&
|
|
b1000 I&
|
|
b100000 H&
|
|
b0 A&
|
|
b100 @&
|
|
b10000 ?&
|
|
b1000 >&
|
|
b100000 =&
|
|
b10000 3&
|
|
b100000000 2&
|
|
b100 1&
|
|
b10000 0&
|
|
b1000 /&
|
|
b100000 .&
|
|
b10 %&
|
|
b0 $&
|
|
b11 #&
|
|
b1 "&
|
|
b0 !&
|
|
b10 ~%
|
|
b11 }%
|
|
b10 |%
|
|
b1 {%
|
|
b0 z%
|
|
b1 y%
|
|
b111 x%
|
|
b110 w%
|
|
b101 v%
|
|
b100 u%
|
|
b11 t%
|
|
b10 s%
|
|
b1 r%
|
|
b0 q%
|
|
b0 p%
|
|
b1111 o%
|
|
b1110 n%
|
|
b1101 m%
|
|
b1100 l%
|
|
b1011 k%
|
|
b1010 j%
|
|
b1001 i%
|
|
b1000 h%
|
|
b111 g%
|
|
b110 f%
|
|
b101 e%
|
|
b100 d%
|
|
b11 c%
|
|
b10 b%
|
|
b1 a%
|
|
b0 `%
|
|
b10000 _%
|
|
b1000 ^%
|
|
b100000 ]%
|
|
b1111 V%
|
|
b10000 U%
|
|
b1000 T%
|
|
b100000 S%
|
|
b1110 L%
|
|
b10000 K%
|
|
b1000 J%
|
|
b100000 I%
|
|
b1101 B%
|
|
b10000 A%
|
|
b1000 @%
|
|
b100000 ?%
|
|
b1100 8%
|
|
b10000 7%
|
|
b1000 6%
|
|
b100000 5%
|
|
b1011 .%
|
|
b10000 -%
|
|
b1000 ,%
|
|
b100000 +%
|
|
b1010 $%
|
|
b10000 #%
|
|
b1000 "%
|
|
b100000 !%
|
|
b1001 x$
|
|
b10000 w$
|
|
b1000 v$
|
|
b100000 u$
|
|
b1000 n$
|
|
b10000 m$
|
|
b1000 l$
|
|
b100000 k$
|
|
b111 d$
|
|
b10000 c$
|
|
b1000 b$
|
|
b100000 a$
|
|
b110 Z$
|
|
b10000 Y$
|
|
b1000 X$
|
|
b100000 W$
|
|
b101 P$
|
|
b10000 O$
|
|
b1000 N$
|
|
b100000 M$
|
|
b100 F$
|
|
b10000 E$
|
|
b1000 D$
|
|
b100000 C$
|
|
b11 <$
|
|
b10000 ;$
|
|
b1000 :$
|
|
b100000 9$
|
|
b10 2$
|
|
b10000 1$
|
|
b1000 0$
|
|
b100000 /$
|
|
b1 ($
|
|
b10000 '$
|
|
b1000 &$
|
|
b100000 %$
|
|
b0 |#
|
|
b100 {#
|
|
b10000 z#
|
|
b1000 y#
|
|
b100000 x#
|
|
b10000 n#
|
|
b100000000 m#
|
|
b100 l#
|
|
b10000 k#
|
|
b1000 j#
|
|
b100000 i#
|
|
b1 `#
|
|
b0 _#
|
|
b11 ^#
|
|
b1 ]#
|
|
b0 \#
|
|
b10 [#
|
|
b11 Z#
|
|
b10 Y#
|
|
b1 X#
|
|
b0 W#
|
|
b1 V#
|
|
b111 U#
|
|
b110 T#
|
|
b101 S#
|
|
b100 R#
|
|
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 4
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 @
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 c#
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 (&
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