3593 lines
100 KiB
Plaintext
3593 lines
100 KiB
Plaintext
$date
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Wed Sep 2 09:14:02 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module tb $end
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$var wire 128 ! y_bus [127:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 $ ACC_WIDTH $end
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$var parameter 32 % DATA_WIDTH $end
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$var parameter 32 & FRAC_BITS $end
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$var parameter 32 ' N_INPUTS $end
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$var parameter 32 ( N_NEURONS $end
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$var parameter 32 ) PARALLEL $end
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$var reg 128 * bias_bus [127:0] $end
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$var reg 1 + clk $end
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$var reg 1 , rst $end
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$var reg 1 - start $end
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$var reg 8192 . weights_bus [8191:0] $end
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$var reg 1024 / x_bus [1023:0] $end
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$var integer 32 0 errors [31:0] $end
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$var integer 32 1 i [31:0] $end
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$scope function q8_8 $end
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$var real 1 2 value $end
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$upscope $end
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$scope module dut $end
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$var wire 128 3 bias_bus [127:0] $end
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$var wire 1 + clk $end
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$var wire 1 , rst $end
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$var wire 1 - start $end
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$var wire 8192 4 weights_bus [8191:0] $end
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$var wire 1024 5 x_bus [1023:0] $end
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$var wire 128 6 y_bus [127:0] $end
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$var wire 8 7 neuron_done [7:0] $end
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$var wire 8 8 neuron_busy [7:0] $end
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$var wire 1 " done $end
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$var wire 1 # busy $end
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$var parameter 32 9 ACC_WIDTH $end
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$var parameter 32 : DATA_WIDTH $end
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$var parameter 32 ; FRAC_BITS $end
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$var parameter 32 < N_INPUTS $end
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$var parameter 32 = N_NEURONS $end
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$var parameter 32 > PARALLEL $end
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$scope begin GEN_NEURON[0] $end
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$var parameter 2 ? n $end
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$scope module u_neuron $end
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$var wire 16 @ bias [15:0] $end
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$var wire 16 A bias_ext_small [15:0] $end
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$var wire 1 + clk $end
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$var wire 1 , rst $end
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$var wire 1 - start $end
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$var wire 1024 B w_bus [1023:0] $end
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$var wire 1024 C x_bus [1023:0] $end
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$var wire 128 D x_group [127:0] $end
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$var wire 128 E w_group [127:0] $end
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$var wire 40 F final_value [39:0] $end
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$var wire 40 G final_acc [39:0] $end
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$var wire 40 H bias_ext [39:0] $end
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$var wire 40 I acc_next [39:0] $end
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$var parameter 32 J ACC_WIDTH $end
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$var parameter 32 K DATA_WIDTH $end
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$var parameter 32 L FRAC_BITS $end
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$var parameter 32 M GROUPS $end
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$var parameter 32 N GROUP_INDEX_WIDTH $end
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$var parameter 32 O N_INPUTS $end
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$var parameter 32 P PARALLEL $end
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$var reg 40 Q acc [39:0] $end
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$var reg 1 R busy $end
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$var reg 1 S done $end
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$var reg 3 T group_index [2:0] $end
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$var reg 16 U y [15:0] $end
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$scope module u_mac8 $end
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$var wire 40 V acc_in [39:0] $end
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$var wire 128 W w_bus [127:0] $end
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$var wire 128 X x_bus [127:0] $end
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$var wire 40 Y sum [39:0] $end
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$var wire 40 Z s5 [39:0] $end
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$var wire 40 [ s4 [39:0] $end
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$var wire 40 \ s3 [39:0] $end
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$var wire 40 ] s2 [39:0] $end
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$var wire 40 ^ s1 [39:0] $end
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$var wire 40 _ s0 [39:0] $end
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$var wire 40 ` m7 [39:0] $end
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$var wire 40 a m6 [39:0] $end
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$var wire 40 b m5 [39:0] $end
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$var wire 40 c m4 [39:0] $end
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$var wire 40 d m3 [39:0] $end
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$var wire 40 e m2 [39:0] $end
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$var wire 40 f m1 [39:0] $end
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$var wire 40 g m0 [39:0] $end
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$var wire 40 h acc_out [39:0] $end
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$var parameter 32 i ACC_WIDTH $end
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$var parameter 32 j DATA_WIDTH $end
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$scope module mac0 $end
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$var wire 40 k acc_in [39:0] $end
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$var wire 16 l w [15:0] $end
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$var wire 16 m x [15:0] $end
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$var wire 40 n product_ext [39:0] $end
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$var wire 32 o product [31:0] $end
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$var wire 40 p acc_out [39:0] $end
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$var parameter 32 q ACC_WIDTH $end
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$var parameter 32 r DATA_WIDTH $end
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$var parameter 64 s PROD_WIDTH $end
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$upscope $end
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$scope module mac1 $end
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$var wire 40 t acc_in [39:0] $end
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$var wire 16 u w [15:0] $end
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$var wire 16 v x [15:0] $end
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$var wire 40 w product_ext [39:0] $end
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$var wire 32 x product [31:0] $end
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$var wire 40 y acc_out [39:0] $end
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$var parameter 32 z ACC_WIDTH $end
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$var parameter 32 { DATA_WIDTH $end
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$var parameter 64 | PROD_WIDTH $end
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$upscope $end
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$scope module mac2 $end
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$var wire 40 } acc_in [39:0] $end
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$var wire 16 ~ w [15:0] $end
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$var wire 16 !" x [15:0] $end
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$var wire 40 "" product_ext [39:0] $end
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$var wire 32 #" product [31:0] $end
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$var wire 40 $" acc_out [39:0] $end
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$var parameter 32 %" ACC_WIDTH $end
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$var parameter 32 &" DATA_WIDTH $end
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$var parameter 64 '" PROD_WIDTH $end
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$upscope $end
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$scope module mac3 $end
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$var wire 40 (" acc_in [39:0] $end
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$var wire 16 )" w [15:0] $end
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$var wire 16 *" x [15:0] $end
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$var wire 40 +" product_ext [39:0] $end
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$var wire 32 ," product [31:0] $end
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$var wire 40 -" acc_out [39:0] $end
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$var parameter 32 ." ACC_WIDTH $end
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$var parameter 32 /" DATA_WIDTH $end
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$var parameter 64 0" PROD_WIDTH $end
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$upscope $end
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$scope module mac4 $end
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$var wire 40 1" acc_in [39:0] $end
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$var wire 16 2" w [15:0] $end
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$var wire 16 3" x [15:0] $end
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$var wire 40 4" product_ext [39:0] $end
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$var wire 32 5" product [31:0] $end
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$var wire 40 6" acc_out [39:0] $end
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$var parameter 32 7" ACC_WIDTH $end
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$var parameter 32 8" DATA_WIDTH $end
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$var parameter 64 9" PROD_WIDTH $end
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$upscope $end
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$scope module mac5 $end
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$var wire 40 :" acc_in [39:0] $end
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$var wire 16 ;" w [15:0] $end
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$var wire 16 <" x [15:0] $end
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$var wire 40 =" product_ext [39:0] $end
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$var wire 32 >" product [31:0] $end
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$var wire 40 ?" acc_out [39:0] $end
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$var parameter 32 @" ACC_WIDTH $end
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$var parameter 32 A" DATA_WIDTH $end
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$var parameter 64 B" PROD_WIDTH $end
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$upscope $end
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$scope module mac6 $end
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$var wire 40 C" acc_in [39:0] $end
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$var wire 16 D" w [15:0] $end
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$var wire 16 E" x [15:0] $end
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$var wire 40 F" product_ext [39:0] $end
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$var wire 32 G" product [31:0] $end
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$var wire 40 H" acc_out [39:0] $end
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$var parameter 32 I" ACC_WIDTH $end
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$var parameter 32 J" DATA_WIDTH $end
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$var parameter 64 K" PROD_WIDTH $end
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$upscope $end
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$scope module mac7 $end
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$var wire 40 L" acc_in [39:0] $end
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$var wire 16 M" w [15:0] $end
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$var wire 16 N" x [15:0] $end
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$var wire 40 O" product_ext [39:0] $end
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$var wire 32 P" product [31:0] $end
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$var wire 40 Q" acc_out [39:0] $end
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$var parameter 32 R" ACC_WIDTH $end
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$var parameter 32 S" DATA_WIDTH $end
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$var parameter 64 T" PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin GEN_NEURON[1] $end
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$var parameter 2 U" n $end
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$scope module u_neuron $end
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$var wire 16 V" bias [15:0] $end
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$var wire 16 W" bias_ext_small [15:0] $end
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$var wire 1 + clk $end
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$var wire 1 , rst $end
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$var wire 1 - start $end
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$var wire 1024 X" w_bus [1023:0] $end
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$var wire 1024 Y" x_bus [1023:0] $end
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$var wire 128 Z" x_group [127:0] $end
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$var wire 128 [" w_group [127:0] $end
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$var wire 40 \" final_value [39:0] $end
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$var wire 40 ]" final_acc [39:0] $end
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$var wire 40 ^" bias_ext [39:0] $end
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$var wire 40 _" acc_next [39:0] $end
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$var parameter 32 `" ACC_WIDTH $end
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$var parameter 32 a" DATA_WIDTH $end
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$var parameter 32 b" FRAC_BITS $end
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$var parameter 32 c" GROUPS $end
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$var parameter 32 d" GROUP_INDEX_WIDTH $end
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$var parameter 32 e" N_INPUTS $end
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$var parameter 32 f" PARALLEL $end
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$var reg 40 g" acc [39:0] $end
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$var reg 1 h" busy $end
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$var reg 1 i" done $end
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$var reg 3 j" group_index [2:0] $end
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$var reg 16 k" y [15:0] $end
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$scope module u_mac8 $end
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$var wire 40 l" acc_in [39:0] $end
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$var wire 128 m" w_bus [127:0] $end
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$var wire 128 n" x_bus [127:0] $end
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$var wire 40 o" sum [39:0] $end
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$var wire 40 p" s5 [39:0] $end
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$var wire 40 q" s4 [39:0] $end
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$var wire 40 r" s3 [39:0] $end
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$var wire 40 s" s2 [39:0] $end
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$var wire 40 t" s1 [39:0] $end
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$var wire 40 u" s0 [39:0] $end
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$var wire 40 v" m7 [39:0] $end
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$var wire 40 w" m6 [39:0] $end
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$var wire 40 x" m5 [39:0] $end
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$var wire 40 y" m4 [39:0] $end
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$var wire 40 z" m3 [39:0] $end
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$var wire 40 {" m2 [39:0] $end
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$var wire 40 |" m1 [39:0] $end
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$var wire 40 }" m0 [39:0] $end
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$var wire 40 ~" acc_out [39:0] $end
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$var parameter 32 !# ACC_WIDTH $end
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$var parameter 32 "# DATA_WIDTH $end
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$scope module mac0 $end
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$var wire 40 ## acc_in [39:0] $end
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$var wire 16 $# w [15:0] $end
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$var wire 16 %# x [15:0] $end
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$var wire 40 &# product_ext [39:0] $end
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$var wire 32 '# product [31:0] $end
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$var wire 40 (# acc_out [39:0] $end
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$var parameter 32 )# ACC_WIDTH $end
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$var parameter 32 *# DATA_WIDTH $end
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$var parameter 64 +# PROD_WIDTH $end
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$upscope $end
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$scope module mac1 $end
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$var wire 40 ,# acc_in [39:0] $end
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$var wire 16 -# w [15:0] $end
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$var wire 16 .# x [15:0] $end
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$var wire 40 /# product_ext [39:0] $end
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$var wire 32 0# product [31:0] $end
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$var wire 40 1# acc_out [39:0] $end
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$var parameter 32 2# ACC_WIDTH $end
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$var parameter 32 3# DATA_WIDTH $end
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$var parameter 64 4# PROD_WIDTH $end
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$upscope $end
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$scope module mac2 $end
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$var wire 40 5# acc_in [39:0] $end
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$var wire 16 6# w [15:0] $end
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$var wire 16 7# x [15:0] $end
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$var wire 40 8# product_ext [39:0] $end
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$var wire 32 9# product [31:0] $end
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$var wire 40 :# acc_out [39:0] $end
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$var parameter 32 ;# ACC_WIDTH $end
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$var parameter 32 <# DATA_WIDTH $end
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$var parameter 64 =# PROD_WIDTH $end
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$upscope $end
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$scope module mac3 $end
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$var wire 40 ># acc_in [39:0] $end
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$var wire 16 ?# w [15:0] $end
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$var wire 16 @# x [15:0] $end
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$var wire 40 A# product_ext [39:0] $end
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$var wire 32 B# product [31:0] $end
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$var wire 40 C# acc_out [39:0] $end
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$var parameter 32 D# ACC_WIDTH $end
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$var parameter 32 E# DATA_WIDTH $end
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$var parameter 64 F# PROD_WIDTH $end
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$upscope $end
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$scope module mac4 $end
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$var wire 40 G# acc_in [39:0] $end
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$var wire 16 H# w [15:0] $end
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$var wire 16 I# x [15:0] $end
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$var wire 40 J# product_ext [39:0] $end
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$var wire 32 K# product [31:0] $end
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$var wire 40 L# acc_out [39:0] $end
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$var parameter 32 M# ACC_WIDTH $end
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$var parameter 32 N# DATA_WIDTH $end
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$var parameter 64 O# PROD_WIDTH $end
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$upscope $end
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$scope module mac5 $end
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$var wire 40 P# acc_in [39:0] $end
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$var wire 16 Q# w [15:0] $end
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$var wire 16 R# x [15:0] $end
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$var wire 40 S# product_ext [39:0] $end
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$var wire 32 T# product [31:0] $end
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$var wire 40 U# acc_out [39:0] $end
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$var parameter 32 V# ACC_WIDTH $end
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$var parameter 32 W# DATA_WIDTH $end
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$var parameter 64 X# PROD_WIDTH $end
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$upscope $end
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$scope module mac6 $end
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$var wire 40 Y# acc_in [39:0] $end
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$var wire 16 Z# w [15:0] $end
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$var wire 16 [# x [15:0] $end
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$var wire 40 \# product_ext [39:0] $end
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$var wire 32 ]# product [31:0] $end
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$var wire 40 ^# acc_out [39:0] $end
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$var parameter 32 _# ACC_WIDTH $end
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$var parameter 32 `# DATA_WIDTH $end
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$var parameter 64 a# PROD_WIDTH $end
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$upscope $end
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$scope module mac7 $end
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$var wire 40 b# acc_in [39:0] $end
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$var wire 16 c# w [15:0] $end
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$var wire 16 d# x [15:0] $end
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$var wire 40 e# product_ext [39:0] $end
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$var wire 32 f# product [31:0] $end
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$var wire 40 g# acc_out [39:0] $end
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$var parameter 32 h# ACC_WIDTH $end
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$var parameter 32 i# DATA_WIDTH $end
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$var parameter 64 j# PROD_WIDTH $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope begin GEN_NEURON[2] $end
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$var parameter 3 k# n $end
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$scope module u_neuron $end
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$var wire 16 l# bias [15:0] $end
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$var wire 16 m# bias_ext_small [15:0] $end
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$var wire 1 + clk $end
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$var wire 1 , rst $end
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$var wire 1 - start $end
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$var wire 1024 n# w_bus [1023:0] $end
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$var wire 1024 o# x_bus [1023:0] $end
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$var wire 128 p# x_group [127:0] $end
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$var wire 128 q# w_group [127:0] $end
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$var wire 40 r# final_value [39:0] $end
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$var wire 40 s# final_acc [39:0] $end
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$var wire 40 t# bias_ext [39:0] $end
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$var wire 40 u# acc_next [39:0] $end
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$var parameter 32 v# ACC_WIDTH $end
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$var parameter 32 w# DATA_WIDTH $end
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$var parameter 32 x# FRAC_BITS $end
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$var parameter 32 y# GROUPS $end
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$var parameter 32 z# GROUP_INDEX_WIDTH $end
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$var parameter 32 {# N_INPUTS $end
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$var parameter 32 |# PARALLEL $end
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$var reg 40 }# acc [39:0] $end
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$var reg 1 ~# busy $end
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$var reg 1 !$ done $end
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$var reg 3 "$ group_index [2:0] $end
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$var reg 16 #$ y [15:0] $end
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$scope module u_mac8 $end
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$var wire 40 $$ acc_in [39:0] $end
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$var wire 128 %$ w_bus [127:0] $end
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$var wire 128 &$ x_bus [127:0] $end
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$var wire 40 '$ sum [39:0] $end
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$var wire 40 ($ s5 [39:0] $end
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$var wire 40 )$ s4 [39:0] $end
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$var wire 40 *$ s3 [39:0] $end
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$var wire 40 +$ s2 [39:0] $end
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$var wire 40 ,$ s1 [39:0] $end
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$var wire 40 -$ s0 [39:0] $end
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$var wire 40 .$ m7 [39:0] $end
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$var wire 40 /$ m6 [39:0] $end
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$var wire 40 0$ m5 [39:0] $end
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$var wire 40 1$ m4 [39:0] $end
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$var wire 40 2$ m3 [39:0] $end
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$var wire 40 3$ m2 [39:0] $end
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$var wire 40 4$ m1 [39:0] $end
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$var wire 40 5$ m0 [39:0] $end
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$var wire 40 6$ acc_out [39:0] $end
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$var parameter 32 7$ ACC_WIDTH $end
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$var parameter 32 8$ DATA_WIDTH $end
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$scope module mac0 $end
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$var wire 40 9$ acc_in [39:0] $end
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$var wire 16 :$ w [15:0] $end
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$var wire 16 ;$ x [15:0] $end
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$var wire 40 <$ product_ext [39:0] $end
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$var wire 32 =$ product [31:0] $end
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$var wire 40 >$ acc_out [39:0] $end
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$var parameter 32 ?$ ACC_WIDTH $end
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$var parameter 32 @$ DATA_WIDTH $end
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$var parameter 64 A$ PROD_WIDTH $end
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$upscope $end
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$scope module mac1 $end
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$var wire 40 B$ acc_in [39:0] $end
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$var wire 16 C$ w [15:0] $end
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$var wire 16 D$ x [15:0] $end
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$var wire 40 E$ product_ext [39:0] $end
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$var wire 32 F$ product [31:0] $end
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$var wire 40 G$ acc_out [39:0] $end
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$var parameter 32 H$ ACC_WIDTH $end
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$var parameter 32 I$ DATA_WIDTH $end
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$var parameter 64 J$ PROD_WIDTH $end
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$upscope $end
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$scope module mac2 $end
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$var wire 40 K$ acc_in [39:0] $end
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$var wire 16 L$ w [15:0] $end
|
|
$var wire 16 M$ x [15:0] $end
|
|
$var wire 40 N$ product_ext [39:0] $end
|
|
$var wire 32 O$ product [31:0] $end
|
|
$var wire 40 P$ acc_out [39:0] $end
|
|
$var parameter 32 Q$ ACC_WIDTH $end
|
|
$var parameter 32 R$ DATA_WIDTH $end
|
|
$var parameter 64 S$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 T$ acc_in [39:0] $end
|
|
$var wire 16 U$ w [15:0] $end
|
|
$var wire 16 V$ x [15:0] $end
|
|
$var wire 40 W$ product_ext [39:0] $end
|
|
$var wire 32 X$ product [31:0] $end
|
|
$var wire 40 Y$ acc_out [39:0] $end
|
|
$var parameter 32 Z$ ACC_WIDTH $end
|
|
$var parameter 32 [$ DATA_WIDTH $end
|
|
$var parameter 64 \$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 ]$ acc_in [39:0] $end
|
|
$var wire 16 ^$ w [15:0] $end
|
|
$var wire 16 _$ x [15:0] $end
|
|
$var wire 40 `$ product_ext [39:0] $end
|
|
$var wire 32 a$ product [31:0] $end
|
|
$var wire 40 b$ acc_out [39:0] $end
|
|
$var parameter 32 c$ ACC_WIDTH $end
|
|
$var parameter 32 d$ DATA_WIDTH $end
|
|
$var parameter 64 e$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 f$ acc_in [39:0] $end
|
|
$var wire 16 g$ w [15:0] $end
|
|
$var wire 16 h$ x [15:0] $end
|
|
$var wire 40 i$ product_ext [39:0] $end
|
|
$var wire 32 j$ product [31:0] $end
|
|
$var wire 40 k$ acc_out [39:0] $end
|
|
$var parameter 32 l$ ACC_WIDTH $end
|
|
$var parameter 32 m$ DATA_WIDTH $end
|
|
$var parameter 64 n$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 o$ acc_in [39:0] $end
|
|
$var wire 16 p$ w [15:0] $end
|
|
$var wire 16 q$ x [15:0] $end
|
|
$var wire 40 r$ product_ext [39:0] $end
|
|
$var wire 32 s$ product [31:0] $end
|
|
$var wire 40 t$ acc_out [39:0] $end
|
|
$var parameter 32 u$ ACC_WIDTH $end
|
|
$var parameter 32 v$ DATA_WIDTH $end
|
|
$var parameter 64 w$ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 x$ acc_in [39:0] $end
|
|
$var wire 16 y$ w [15:0] $end
|
|
$var wire 16 z$ x [15:0] $end
|
|
$var wire 40 {$ product_ext [39:0] $end
|
|
$var wire 32 |$ product [31:0] $end
|
|
$var wire 40 }$ acc_out [39:0] $end
|
|
$var parameter 32 ~$ ACC_WIDTH $end
|
|
$var parameter 32 !% DATA_WIDTH $end
|
|
$var parameter 64 "% PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[3] $end
|
|
$var parameter 3 #% n $end
|
|
$scope module u_neuron $end
|
|
$var wire 16 $% bias [15:0] $end
|
|
$var wire 16 %% bias_ext_small [15:0] $end
|
|
$var wire 1 + clk $end
|
|
$var wire 1 , rst $end
|
|
$var wire 1 - start $end
|
|
$var wire 1024 &% w_bus [1023:0] $end
|
|
$var wire 1024 '% x_bus [1023:0] $end
|
|
$var wire 128 (% x_group [127:0] $end
|
|
$var wire 128 )% w_group [127:0] $end
|
|
$var wire 40 *% final_value [39:0] $end
|
|
$var wire 40 +% final_acc [39:0] $end
|
|
$var wire 40 ,% bias_ext [39:0] $end
|
|
$var wire 40 -% acc_next [39:0] $end
|
|
$var parameter 32 .% ACC_WIDTH $end
|
|
$var parameter 32 /% DATA_WIDTH $end
|
|
$var parameter 32 0% FRAC_BITS $end
|
|
$var parameter 32 1% GROUPS $end
|
|
$var parameter 32 2% GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 3% N_INPUTS $end
|
|
$var parameter 32 4% PARALLEL $end
|
|
$var reg 40 5% acc [39:0] $end
|
|
$var reg 1 6% busy $end
|
|
$var reg 1 7% done $end
|
|
$var reg 3 8% group_index [2:0] $end
|
|
$var reg 16 9% y [15:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 40 :% acc_in [39:0] $end
|
|
$var wire 128 ;% w_bus [127:0] $end
|
|
$var wire 128 <% x_bus [127:0] $end
|
|
$var wire 40 =% sum [39:0] $end
|
|
$var wire 40 >% s5 [39:0] $end
|
|
$var wire 40 ?% s4 [39:0] $end
|
|
$var wire 40 @% s3 [39:0] $end
|
|
$var wire 40 A% s2 [39:0] $end
|
|
$var wire 40 B% s1 [39:0] $end
|
|
$var wire 40 C% s0 [39:0] $end
|
|
$var wire 40 D% m7 [39:0] $end
|
|
$var wire 40 E% m6 [39:0] $end
|
|
$var wire 40 F% m5 [39:0] $end
|
|
$var wire 40 G% m4 [39:0] $end
|
|
$var wire 40 H% m3 [39:0] $end
|
|
$var wire 40 I% m2 [39:0] $end
|
|
$var wire 40 J% m1 [39:0] $end
|
|
$var wire 40 K% m0 [39:0] $end
|
|
$var wire 40 L% acc_out [39:0] $end
|
|
$var parameter 32 M% ACC_WIDTH $end
|
|
$var parameter 32 N% DATA_WIDTH $end
|
|
$scope module mac0 $end
|
|
$var wire 40 O% acc_in [39:0] $end
|
|
$var wire 16 P% w [15:0] $end
|
|
$var wire 16 Q% x [15:0] $end
|
|
$var wire 40 R% product_ext [39:0] $end
|
|
$var wire 32 S% product [31:0] $end
|
|
$var wire 40 T% acc_out [39:0] $end
|
|
$var parameter 32 U% ACC_WIDTH $end
|
|
$var parameter 32 V% DATA_WIDTH $end
|
|
$var parameter 64 W% PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac1 $end
|
|
$var wire 40 X% acc_in [39:0] $end
|
|
$var wire 16 Y% w [15:0] $end
|
|
$var wire 16 Z% x [15:0] $end
|
|
$var wire 40 [% product_ext [39:0] $end
|
|
$var wire 32 \% product [31:0] $end
|
|
$var wire 40 ]% acc_out [39:0] $end
|
|
$var parameter 32 ^% ACC_WIDTH $end
|
|
$var parameter 32 _% DATA_WIDTH $end
|
|
$var parameter 64 `% PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac2 $end
|
|
$var wire 40 a% acc_in [39:0] $end
|
|
$var wire 16 b% w [15:0] $end
|
|
$var wire 16 c% x [15:0] $end
|
|
$var wire 40 d% product_ext [39:0] $end
|
|
$var wire 32 e% product [31:0] $end
|
|
$var wire 40 f% acc_out [39:0] $end
|
|
$var parameter 32 g% ACC_WIDTH $end
|
|
$var parameter 32 h% DATA_WIDTH $end
|
|
$var parameter 64 i% PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 j% acc_in [39:0] $end
|
|
$var wire 16 k% w [15:0] $end
|
|
$var wire 16 l% x [15:0] $end
|
|
$var wire 40 m% product_ext [39:0] $end
|
|
$var wire 32 n% product [31:0] $end
|
|
$var wire 40 o% acc_out [39:0] $end
|
|
$var parameter 32 p% ACC_WIDTH $end
|
|
$var parameter 32 q% DATA_WIDTH $end
|
|
$var parameter 64 r% PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 s% acc_in [39:0] $end
|
|
$var wire 16 t% w [15:0] $end
|
|
$var wire 16 u% x [15:0] $end
|
|
$var wire 40 v% product_ext [39:0] $end
|
|
$var wire 32 w% product [31:0] $end
|
|
$var wire 40 x% acc_out [39:0] $end
|
|
$var parameter 32 y% ACC_WIDTH $end
|
|
$var parameter 32 z% DATA_WIDTH $end
|
|
$var parameter 64 {% PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 |% acc_in [39:0] $end
|
|
$var wire 16 }% w [15:0] $end
|
|
$var wire 16 ~% x [15:0] $end
|
|
$var wire 40 !& product_ext [39:0] $end
|
|
$var wire 32 "& product [31:0] $end
|
|
$var wire 40 #& acc_out [39:0] $end
|
|
$var parameter 32 $& ACC_WIDTH $end
|
|
$var parameter 32 %& DATA_WIDTH $end
|
|
$var parameter 64 && PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 '& acc_in [39:0] $end
|
|
$var wire 16 (& w [15:0] $end
|
|
$var wire 16 )& x [15:0] $end
|
|
$var wire 40 *& product_ext [39:0] $end
|
|
$var wire 32 +& product [31:0] $end
|
|
$var wire 40 ,& acc_out [39:0] $end
|
|
$var parameter 32 -& ACC_WIDTH $end
|
|
$var parameter 32 .& DATA_WIDTH $end
|
|
$var parameter 64 /& PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 0& acc_in [39:0] $end
|
|
$var wire 16 1& w [15:0] $end
|
|
$var wire 16 2& x [15:0] $end
|
|
$var wire 40 3& product_ext [39:0] $end
|
|
$var wire 32 4& product [31:0] $end
|
|
$var wire 40 5& acc_out [39:0] $end
|
|
$var parameter 32 6& ACC_WIDTH $end
|
|
$var parameter 32 7& DATA_WIDTH $end
|
|
$var parameter 64 8& PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[4] $end
|
|
$var parameter 4 9& n $end
|
|
$scope module u_neuron $end
|
|
$var wire 16 :& bias [15:0] $end
|
|
$var wire 16 ;& bias_ext_small [15:0] $end
|
|
$var wire 1 + clk $end
|
|
$var wire 1 , rst $end
|
|
$var wire 1 - start $end
|
|
$var wire 1024 <& w_bus [1023:0] $end
|
|
$var wire 1024 =& x_bus [1023:0] $end
|
|
$var wire 128 >& x_group [127:0] $end
|
|
$var wire 128 ?& w_group [127:0] $end
|
|
$var wire 40 @& final_value [39:0] $end
|
|
$var wire 40 A& final_acc [39:0] $end
|
|
$var wire 40 B& bias_ext [39:0] $end
|
|
$var wire 40 C& acc_next [39:0] $end
|
|
$var parameter 32 D& ACC_WIDTH $end
|
|
$var parameter 32 E& DATA_WIDTH $end
|
|
$var parameter 32 F& FRAC_BITS $end
|
|
$var parameter 32 G& GROUPS $end
|
|
$var parameter 32 H& GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 I& N_INPUTS $end
|
|
$var parameter 32 J& PARALLEL $end
|
|
$var reg 40 K& acc [39:0] $end
|
|
$var reg 1 L& busy $end
|
|
$var reg 1 M& done $end
|
|
$var reg 3 N& group_index [2:0] $end
|
|
$var reg 16 O& y [15:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 40 P& acc_in [39:0] $end
|
|
$var wire 128 Q& w_bus [127:0] $end
|
|
$var wire 128 R& x_bus [127:0] $end
|
|
$var wire 40 S& sum [39:0] $end
|
|
$var wire 40 T& s5 [39:0] $end
|
|
$var wire 40 U& s4 [39:0] $end
|
|
$var wire 40 V& s3 [39:0] $end
|
|
$var wire 40 W& s2 [39:0] $end
|
|
$var wire 40 X& s1 [39:0] $end
|
|
$var wire 40 Y& s0 [39:0] $end
|
|
$var wire 40 Z& m7 [39:0] $end
|
|
$var wire 40 [& m6 [39:0] $end
|
|
$var wire 40 \& m5 [39:0] $end
|
|
$var wire 40 ]& m4 [39:0] $end
|
|
$var wire 40 ^& m3 [39:0] $end
|
|
$var wire 40 _& m2 [39:0] $end
|
|
$var wire 40 `& m1 [39:0] $end
|
|
$var wire 40 a& m0 [39:0] $end
|
|
$var wire 40 b& acc_out [39:0] $end
|
|
$var parameter 32 c& ACC_WIDTH $end
|
|
$var parameter 32 d& DATA_WIDTH $end
|
|
$scope module mac0 $end
|
|
$var wire 40 e& acc_in [39:0] $end
|
|
$var wire 16 f& w [15:0] $end
|
|
$var wire 16 g& x [15:0] $end
|
|
$var wire 40 h& product_ext [39:0] $end
|
|
$var wire 32 i& product [31:0] $end
|
|
$var wire 40 j& acc_out [39:0] $end
|
|
$var parameter 32 k& ACC_WIDTH $end
|
|
$var parameter 32 l& DATA_WIDTH $end
|
|
$var parameter 64 m& PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac1 $end
|
|
$var wire 40 n& acc_in [39:0] $end
|
|
$var wire 16 o& w [15:0] $end
|
|
$var wire 16 p& x [15:0] $end
|
|
$var wire 40 q& product_ext [39:0] $end
|
|
$var wire 32 r& product [31:0] $end
|
|
$var wire 40 s& acc_out [39:0] $end
|
|
$var parameter 32 t& ACC_WIDTH $end
|
|
$var parameter 32 u& DATA_WIDTH $end
|
|
$var parameter 64 v& PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac2 $end
|
|
$var wire 40 w& acc_in [39:0] $end
|
|
$var wire 16 x& w [15:0] $end
|
|
$var wire 16 y& x [15:0] $end
|
|
$var wire 40 z& product_ext [39:0] $end
|
|
$var wire 32 {& product [31:0] $end
|
|
$var wire 40 |& acc_out [39:0] $end
|
|
$var parameter 32 }& ACC_WIDTH $end
|
|
$var parameter 32 ~& DATA_WIDTH $end
|
|
$var parameter 64 !' PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 "' acc_in [39:0] $end
|
|
$var wire 16 #' w [15:0] $end
|
|
$var wire 16 $' x [15:0] $end
|
|
$var wire 40 %' product_ext [39:0] $end
|
|
$var wire 32 &' product [31:0] $end
|
|
$var wire 40 '' acc_out [39:0] $end
|
|
$var parameter 32 (' ACC_WIDTH $end
|
|
$var parameter 32 )' DATA_WIDTH $end
|
|
$var parameter 64 *' PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 +' acc_in [39:0] $end
|
|
$var wire 16 ,' w [15:0] $end
|
|
$var wire 16 -' x [15:0] $end
|
|
$var wire 40 .' product_ext [39:0] $end
|
|
$var wire 32 /' product [31:0] $end
|
|
$var wire 40 0' acc_out [39:0] $end
|
|
$var parameter 32 1' ACC_WIDTH $end
|
|
$var parameter 32 2' DATA_WIDTH $end
|
|
$var parameter 64 3' PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 4' acc_in [39:0] $end
|
|
$var wire 16 5' w [15:0] $end
|
|
$var wire 16 6' x [15:0] $end
|
|
$var wire 40 7' product_ext [39:0] $end
|
|
$var wire 32 8' product [31:0] $end
|
|
$var wire 40 9' acc_out [39:0] $end
|
|
$var parameter 32 :' ACC_WIDTH $end
|
|
$var parameter 32 ;' DATA_WIDTH $end
|
|
$var parameter 64 <' PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 =' acc_in [39:0] $end
|
|
$var wire 16 >' w [15:0] $end
|
|
$var wire 16 ?' x [15:0] $end
|
|
$var wire 40 @' product_ext [39:0] $end
|
|
$var wire 32 A' product [31:0] $end
|
|
$var wire 40 B' acc_out [39:0] $end
|
|
$var parameter 32 C' ACC_WIDTH $end
|
|
$var parameter 32 D' DATA_WIDTH $end
|
|
$var parameter 64 E' PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 F' acc_in [39:0] $end
|
|
$var wire 16 G' w [15:0] $end
|
|
$var wire 16 H' x [15:0] $end
|
|
$var wire 40 I' product_ext [39:0] $end
|
|
$var wire 32 J' product [31:0] $end
|
|
$var wire 40 K' acc_out [39:0] $end
|
|
$var parameter 32 L' ACC_WIDTH $end
|
|
$var parameter 32 M' DATA_WIDTH $end
|
|
$var parameter 64 N' PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[5] $end
|
|
$var parameter 4 O' n $end
|
|
$scope module u_neuron $end
|
|
$var wire 16 P' bias [15:0] $end
|
|
$var wire 16 Q' bias_ext_small [15:0] $end
|
|
$var wire 1 + clk $end
|
|
$var wire 1 , rst $end
|
|
$var wire 1 - start $end
|
|
$var wire 1024 R' w_bus [1023:0] $end
|
|
$var wire 1024 S' x_bus [1023:0] $end
|
|
$var wire 128 T' x_group [127:0] $end
|
|
$var wire 128 U' w_group [127:0] $end
|
|
$var wire 40 V' final_value [39:0] $end
|
|
$var wire 40 W' final_acc [39:0] $end
|
|
$var wire 40 X' bias_ext [39:0] $end
|
|
$var wire 40 Y' acc_next [39:0] $end
|
|
$var parameter 32 Z' ACC_WIDTH $end
|
|
$var parameter 32 [' DATA_WIDTH $end
|
|
$var parameter 32 \' FRAC_BITS $end
|
|
$var parameter 32 ]' GROUPS $end
|
|
$var parameter 32 ^' GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 _' N_INPUTS $end
|
|
$var parameter 32 `' PARALLEL $end
|
|
$var reg 40 a' acc [39:0] $end
|
|
$var reg 1 b' busy $end
|
|
$var reg 1 c' done $end
|
|
$var reg 3 d' group_index [2:0] $end
|
|
$var reg 16 e' y [15:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 40 f' acc_in [39:0] $end
|
|
$var wire 128 g' w_bus [127:0] $end
|
|
$var wire 128 h' x_bus [127:0] $end
|
|
$var wire 40 i' sum [39:0] $end
|
|
$var wire 40 j' s5 [39:0] $end
|
|
$var wire 40 k' s4 [39:0] $end
|
|
$var wire 40 l' s3 [39:0] $end
|
|
$var wire 40 m' s2 [39:0] $end
|
|
$var wire 40 n' s1 [39:0] $end
|
|
$var wire 40 o' s0 [39:0] $end
|
|
$var wire 40 p' m7 [39:0] $end
|
|
$var wire 40 q' m6 [39:0] $end
|
|
$var wire 40 r' m5 [39:0] $end
|
|
$var wire 40 s' m4 [39:0] $end
|
|
$var wire 40 t' m3 [39:0] $end
|
|
$var wire 40 u' m2 [39:0] $end
|
|
$var wire 40 v' m1 [39:0] $end
|
|
$var wire 40 w' m0 [39:0] $end
|
|
$var wire 40 x' acc_out [39:0] $end
|
|
$var parameter 32 y' ACC_WIDTH $end
|
|
$var parameter 32 z' DATA_WIDTH $end
|
|
$scope module mac0 $end
|
|
$var wire 40 {' acc_in [39:0] $end
|
|
$var wire 16 |' w [15:0] $end
|
|
$var wire 16 }' x [15:0] $end
|
|
$var wire 40 ~' product_ext [39:0] $end
|
|
$var wire 32 !( product [31:0] $end
|
|
$var wire 40 "( acc_out [39:0] $end
|
|
$var parameter 32 #( ACC_WIDTH $end
|
|
$var parameter 32 $( DATA_WIDTH $end
|
|
$var parameter 64 %( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac1 $end
|
|
$var wire 40 &( acc_in [39:0] $end
|
|
$var wire 16 '( w [15:0] $end
|
|
$var wire 16 (( x [15:0] $end
|
|
$var wire 40 )( product_ext [39:0] $end
|
|
$var wire 32 *( product [31:0] $end
|
|
$var wire 40 +( acc_out [39:0] $end
|
|
$var parameter 32 ,( ACC_WIDTH $end
|
|
$var parameter 32 -( DATA_WIDTH $end
|
|
$var parameter 64 .( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac2 $end
|
|
$var wire 40 /( acc_in [39:0] $end
|
|
$var wire 16 0( w [15:0] $end
|
|
$var wire 16 1( x [15:0] $end
|
|
$var wire 40 2( product_ext [39:0] $end
|
|
$var wire 32 3( product [31:0] $end
|
|
$var wire 40 4( acc_out [39:0] $end
|
|
$var parameter 32 5( ACC_WIDTH $end
|
|
$var parameter 32 6( DATA_WIDTH $end
|
|
$var parameter 64 7( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 8( acc_in [39:0] $end
|
|
$var wire 16 9( w [15:0] $end
|
|
$var wire 16 :( x [15:0] $end
|
|
$var wire 40 ;( product_ext [39:0] $end
|
|
$var wire 32 <( product [31:0] $end
|
|
$var wire 40 =( acc_out [39:0] $end
|
|
$var parameter 32 >( ACC_WIDTH $end
|
|
$var parameter 32 ?( DATA_WIDTH $end
|
|
$var parameter 64 @( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 A( acc_in [39:0] $end
|
|
$var wire 16 B( w [15:0] $end
|
|
$var wire 16 C( x [15:0] $end
|
|
$var wire 40 D( product_ext [39:0] $end
|
|
$var wire 32 E( product [31:0] $end
|
|
$var wire 40 F( acc_out [39:0] $end
|
|
$var parameter 32 G( ACC_WIDTH $end
|
|
$var parameter 32 H( DATA_WIDTH $end
|
|
$var parameter 64 I( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 J( acc_in [39:0] $end
|
|
$var wire 16 K( w [15:0] $end
|
|
$var wire 16 L( x [15:0] $end
|
|
$var wire 40 M( product_ext [39:0] $end
|
|
$var wire 32 N( product [31:0] $end
|
|
$var wire 40 O( acc_out [39:0] $end
|
|
$var parameter 32 P( ACC_WIDTH $end
|
|
$var parameter 32 Q( DATA_WIDTH $end
|
|
$var parameter 64 R( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 S( acc_in [39:0] $end
|
|
$var wire 16 T( w [15:0] $end
|
|
$var wire 16 U( x [15:0] $end
|
|
$var wire 40 V( product_ext [39:0] $end
|
|
$var wire 32 W( product [31:0] $end
|
|
$var wire 40 X( acc_out [39:0] $end
|
|
$var parameter 32 Y( ACC_WIDTH $end
|
|
$var parameter 32 Z( DATA_WIDTH $end
|
|
$var parameter 64 [( PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 \( acc_in [39:0] $end
|
|
$var wire 16 ]( w [15:0] $end
|
|
$var wire 16 ^( x [15:0] $end
|
|
$var wire 40 _( product_ext [39:0] $end
|
|
$var wire 32 `( product [31:0] $end
|
|
$var wire 40 a( acc_out [39:0] $end
|
|
$var parameter 32 b( ACC_WIDTH $end
|
|
$var parameter 32 c( DATA_WIDTH $end
|
|
$var parameter 64 d( PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[6] $end
|
|
$var parameter 4 e( n $end
|
|
$scope module u_neuron $end
|
|
$var wire 16 f( bias [15:0] $end
|
|
$var wire 16 g( bias_ext_small [15:0] $end
|
|
$var wire 1 + clk $end
|
|
$var wire 1 , rst $end
|
|
$var wire 1 - start $end
|
|
$var wire 1024 h( w_bus [1023:0] $end
|
|
$var wire 1024 i( x_bus [1023:0] $end
|
|
$var wire 128 j( x_group [127:0] $end
|
|
$var wire 128 k( w_group [127:0] $end
|
|
$var wire 40 l( final_value [39:0] $end
|
|
$var wire 40 m( final_acc [39:0] $end
|
|
$var wire 40 n( bias_ext [39:0] $end
|
|
$var wire 40 o( acc_next [39:0] $end
|
|
$var parameter 32 p( ACC_WIDTH $end
|
|
$var parameter 32 q( DATA_WIDTH $end
|
|
$var parameter 32 r( FRAC_BITS $end
|
|
$var parameter 32 s( GROUPS $end
|
|
$var parameter 32 t( GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 u( N_INPUTS $end
|
|
$var parameter 32 v( PARALLEL $end
|
|
$var reg 40 w( acc [39:0] $end
|
|
$var reg 1 x( busy $end
|
|
$var reg 1 y( done $end
|
|
$var reg 3 z( group_index [2:0] $end
|
|
$var reg 16 {( y [15:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 40 |( acc_in [39:0] $end
|
|
$var wire 128 }( w_bus [127:0] $end
|
|
$var wire 128 ~( x_bus [127:0] $end
|
|
$var wire 40 !) sum [39:0] $end
|
|
$var wire 40 ") s5 [39:0] $end
|
|
$var wire 40 #) s4 [39:0] $end
|
|
$var wire 40 $) s3 [39:0] $end
|
|
$var wire 40 %) s2 [39:0] $end
|
|
$var wire 40 &) s1 [39:0] $end
|
|
$var wire 40 ') s0 [39:0] $end
|
|
$var wire 40 () m7 [39:0] $end
|
|
$var wire 40 )) m6 [39:0] $end
|
|
$var wire 40 *) m5 [39:0] $end
|
|
$var wire 40 +) m4 [39:0] $end
|
|
$var wire 40 ,) m3 [39:0] $end
|
|
$var wire 40 -) m2 [39:0] $end
|
|
$var wire 40 .) m1 [39:0] $end
|
|
$var wire 40 /) m0 [39:0] $end
|
|
$var wire 40 0) acc_out [39:0] $end
|
|
$var parameter 32 1) ACC_WIDTH $end
|
|
$var parameter 32 2) DATA_WIDTH $end
|
|
$scope module mac0 $end
|
|
$var wire 40 3) acc_in [39:0] $end
|
|
$var wire 16 4) w [15:0] $end
|
|
$var wire 16 5) x [15:0] $end
|
|
$var wire 40 6) product_ext [39:0] $end
|
|
$var wire 32 7) product [31:0] $end
|
|
$var wire 40 8) acc_out [39:0] $end
|
|
$var parameter 32 9) ACC_WIDTH $end
|
|
$var parameter 32 :) DATA_WIDTH $end
|
|
$var parameter 64 ;) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac1 $end
|
|
$var wire 40 <) acc_in [39:0] $end
|
|
$var wire 16 =) w [15:0] $end
|
|
$var wire 16 >) x [15:0] $end
|
|
$var wire 40 ?) product_ext [39:0] $end
|
|
$var wire 32 @) product [31:0] $end
|
|
$var wire 40 A) acc_out [39:0] $end
|
|
$var parameter 32 B) ACC_WIDTH $end
|
|
$var parameter 32 C) DATA_WIDTH $end
|
|
$var parameter 64 D) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac2 $end
|
|
$var wire 40 E) acc_in [39:0] $end
|
|
$var wire 16 F) w [15:0] $end
|
|
$var wire 16 G) x [15:0] $end
|
|
$var wire 40 H) product_ext [39:0] $end
|
|
$var wire 32 I) product [31:0] $end
|
|
$var wire 40 J) acc_out [39:0] $end
|
|
$var parameter 32 K) ACC_WIDTH $end
|
|
$var parameter 32 L) DATA_WIDTH $end
|
|
$var parameter 64 M) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 N) acc_in [39:0] $end
|
|
$var wire 16 O) w [15:0] $end
|
|
$var wire 16 P) x [15:0] $end
|
|
$var wire 40 Q) product_ext [39:0] $end
|
|
$var wire 32 R) product [31:0] $end
|
|
$var wire 40 S) acc_out [39:0] $end
|
|
$var parameter 32 T) ACC_WIDTH $end
|
|
$var parameter 32 U) DATA_WIDTH $end
|
|
$var parameter 64 V) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 W) acc_in [39:0] $end
|
|
$var wire 16 X) w [15:0] $end
|
|
$var wire 16 Y) x [15:0] $end
|
|
$var wire 40 Z) product_ext [39:0] $end
|
|
$var wire 32 [) product [31:0] $end
|
|
$var wire 40 \) acc_out [39:0] $end
|
|
$var parameter 32 ]) ACC_WIDTH $end
|
|
$var parameter 32 ^) DATA_WIDTH $end
|
|
$var parameter 64 _) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 `) acc_in [39:0] $end
|
|
$var wire 16 a) w [15:0] $end
|
|
$var wire 16 b) x [15:0] $end
|
|
$var wire 40 c) product_ext [39:0] $end
|
|
$var wire 32 d) product [31:0] $end
|
|
$var wire 40 e) acc_out [39:0] $end
|
|
$var parameter 32 f) ACC_WIDTH $end
|
|
$var parameter 32 g) DATA_WIDTH $end
|
|
$var parameter 64 h) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 i) acc_in [39:0] $end
|
|
$var wire 16 j) w [15:0] $end
|
|
$var wire 16 k) x [15:0] $end
|
|
$var wire 40 l) product_ext [39:0] $end
|
|
$var wire 32 m) product [31:0] $end
|
|
$var wire 40 n) acc_out [39:0] $end
|
|
$var parameter 32 o) ACC_WIDTH $end
|
|
$var parameter 32 p) DATA_WIDTH $end
|
|
$var parameter 64 q) PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 r) acc_in [39:0] $end
|
|
$var wire 16 s) w [15:0] $end
|
|
$var wire 16 t) x [15:0] $end
|
|
$var wire 40 u) product_ext [39:0] $end
|
|
$var wire 32 v) product [31:0] $end
|
|
$var wire 40 w) acc_out [39:0] $end
|
|
$var parameter 32 x) ACC_WIDTH $end
|
|
$var parameter 32 y) DATA_WIDTH $end
|
|
$var parameter 64 z) PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope begin GEN_NEURON[7] $end
|
|
$var parameter 4 {) n $end
|
|
$scope module u_neuron $end
|
|
$var wire 16 |) bias [15:0] $end
|
|
$var wire 16 }) bias_ext_small [15:0] $end
|
|
$var wire 1 + clk $end
|
|
$var wire 1 , rst $end
|
|
$var wire 1 - start $end
|
|
$var wire 1024 ~) w_bus [1023:0] $end
|
|
$var wire 1024 !* x_bus [1023:0] $end
|
|
$var wire 128 "* x_group [127:0] $end
|
|
$var wire 128 #* w_group [127:0] $end
|
|
$var wire 40 $* final_value [39:0] $end
|
|
$var wire 40 %* final_acc [39:0] $end
|
|
$var wire 40 &* bias_ext [39:0] $end
|
|
$var wire 40 '* acc_next [39:0] $end
|
|
$var parameter 32 (* ACC_WIDTH $end
|
|
$var parameter 32 )* DATA_WIDTH $end
|
|
$var parameter 32 ** FRAC_BITS $end
|
|
$var parameter 32 +* GROUPS $end
|
|
$var parameter 32 ,* GROUP_INDEX_WIDTH $end
|
|
$var parameter 32 -* N_INPUTS $end
|
|
$var parameter 32 .* PARALLEL $end
|
|
$var reg 40 /* acc [39:0] $end
|
|
$var reg 1 0* busy $end
|
|
$var reg 1 1* done $end
|
|
$var reg 3 2* group_index [2:0] $end
|
|
$var reg 16 3* y [15:0] $end
|
|
$scope module u_mac8 $end
|
|
$var wire 40 4* acc_in [39:0] $end
|
|
$var wire 128 5* w_bus [127:0] $end
|
|
$var wire 128 6* x_bus [127:0] $end
|
|
$var wire 40 7* sum [39:0] $end
|
|
$var wire 40 8* s5 [39:0] $end
|
|
$var wire 40 9* s4 [39:0] $end
|
|
$var wire 40 :* s3 [39:0] $end
|
|
$var wire 40 ;* s2 [39:0] $end
|
|
$var wire 40 <* s1 [39:0] $end
|
|
$var wire 40 =* s0 [39:0] $end
|
|
$var wire 40 >* m7 [39:0] $end
|
|
$var wire 40 ?* m6 [39:0] $end
|
|
$var wire 40 @* m5 [39:0] $end
|
|
$var wire 40 A* m4 [39:0] $end
|
|
$var wire 40 B* m3 [39:0] $end
|
|
$var wire 40 C* m2 [39:0] $end
|
|
$var wire 40 D* m1 [39:0] $end
|
|
$var wire 40 E* m0 [39:0] $end
|
|
$var wire 40 F* acc_out [39:0] $end
|
|
$var parameter 32 G* ACC_WIDTH $end
|
|
$var parameter 32 H* DATA_WIDTH $end
|
|
$scope module mac0 $end
|
|
$var wire 40 I* acc_in [39:0] $end
|
|
$var wire 16 J* w [15:0] $end
|
|
$var wire 16 K* x [15:0] $end
|
|
$var wire 40 L* product_ext [39:0] $end
|
|
$var wire 32 M* product [31:0] $end
|
|
$var wire 40 N* acc_out [39:0] $end
|
|
$var parameter 32 O* ACC_WIDTH $end
|
|
$var parameter 32 P* DATA_WIDTH $end
|
|
$var parameter 64 Q* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac1 $end
|
|
$var wire 40 R* acc_in [39:0] $end
|
|
$var wire 16 S* w [15:0] $end
|
|
$var wire 16 T* x [15:0] $end
|
|
$var wire 40 U* product_ext [39:0] $end
|
|
$var wire 32 V* product [31:0] $end
|
|
$var wire 40 W* acc_out [39:0] $end
|
|
$var parameter 32 X* ACC_WIDTH $end
|
|
$var parameter 32 Y* DATA_WIDTH $end
|
|
$var parameter 64 Z* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac2 $end
|
|
$var wire 40 [* acc_in [39:0] $end
|
|
$var wire 16 \* w [15:0] $end
|
|
$var wire 16 ]* x [15:0] $end
|
|
$var wire 40 ^* product_ext [39:0] $end
|
|
$var wire 32 _* product [31:0] $end
|
|
$var wire 40 `* acc_out [39:0] $end
|
|
$var parameter 32 a* ACC_WIDTH $end
|
|
$var parameter 32 b* DATA_WIDTH $end
|
|
$var parameter 64 c* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac3 $end
|
|
$var wire 40 d* acc_in [39:0] $end
|
|
$var wire 16 e* w [15:0] $end
|
|
$var wire 16 f* x [15:0] $end
|
|
$var wire 40 g* product_ext [39:0] $end
|
|
$var wire 32 h* product [31:0] $end
|
|
$var wire 40 i* acc_out [39:0] $end
|
|
$var parameter 32 j* ACC_WIDTH $end
|
|
$var parameter 32 k* DATA_WIDTH $end
|
|
$var parameter 64 l* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac4 $end
|
|
$var wire 40 m* acc_in [39:0] $end
|
|
$var wire 16 n* w [15:0] $end
|
|
$var wire 16 o* x [15:0] $end
|
|
$var wire 40 p* product_ext [39:0] $end
|
|
$var wire 32 q* product [31:0] $end
|
|
$var wire 40 r* acc_out [39:0] $end
|
|
$var parameter 32 s* ACC_WIDTH $end
|
|
$var parameter 32 t* DATA_WIDTH $end
|
|
$var parameter 64 u* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac5 $end
|
|
$var wire 40 v* acc_in [39:0] $end
|
|
$var wire 16 w* w [15:0] $end
|
|
$var wire 16 x* x [15:0] $end
|
|
$var wire 40 y* product_ext [39:0] $end
|
|
$var wire 32 z* product [31:0] $end
|
|
$var wire 40 {* acc_out [39:0] $end
|
|
$var parameter 32 |* ACC_WIDTH $end
|
|
$var parameter 32 }* DATA_WIDTH $end
|
|
$var parameter 64 ~* PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac6 $end
|
|
$var wire 40 !+ acc_in [39:0] $end
|
|
$var wire 16 "+ w [15:0] $end
|
|
$var wire 16 #+ x [15:0] $end
|
|
$var wire 40 $+ product_ext [39:0] $end
|
|
$var wire 32 %+ product [31:0] $end
|
|
$var wire 40 &+ acc_out [39:0] $end
|
|
$var parameter 32 '+ ACC_WIDTH $end
|
|
$var parameter 32 (+ DATA_WIDTH $end
|
|
$var parameter 64 )+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$scope module mac7 $end
|
|
$var wire 40 *+ acc_in [39:0] $end
|
|
$var wire 16 ++ w [15:0] $end
|
|
$var wire 16 ,+ x [15:0] $end
|
|
$var wire 40 -+ product_ext [39:0] $end
|
|
$var wire 32 .+ product [31:0] $end
|
|
$var wire 40 /+ acc_out [39:0] $end
|
|
$var parameter 32 0+ ACC_WIDTH $end
|
|
$var parameter 32 1+ DATA_WIDTH $end
|
|
$var parameter 64 2+ PROD_WIDTH $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$scope task run_layer $end
|
|
$upscope $end
|
|
$upscope $end
|
|
$enddefinitions $end
|
|
$comment Show the parameter values. $end
|
|
$dumpall
|
|
b100000 2+
|
|
b10000 1+
|
|
b101000 0+
|
|
b100000 )+
|
|
b10000 (+
|
|
b101000 '+
|
|
b100000 ~*
|
|
b10000 }*
|
|
b101000 |*
|
|
b100000 u*
|
|
b10000 t*
|
|
b101000 s*
|
|
b100000 l*
|
|
b10000 k*
|
|
b101000 j*
|
|
b100000 c*
|
|
b10000 b*
|
|
b101000 a*
|
|
b100000 Z*
|
|
b10000 Y*
|
|
b101000 X*
|
|
b100000 Q*
|
|
b10000 P*
|
|
b101000 O*
|
|
b10000 H*
|
|
b101000 G*
|
|
b1000 .*
|
|
b1000000 -*
|
|
b11 ,*
|
|
b1000 +*
|
|
b1000 **
|
|
b10000 )*
|
|
b101000 (*
|
|
b111 {)
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