micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
94 lines
3.3 KiB
Verilog
94 lines
3.3 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// CRC32_BYTE TESTBENCH
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//
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// Oracle: tools/flash_catalog/oracle.py's crc32() (Python stdlib
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// zlib.crc32) -- an independent implementation, not derived from
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// rtl/crc32.v. Expected values below were generated by running that
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// script (see its own __main__ block and WORKLOG.md's F4 entry for
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// the exact invocation), not by reading rtl/crc32.v's algorithm and
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// re-deriving them by hand.
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// ================================================================
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module tb;
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reg [31:0] crc_in;
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reg [7:0] data;
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wire [31:0] crc_out;
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crc32_byte dut (.crc_in(crc_in), .data(data), .crc_out(crc_out));
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integer errors;
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integer i;
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reg [31:0] crc;
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task automatic check(input [31:0] got, input [31:0] exp, input [255:0] label);
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begin
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if (got !== exp) begin
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$display("FAIL: %0s got=%08h exp=%08h", label, got, exp);
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errors = errors + 1;
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end else begin
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$display("PASS: %0s = %08h", label, got);
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end
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end
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endtask
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initial begin
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errors = 0;
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// TEST 1: CRC32 of the empty message is, by definition,
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// 0x00000000 (init 0xFFFFFFFF XOR final 0xFFFFFFFF, no bytes
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// processed) -- a fixed, well-known property of this exact
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// algorithm, not something derived from either implementation.
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check(32'hFFFFFFFF ^ 32'hFFFFFFFF, 32'h00000000, "TEST1 empty-message identity");
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// TEST 2: single byte 0x00. Oracle (Python):
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// >>> zlib.crc32(bytes([0x00])) -> 0xd202ef8d
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crc = 32'hFFFFFFFF;
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#1 crc_in = crc; data = 8'h00; #1;
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crc = crc_out;
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check(crc ^ 32'hFFFFFFFF, 32'hd202ef8d, "TEST2 single byte 0x00");
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// TEST 3: ASCII "123456789" (the standard CRC32 check-value
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// vector quoted by every CRC32 reference table, e.g.
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// Rocksoft's "check value" for CRC-32/ISO-HDLC = 0xCBF43926
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// -- an independent, textbook-published constant, not
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// computed by either this RTL or the Python oracle).
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begin : t3
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reg [7:0] msg [0:8];
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msg[0]=8'h31; msg[1]=8'h32; msg[2]=8'h33; msg[3]=8'h34; msg[4]=8'h35;
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msg[5]=8'h36; msg[6]=8'h37; msg[7]=8'h38; msg[8]=8'h39;
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crc = 32'hFFFFFFFF;
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for (i = 0; i < 9; i = i + 1) begin
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crc_in = crc; data = msg[i]; #1;
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crc = crc_out;
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#1;
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end
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check(crc ^ 32'hFFFFFFFF, 32'hCBF43926, "TEST3 \"123456789\" textbook check-value");
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end
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// TEST 4: 32-byte payload 0x10..0x2F, matching
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// tools/flash_catalog/oracle.py's __main__ self-check output
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// exactly (run: `python3 tools/flash_catalog/oracle.py`) --
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// oracle printed CRC32 = 0x3b8cfe40 for this exact payload.
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begin : t4
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crc = 32'hFFFFFFFF;
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for (i = 0; i < 32; i = i + 1) begin
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crc_in = crc; data = 8'h10 + i[7:0]; #1;
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crc = crc_out;
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#1;
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end
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check(crc ^ 32'hFFFFFFFF, 32'h3b8cfe40, "TEST4 32B payload vs Python oracle.py");
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end
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if (errors == 0)
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$display("ALL TESTS PASSED");
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else
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$display("FAILED: %0d error(s)", errors);
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$finish;
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end
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endmodule
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