FPGA-Neural/hardware/v2/nms/reports/nms_prefetch_sweep.csv at 124a0dbca0254cc40352e80b5ef75b5cf1d73cd0

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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM

FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

2026-09-06 13:39:55 +02:00

2.5 KiB

Raw Blame History

1	configuration	n_slots	pfd	latency_class	cycles	psram_util_pct	weight_stall_pct	prefetch_effectiveness_pct	sustained_mac_per_cycle	theoretical_mac_per_cycle	utilization_pct_of_theoretical	fmax_mhz	lut4	ccu2c	ff	dsp	bram	classification
2	current_nms_baseline	2	n/a	real_v1_psram	185645	90.4	92.5	0.0	0.1765	16	1.10	93.10	1948	266	3522	16	0	POST-P&R MEASURED Fmax/resources + RTL SIMULATION cycles (EXP-0022)
3	nms_plus_prefetch	1	1	real_v1_psram	181489	59.3	87.91	0.02	0.1806	8	2.26	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
4	nms_plus_prefetch	1	2	real_v1_psram	162876	66.4	86.44	0.39	0.2012	8	2.52	132.26	1333	203	2245	8	0	POST-P&R MEASURED Fmax/resources + RTL SIMULATION cycles (EXP-0024)
5	nms_plus_prefetch	1	4	real_v1_psram	162876	66.4	86.44	0.39	0.2012	8	2.52	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
6	nms_plus_prefetch	1	8	real_v1_psram	162876	66.4	86.44	0.39	0.2012	8	2.52	137.76	1464	200	2245	8	0	POST-P&R MEASURED Fmax/resources + RTL SIMULATION cycles (EXP-0024)
7	nms_plus_prefetch	1	16	real_v1_psram	162876	66.4	86.44	0.39	0.2012	8	2.52	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
8	nms_plus_prefetch	2	1	real_v1_psram	185410	90.5	93.32	0.78	0.1767	16	1.10	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
9	nms_plus_prefetch	2	2	real_v1_psram	185408	90.5	93.32	0.78	0.1767	16	1.10	97.16	1941	368	3449	16	0	POST-P&R MEASURED Fmax/resources + RTL SIMULATION cycles (EXP-0024)
10	nms_plus_prefetch	2	4	real_v1_psram	185404	90.5	93.32	0.78	0.1767	16	1.10	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
11	nms_plus_prefetch	2	8	real_v1_psram	185398	90.5	93.32	0.78	0.1767	16	1.10	95.25	1908	362	3449	16	0	POST-P&R MEASURED Fmax/resources + RTL SIMULATION cycles (EXP-0024)
12	nms_plus_prefetch	2	16	real_v1_psram	185390	90.5	93.33	0.78	0.1768	16	1.11	n/a	n/a	n/a	n/a	n/a	n/a	RTL SIMULATION (EXP-0024)
13	ideal_memory_pfd_sweep	1_or_2	1	latency_0-1_cyc	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	IDEAL-MEMORY SIMULATION (EXP-0023) -- min PFD for >=90% util at latency 0-1 is PFD=4
14	ideal_memory_pfd_sweep	1_or_2	1	latency_2-4_cyc	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	IDEAL-MEMORY SIMULATION (EXP-0023) -- min PFD for >=90% util at latency 2-4 is PFD=8
15	ideal_memory_pfd_sweep	1_or_2	1	latency_8_cyc	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	IDEAL-MEMORY SIMULATION (EXP-0023) -- min PFD for >=90% util at latency 8 is PFD=16
16	ideal_memory_pfd_sweep	1_or_2	1	latency_16_cyc	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	n/a	IDEAL-MEMORY SIMULATION (EXP-0023) -- min PFD for >=90% util at latency 16 is PFD=32

2.5 KiB Raw Blame History

2.5 KiB

Raw Blame History