micheleandClaude Sonnet 5
124a0dbca0
Promotes EXP-0062's own procedural testbench sequence (prefetch -> buffer swap -> per-tile gather -> operand streaming -> result capture) into real synthesizable RTL, wrapping layer_prefetch_ctrl.v -> layer_weight_buffer.v -> weight_tile_gather.v -> neural_processor_packed.v behind a 9-state FSM matching neural_director_packed.v's own per-slot contract. First run: 4/9 failed, deterministic. Root-caused (not a sequencer bug): the testbench's own w_base computation wrongly treated it as a byte address needing *2 conversion; layer_prefetch_ctrl.v expects a word address directly, and packed_slot.v already passes it through unconverted to match. Fixed the testbench. Re-verified: 9/9 PASS, 0 errors, bit-exact results and correct node_id/result_addr passthrough, entirely self-sequenced (no testbench-side procedural driving of the sub-modules). Full writeup in hardware/v2/logs/experiments.log EXP-0065. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC