micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
9 lines
832 B
CSV
9 lines
832 B
CSV
layer,value_mb_s,pct_of_nominal,classification,source
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theoretical_sdram_nominal,160.0,100.0,THEORETICAL,2 bytes x16 x 80MHz
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controller_max_isolated_burst4,64.0,40.0,RTL SIMULATION,STEP16 EXP-0041 isolated regression (10 cyc/txn @80MHz, 8 bytes/txn)
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controller_max_isolated_burst8_packed,~114.3,~71.4,RTL SIMULATION,STEP18 isolated pack128 regression (16 cyc/txn @80MHz for a full pair + amortized 1-cyc cache hit = 17cyc/16bytes)
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realistic_sustained_n4_baseline,53.04,33.2,INTEGRATED BENCHMARK,STEP16/17 N4 D-Stress (BURST_LEN=4, 1 tile/txn)
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realistic_sustained_n4_pack128,58.34,36.5,INTEGRATED BENCHMARK,STEP18 N4 D-Stress (BURST_LEN=8 packed, N_ENTRIES=4 cache)
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realistic_sustained_n2_baseline,50.26,31.4,INTEGRATED BENCHMARK,STEP16/17 N2 D-Stress
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realistic_sustained_n2_pack128,55.30,34.6,INTEGRATED BENCHMARK,STEP18 N2 D-Stress
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