micheleandClaude Sonnet 5
55c827bedf
PSRAM page-mode read burst support in psram_controller.v: enables the ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register software-access sequence at boot (disabled by default on the real chip), then keeps CE#/OE# asserted after a read so a same-page continuation only pays tAPA (20ns) instead of a full tAA (70ns) random access, with automatic tCEM-safe session closing. Only a WRITE closes the page -- byte-enable changes do not, since int8_memory_access.v alternates them on nearly every access and an early implementation attempt that treated them as a close condition measured a real regression (53.25->61.25 cycles/edge) before being corrected (53.25->37.53 cycles/edge, +42% gather bandwidth). sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement (with a real Verilog same-timestep event-ordering race found and fixed via a #0 sync) so the regression proves real timing compliance, not just data correctness. New sim/psram_page_mode_tb.v; full 26-file regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and 65.13MHz (P8) -- still under the 80MHz target but not regressed, with the critical path confirmed (not assumed) to remain entirely inside neuron_parallel's accumulate chain, never psram_controller. Also includes this session's other already-validated work: the graph engine (Type #2 sparse-graph network: act_buffer, graph_engine, netasm host assembler), real CABGA381 pinout (.lpf, place&route verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing closure logs -- all previously uncommitted, documented in WORKLOG.md. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
452 lines
44 KiB
Plaintext
452 lines
44 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 3458/43848 7%
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Info: logic LUTs: 2682/43848 6%
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Info: carry LUTs: 776/43848 1%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 2399/43848 5%
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Info: Packing IOs..
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Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
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Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
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Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
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Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
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Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
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Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
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Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
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Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
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Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
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Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
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Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
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Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
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Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
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Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
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Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
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Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 536 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x513f90b6
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Info: Device utilisation:
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Info: TRELLIS_IO: 51/ 245 20%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 2/ 108 1%
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Info: MULT18X18D: 16/ 72 22%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 2399/ 43848 5%
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Info: TRELLIS_COMB: 3636/ 43848 8%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 4055 cells, random placement wirelen = 319941.
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Info: at initial placer iter 0, wirelen = 7010
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Info: at initial placer iter 1, wirelen = 6087
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Info: at initial placer iter 2, wirelen = 6012
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Info: at initial placer iter 3, wirelen = 5729
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Info: Running main analytical placer, max placement attempts per cell = 4658878.
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Info: at iteration #1, type ALL: wirelen solved = 5663, spread = 48527, legal = 50567; time = 0.06s
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Info: at iteration #2, type ALL: wirelen solved = 7800, spread = 42352, legal = 44350; time = 0.05s
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Info: at iteration #3, type ALL: wirelen solved = 9798, spread = 37432, legal = 40738; time = 0.05s
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Info: at iteration #4, type ALL: wirelen solved = 10864, spread = 37121, legal = 39324; time = 0.05s
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Info: at iteration #5, type ALL: wirelen solved = 12586, spread = 38907, legal = 40580; time = 0.05s
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Info: at iteration #6, type ALL: wirelen solved = 12832, spread = 36734, legal = 37831; time = 0.05s
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Info: at iteration #7, type ALL: wirelen solved = 13463, spread = 37848, legal = 38735; time = 0.05s
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Info: at iteration #8, type ALL: wirelen solved = 14258, spread = 35521, legal = 37117; time = 0.05s
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Info: at iteration #9, type ALL: wirelen solved = 15056, spread = 34010, legal = 35291; time = 0.05s
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Info: at iteration #10, type ALL: wirelen solved = 14809, spread = 35098, legal = 38246; time = 0.05s
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Info: at iteration #11, type ALL: wirelen solved = 14899, spread = 34596, legal = 36885; time = 0.05s
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Info: at iteration #12, type ALL: wirelen solved = 15696, spread = 33811, legal = 36290; time = 0.04s
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Info: at iteration #13, type ALL: wirelen solved = 16284, spread = 33928, legal = 35084; time = 0.04s
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Info: at iteration #14, type ALL: wirelen solved = 17172, spread = 32966, legal = 34679; time = 0.04s
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Info: at iteration #15, type ALL: wirelen solved = 17271, spread = 32386, legal = 33811; time = 0.04s
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Info: at iteration #16, type ALL: wirelen solved = 16851, spread = 32594, legal = 33530; time = 0.04s
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Info: at iteration #17, type ALL: wirelen solved = 17239, spread = 32264, legal = 34153; time = 0.04s
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Info: at iteration #18, type ALL: wirelen solved = 17012, spread = 31846, legal = 33701; time = 0.05s
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Info: at iteration #19, type ALL: wirelen solved = 17055, spread = 32272, legal = 34126; time = 0.04s
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Info: at iteration #20, type ALL: wirelen solved = 17005, spread = 34042, legal = 35729; time = 0.04s
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Info: at iteration #21, type ALL: wirelen solved = 18281, spread = 32377, legal = 33375; time = 0.04s
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Info: at iteration #22, type ALL: wirelen solved = 17957, spread = 32693, legal = 34088; time = 0.04s
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Info: at iteration #23, type ALL: wirelen solved = 18920, spread = 32498, legal = 33038; time = 0.04s
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Info: at iteration #24, type ALL: wirelen solved = 18582, spread = 32188, legal = 33875; time = 0.04s
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Info: at iteration #25, type ALL: wirelen solved = 18222, spread = 32667, legal = 33367; time = 0.04s
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Info: at iteration #26, type ALL: wirelen solved = 18384, spread = 33230, legal = 33749; time = 0.04s
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Info: at iteration #27, type ALL: wirelen solved = 18225, spread = 32407, legal = 32986; time = 0.04s
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Info: at iteration #28, type ALL: wirelen solved = 18989, spread = 34326, legal = 35129; time = 0.04s
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Info: at iteration #29, type ALL: wirelen solved = 18996, spread = 34984, legal = 35613; time = 0.04s
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Info: at iteration #30, type ALL: wirelen solved = 18898, spread = 33843, legal = 34760; time = 0.04s
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Info: at iteration #31, type ALL: wirelen solved = 18999, spread = 32158, legal = 33134; time = 0.04s
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Info: at iteration #32, type ALL: wirelen solved = 18458, spread = 34402, legal = 36055; time = 0.04s
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Info: HeAP Placer Time: 1.87s
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Info: of which solving equations: 1.14s
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Info: of which spreading cells: 0.25s
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Info: of which strict legalisation: 0.17s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 2561, wirelen = 32986
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Info: at iteration #5: temp = 0.000000, timing cost = 2769, wirelen = 28411
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Info: at iteration #10: temp = 0.000000, timing cost = 2615, wirelen = 27319
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Info: at iteration #15: temp = 0.000000, timing cost = 2474, wirelen = 26677
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Info: at iteration #20: temp = 0.000000, timing cost = 2380, wirelen = 26444
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Info: at iteration #25: temp = 0.000000, timing cost = 2386, wirelen = 26363
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Info: at iteration #30: temp = 0.000000, timing cost = 2370, wirelen = 26328
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Info: at iteration #31: temp = 0.000000, timing cost = 2378, wirelen = 26323
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Info: SA placement time 2.75s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.29 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.08 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.64 ns
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Info: Slack histogram:
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Info: legend: * represents 18 endpoint(s)
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Info: + represents [1,18) endpoint(s)
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Info: [-10598, -9471) |+
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Info: [ -9471, -8344) |+
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Info: [ -8344, -7217) |*+
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Info: [ -7217, -6090) |*+
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Info: [ -6090, -4963) |+
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Info: [ -4963, -3836) |+
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Info: [ -3836, -2709) |+
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Info: [ -2709, -1582) |+
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Info: [ -1582, -455) |
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Info: [ -455, 672) |
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Info: [ 672, 1799) |*+
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Info: [ 1799, 2926) |+
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Info: [ 2926, 4053) |***+
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Info: [ 4053, 5180) |************************+
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Info: [ 5180, 6307) |*************************************+
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Info: [ 6307, 7434) |*******************************************+
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Info: [ 7434, 8561) |****************************************************+
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Info: [ 8561, 9688) |**************************************************+
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Info: [ 9688, 10815) |************************************************************
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Info: [ 10815, 11942) |*********************************+
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Info: Checksum: 0x1d006fc9
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 18744 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 576 423 | 576 423 | 18409| 0.39 0.39|
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Info: 2000 | 984 1015 | 408 592 | 17894| 0.22 0.61|
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Info: 3000 | 1463 1536 | 479 521 | 17469| 0.19 0.81|
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Info: 4000 | 1965 2034 | 502 498 | 17025| 0.14 0.95|
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Info: 5000 | 2495 2504 | 530 470 | 16679| 0.14 1.09|
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Info: 6000 | 2977 3022 | 482 518 | 16308| 0.16 1.25|
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Info: 7000 | 3416 3583 | 439 561 | 15946| 0.11 1.36|
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Info: 8000 | 3938 4061 | 522 478 | 15547| 0.15 1.51|
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Info: 9000 | 4377 4622 | 439 561 | 15126| 0.15 1.66|
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Info: 10000 | 4795 5204 | 418 582 | 14768| 0.12 1.78|
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Info: 11000 | 5203 5796 | 408 592 | 14256| 0.10 1.88|
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Info: 12000 | 5760 6239 | 557 443 | 13925| 0.11 1.99|
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Info: 13000 | 6129 6870 | 369 631 | 13405| 0.10 2.09|
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Info: 14000 | 6323 7524 | 194 654 | 12648| 0.09 2.18|
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Info: 15000 | 6692 7994 | 369 470 | 12045| 0.07 2.25|
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Info: 16000 | 7327 8321 | 635 327 | 11729| 0.09 2.34|
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Info: 17000 | 7917 8665 | 590 344 | 11397| 0.10 2.44|
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Info: 18000 | 8489 9039 | 572 374 | 10983| 0.09 2.53|
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Info: 19000 | 9019 9484 | 530 445 | 10540| 0.08 2.62|
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Info: 20000 | 9623 9880 | 604 396 | 10168| 0.09 2.71|
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Info: 21000 | 10168 10325 | 545 445 | 9743| 0.09 2.80|
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Info: 22000 | 10406 11079 | 238 754 | 9004| 0.10 2.89|
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Info: 23000 | 10542 11943 | 136 864 | 8183| 0.13 3.02|
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Info: 24000 | 10654 12830 | 112 887 | 7334| 0.13 3.16|
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Info: 25000 | 10763 13721 | 109 891 | 6488| 0.15 3.30|
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Info: 26000 | 10911 14542 | 148 821 | 5720| 0.12 3.42|
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Info: 27000 | 11036 15369 | 125 827 | 4890| 0.12 3.54|
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Info: 28000 | 11150 16166 | 114 797 | 4040| 0.09 3.63|
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Info: 29000 | 11222 16986 | 72 820 | 3118| 0.08 3.71|
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Info: 30000 | 11280 17837 | 58 851 | 2180| 0.08 3.79|
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Info: 31000 | 11371 18714 | 91 877 | 1281| 0.10 3.88|
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Info: 32000 | 11386 19610 | 15 896 | 297| 0.13 4.01|
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Info: 32306 | 11393 19890 | 7 280 | 0| 0.04 4.05|
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Info: Routing complete.
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Info: Router1 time 4.05s
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Info: Checksum: 0x79c76f3f
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_graph_engine.u_neuron.group_index_TRELLIS_FF_Q_1.Q
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Info: routing 1.37 1.76 Net u_graph_engine.u_neuron.group_index[0] (21,6) -> (13,20)
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Info: Sink u_graph_engine.u_neuron.u_mac8.w_bus_PFUMX_Z_C0_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.94 Source u_graph_engine.u_neuron.u_mac8.w_bus_PFUMX_Z_C0_LUT4_Z.F
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Info: routing 1.50 3.44 Net u_graph_engine.u_neuron.u_mac8.w_bus_PFUMX_Z_C0[4] (13,20) -> (22,33)
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Info: Sink u_graph_engine.u_neuron.u_mac8.w_bus_PFUMX_Z_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 3.63 Source u_graph_engine.u_neuron.u_mac8.w_bus_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 1.53 5.16 Net u_graph_engine.u_neuron.w_group[23] (22,33) -> (22,46)
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Info: Sink u_graph_engine.u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9.B17
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.43-93.50
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Info: logic 3.07 8.23 Source u_graph_engine.u_neuron.u_mac8.GEN_MAC[2].u_mac.product_MULT18X18D_P9.P1
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Info: routing 2.39 10.61 Net u_graph_engine.u_neuron.u_mac8.products[2][1] (22,46) -> (20,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.B
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
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Info: logic 0.35 10.97 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO
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Info: routing 0.00 10.97 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_CIN (20,14) -> (20,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.03 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.03 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (20,14) -> (20,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.03 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.03 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (20,14) -> (20,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.08 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.08 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (20,14) -> (20,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.08 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.08 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (20,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.14 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.14 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.14 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.14 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.19 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.19 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.19 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.19 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.25 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.25 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 11.25 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 11.25 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 11.31 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 11.31 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,14) -> (21,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.29 11.60 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.F
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Info: routing 1.02 12.62 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1[0] (21,14) -> (21,5)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_PFUMX_Z_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 12.81 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.54 13.35 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[4] (21,5) -> (22,6)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1_B1_PFUMX_Z_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 13.54 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1_B1_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 1.03 14.57 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1_B1 (22,6) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.B
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Info: logic 0.35 14.93 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 14.93 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_CCU2C_S1_COUT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 14.98 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 14.98 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 14.98 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 14.98 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.04 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 15.04 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 15.04 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 15.04 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.10 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 15.10 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (20,9) -> (20,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 15.10 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 15.10 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (20,9) -> (21,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.15 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 15.15 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,9) -> (21,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 15.15 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 15.15 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (21,9) -> (21,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.06 15.21 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
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Info: routing 0.00 15.21 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (21,9) -> (21,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
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Info: logic 0.00 15.21 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
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Info: routing 0.00 15.21 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (21,9) -> (21,9)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.33 15.54 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.F
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Info: routing 0.82 16.35 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[1] (21,9) -> (21,11)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.35 16.71 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCO
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Info: routing 0.00 16.71 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_FCI_INT (21,11) -> (21,11)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCI
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Info: logic 0.00 16.71 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB1.FCO
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Info: routing 0.00 16.71 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT (21,11) -> (21,11)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.FCI
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:128.24-128.43
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Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
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Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
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Info: logic 0.33 17.04 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN$CCU2_COMB0.F
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Info: routing 0.61 17.65 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[2] (21,11) -> (22,11)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_LUT4_A_Z_LUT4_Z.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 17.83 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_LUT4_A_Z_LUT4_Z.F
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Info: routing 0.72 18.55 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_1_S1_CCU2C_S0_S1_LUT4_A_Z[3] (22,11) -> (20,12)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_Z_D_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 18.73 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_Z_D_LUT4_Z.F
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Info: routing 0.56 19.28 Net u_graph_engine.activation_reg_LUT4_D_Z_LUT4_Z_D[3] (20,12) -> (19,13)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 19.47 Source u_graph_engine.activation_reg_LUT4_D_Z_LUT4_Z.F
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Info: routing 0.52 19.98 Net u_graph_engine.activation_reg_LUT4_D_Z[4] (19,13) -> (19,14)
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Info: Sink u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_S1_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_4_BLUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 20.17 Source u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_S1_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_Z_4_BLUT_LUT4_Z.OFX
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Info: routing 0.35 20.53 Net u_graph_engine.activation_reg_LUT4_D_Z_CCU2C_S0_S1_LUT4_C_Z_PFUMX_BLUT_Z[0] (19,14) -> (19,14)
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Info: Sink u_graph_engine.u_neuron.y_TRELLIS_FF_Q_7.M
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Info: setup 0.00 20.53 Source u_graph_engine.u_neuron.y_TRELLIS_FF_Q_7.M
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Info: 7.58 ns logic, 12.94 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 2.96 2.96 Net rst$TRELLIS_IO_IN (0,17) -> (35,6)
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Info: Sink graph_rst_LUT4_Z.C
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:23.16-23.19
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Info: logic 0.18 3.14 Source graph_rst_LUT4_Z.F
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Info: routing 2.27 5.41 Net graph_rst (35,6) -> (17,20)
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Info: Sink u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.59 Source u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z_1.F
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Info: routing 2.39 7.98 Net u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[1] (17,20) -> (8,5)
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Info: Sink u_neuron_memory.w_mem[14]_TRELLIS_FF_Q_CE_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 8.16 Source u_neuron_memory.w_mem[14]_TRELLIS_FF_Q_CE_LUT4_Z.F
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Info: routing 0.80 8.96 Net u_neuron_memory.w_mem[14]_TRELLIS_FF_Q_CE (8,5) -> (8,2)
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Info: Sink u_neuron_memory.w_mem[14]_TRELLIS_FF_Q_6.CE
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Info: setup 0.00 8.96 Source u_neuron_memory.w_mem[14]_TRELLIS_FF_Q_6.CE
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Info: 0.54 ns logic, 8.42 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source u_psram_ctrl.dq_oe_TRELLIS_FF_Q.Q
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Info: routing 4.64 5.04 Net u_psram_ctrl.dq_oe (7,3) -> (88,26)
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Info: Sink psram_dq[10]$tr_io$invert_T.A
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Info: Defined in:
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Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/psram_controller.v:90.27-90.32
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Info: logic 0.18 5.22 Source psram_dq[10]$tr_io$invert_T.F
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Info: routing 0.74 5.96 Net psram_dq[10]$tr_io$invert_T$conn$Z (88,26) -> (90,26)
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Info: Sink psram_dq[10]$tr_io.T
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Info: 0.57 ns logic, 5.39 ns routing
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ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.72 MHz (FAIL at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.96 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.96 ns
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Info: Slack histogram:
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Info: legend: * represents 19 endpoint(s)
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Info: + represents [1,19) endpoint(s)
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Info: [ -8026, -7034) |+
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|
Info: [ -7034, -6042) |
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Info: [ -6042, -5050) |*+
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|
Info: [ -5050, -4058) |*+
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|
Info: [ -4058, -3066) |+
|
|
Info: [ -3066, -2074) |+
|
|
Info: [ -2074, -1082) |+
|
|
Info: [ -1082, -90) |+
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|
Info: [ -90, 902) |
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|
Info: [ 902, 1894) |
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Info: [ 1894, 2886) |
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Info: [ 2886, 3878) |+
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Info: [ 3878, 4870) |**+
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Info: [ 4870, 5862) |****************+
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Info: [ 5862, 6854) |************************************+
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Info: [ 6854, 7846) |**********************+
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Info: [ 7846, 8838) |*****************************************+
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|
Info: [ 8838, 9830) |************************************************************
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Info: [ 9830, 10822) |**********************************************************+
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Info: [ 10822, 11814) |***************************************************+
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0 warnings, 1 error
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|
|
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Info: Program finished normally.
|