micheleandClaude Sonnet 5
d716eb04dd
First real RTL piece of the SPI interface (docs §8.1 protocol draft): the physical layer only -- Mode 0 (CPOL=0, CPHA=0), MSB-first, byte-level shift register with a 3-stage CDC synchronizer for SCLK/MOSI/CS_N (the SPI master clock is asynchronous to the FPGA system clock). Exposes rx_byte/rx_valid, tx_byte/tx_byte_req, and cs_active/cs_start/cs_end to the (not yet written) protocol engine. Documented an important consumer contract on tx_byte_req: it is a prefetch hint (fires once extra after the last byte of every transaction, since the slave cannot know in advance whether the master will keep clocking), not a "byte consumed" event -- a consumer must advance any stateful pointer (e.g. a RAM read address) on rx_valid instead, which fires exactly once per real byte transferred. sim/spi_slave_tb.v: bit-banged SPI master BFM (4 tests: single byte, multi-byte in one CS period, back-to-back transactions, slower SCLK). Two testbench-only bugs found and fixed during bring-up (RTL itself needed no functional change beyond the tx_byte_req contract comment): the BFM was advancing its tx queue on tx_byte_req instead of rx_valid (see contract above), and inter-test reset pulses raced against posedge clk (blocking `rst=1` landing on the same simulation time as a clock edge) -- fixed by asserting/deasserting reset on negedge clk instead. Verified two ways: Icarus Verilog (4/4 tests pass) and the real ECP5 toolchain used for prior benchmarks (Yosys 0.68 synth: 0 problems, 41 FF / 55 LUT4, no latches; nextpnr-ecp5 --45k --package CABGA381 --speed 8 --freq 80: PASS, Fmax 403.23 MHz; ecppack: bitstream generated with no errors). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
1007 lines
31 KiB
Plaintext
Executable File
1007 lines
31 KiB
Plaintext
Executable File
#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
|
|
:ivl_version "13.0 (stable)" "(v13_0)";
|
|
:ivl_delay_selection "TYPICAL";
|
|
:vpi_time_precision - 12;
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
|
|
:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
|
|
S_0x104e57530 .scope package, "$unit" "$unit" 2 1;
|
|
.timescale 0 0;
|
|
S_0x104e576b0 .scope module, "tb" "tb" 3 15;
|
|
.timescale -9 -12;
|
|
P_0x88ec50e80 .param/real "CLK_PERIOD" 1 3 17, Cr<m6400000000000000gfc5>; value=12.5000
|
|
v0x88f0899a0_0 .var "clk", 0 0;
|
|
v0x88f089a40_0 .net "cs_active", 0 0, L_0x104e5fa50; 1 drivers
|
|
v0x88f089ae0_0 .net "cs_end", 0 0, v0x88f0885a0_0; 1 drivers
|
|
v0x88f089b80_0 .var/i "cs_end_count", 31 0;
|
|
v0x88f089c20_0 .var "cs_n", 0 0;
|
|
v0x88f089cc0_0 .net "cs_start", 0 0, v0x88f088a00_0; 1 drivers
|
|
v0x88f089d60_0 .var/i "cs_start_count", 31 0;
|
|
v0x88f089e00_0 .var/i "errors", 31 0;
|
|
v0x88f089ea0_0 .var/i "errors_before", 31 0;
|
|
v0x88f089f40_0 .net "miso", 0 0, v0x88f088aa0_0; 1 drivers
|
|
v0x88f089fe0 .array "miso_capture", 7 0, 7 0;
|
|
v0x88f08a080_0 .var "mosi", 0 0;
|
|
v0x88f08a120_0 .var "rst", 0 0;
|
|
v0x88f08a1c0_0 .net "rx_byte", 7 0, v0x88f088dc0_0; 1 drivers
|
|
v0x88f08a260 .array "rx_log", 7 0, 7 0;
|
|
v0x88f08a300_0 .var/i "rx_log_len", 31 0;
|
|
v0x88f08a3a0_0 .var "rx_tmp", 7 0;
|
|
v0x88f08a440_0 .net "rx_valid", 0 0, v0x88f088f00_0; 1 drivers
|
|
v0x88f08a4e0_0 .var "sclk", 0 0;
|
|
v0x88f08a580_0 .var "tx_byte", 7 0;
|
|
v0x88f08a620_0 .net "tx_byte_req", 0 0, v0x88f089400_0; 1 drivers
|
|
v0x88f08a6c0 .array "tx_queue", 7 0, 7 0;
|
|
v0x88f08a760_0 .var/i "tx_queue_idx", 31 0;
|
|
v0x88f08a800_0 .var/i "tx_queue_len", 31 0;
|
|
E_0x88ec46000 .event negedge, v0x88f088460_0;
|
|
v0x88f08a6c0_0 .array/port v0x88f08a6c0, 0;
|
|
v0x88f08a6c0_1 .array/port v0x88f08a6c0, 1;
|
|
E_0x88ec46040/0 .event anyedge, v0x88f08a760_0, v0x88f08a800_0, v0x88f08a6c0_0, v0x88f08a6c0_1;
|
|
v0x88f08a6c0_2 .array/port v0x88f08a6c0, 2;
|
|
v0x88f08a6c0_3 .array/port v0x88f08a6c0, 3;
|
|
v0x88f08a6c0_4 .array/port v0x88f08a6c0, 4;
|
|
v0x88f08a6c0_5 .array/port v0x88f08a6c0, 5;
|
|
E_0x88ec46040/1 .event anyedge, v0x88f08a6c0_2, v0x88f08a6c0_3, v0x88f08a6c0_4, v0x88f08a6c0_5;
|
|
v0x88f08a6c0_6 .array/port v0x88f08a6c0, 6;
|
|
v0x88f08a6c0_7 .array/port v0x88f08a6c0, 7;
|
|
E_0x88ec46040/2 .event anyedge, v0x88f08a6c0_6, v0x88f08a6c0_7;
|
|
E_0x88ec46040 .event/or E_0x88ec46040/0, E_0x88ec46040/1, E_0x88ec46040/2;
|
|
S_0x104e4e9b0 .scope task, "clk_wait" "clk_wait" 3 141, 3 141 0, S_0x104e576b0;
|
|
.timescale -9 -12;
|
|
v0x88f088000_0 .var/i "k", 31 0;
|
|
v0x88f0880a0_0 .var/i "n", 31 0;
|
|
E_0x88ec46080 .event posedge, v0x88f088460_0;
|
|
TD_tb.clk_wait ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f088000_0, 0, 32;
|
|
T_0.0 ; Top of for-loop
|
|
%load/vec4 v0x88f088000_0;
|
|
%load/vec4 v0x88f0880a0_0;
|
|
%cmp/s;
|
|
%jmp/0xz T_0.1, 5;
|
|
%wait E_0x88ec46080;
|
|
T_0.2 ; for-loop step statement
|
|
%load/vec4 v0x88f088000_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f088000_0, 0, 32;
|
|
%jmp T_0.0;
|
|
T_0.1 ; for-loop exit label
|
|
%end;
|
|
S_0x104e4eb30 .scope module, "dut" "spi_slave" 3 40, 4 21 0, S_0x104e576b0;
|
|
.timescale -9 -12;
|
|
.port_info 0 /INPUT 1 "clk";
|
|
.port_info 1 /INPUT 1 "rst";
|
|
.port_info 2 /INPUT 1 "sclk";
|
|
.port_info 3 /INPUT 1 "mosi";
|
|
.port_info 4 /OUTPUT 1 "miso";
|
|
.port_info 5 /INPUT 1 "cs_n";
|
|
.port_info 6 /OUTPUT 8 "rx_byte";
|
|
.port_info 7 /OUTPUT 1 "rx_valid";
|
|
.port_info 8 /INPUT 8 "tx_byte";
|
|
.port_info 9 /OUTPUT 1 "tx_byte_req";
|
|
.port_info 10 /OUTPUT 1 "cs_active";
|
|
.port_info 11 /OUTPUT 1 "cs_start";
|
|
.port_info 12 /OUTPUT 1 "cs_end";
|
|
L_0x104e64420 .functor NOT 1, v0x88f0890e0_0, C4<0>, C4<0>, C4<0>;
|
|
L_0x104e63a20 .functor AND 1, L_0x88f068000, L_0x104e64420, C4<1>, C4<1>;
|
|
L_0x104e4ecb0 .functor NOT 1, L_0x88f068000, C4<0>, C4<0>, C4<0>;
|
|
L_0x104e5ee20 .functor AND 1, L_0x104e4ecb0, v0x88f0890e0_0, C4<1>, C4<1>;
|
|
L_0x104e51730 .functor NOT 1, L_0x88f068140, C4<0>, C4<0>, C4<0>;
|
|
L_0x104e661a0 .functor AND 1, L_0x104e51730, v0x88f088780_0, C4<1>, C4<1>;
|
|
L_0x104e65920 .functor NOT 1, v0x88f088780_0, C4<0>, C4<0>, C4<0>;
|
|
L_0x104e5f9e0 .functor AND 1, L_0x88f068140, L_0x104e65920, C4<1>, C4<1>;
|
|
L_0x104e5fa50 .functor NOT 1, L_0x88f068140, C4<0>, C4<0>, C4<0>;
|
|
v0x88f088140_0 .net *"_ivl_10", 0 0, L_0x104e4ecb0; 1 drivers
|
|
v0x88f0881e0_0 .net *"_ivl_14", 0 0, L_0x104e51730; 1 drivers
|
|
v0x88f088280_0 .net *"_ivl_18", 0 0, L_0x104e65920; 1 drivers
|
|
v0x88f088320_0 .net *"_ivl_6", 0 0, L_0x104e64420; 1 drivers
|
|
v0x88f0883c0_0 .var "bit_count", 2 0;
|
|
v0x88f088460_0 .net "clk", 0 0, v0x88f0899a0_0; 1 drivers
|
|
v0x88f088500_0 .net "cs_active", 0 0, L_0x104e5fa50; alias, 1 drivers
|
|
v0x88f0885a0_0 .var "cs_end", 0 0;
|
|
v0x88f088640_0 .net "cs_fell", 0 0, L_0x104e661a0; 1 drivers
|
|
v0x88f0886e0_0 .net "cs_n", 0 0, v0x88f089c20_0; 1 drivers
|
|
v0x88f088780_0 .var "cs_n_prev", 0 0;
|
|
v0x88f088820_0 .net "cs_n_s", 0 0, L_0x88f068140; 1 drivers
|
|
v0x88f0888c0_0 .var "cs_n_sync", 2 0;
|
|
v0x88f088960_0 .net "cs_rose", 0 0, L_0x104e5f9e0; 1 drivers
|
|
v0x88f088a00_0 .var "cs_start", 0 0;
|
|
v0x88f088aa0_0 .var "miso", 0 0;
|
|
v0x88f088b40_0 .net "mosi", 0 0, v0x88f08a080_0; 1 drivers
|
|
v0x88f088be0_0 .net "mosi_s", 0 0, L_0x88f0680a0; 1 drivers
|
|
v0x88f088c80_0 .var "mosi_sync", 2 0;
|
|
v0x88f088d20_0 .net "rst", 0 0, v0x88f08a120_0; 1 drivers
|
|
v0x88f088dc0_0 .var "rx_byte", 7 0;
|
|
v0x88f088e60_0 .var "rx_shift", 7 0;
|
|
v0x88f088f00_0 .var "rx_valid", 0 0;
|
|
v0x88f088fa0_0 .net "sclk", 0 0, v0x88f08a4e0_0; 1 drivers
|
|
v0x88f089040_0 .net "sclk_fall", 0 0, L_0x104e5ee20; 1 drivers
|
|
v0x88f0890e0_0 .var "sclk_prev", 0 0;
|
|
v0x88f089180_0 .net "sclk_rise", 0 0, L_0x104e63a20; 1 drivers
|
|
v0x88f089220_0 .net "sclk_s", 0 0, L_0x88f068000; 1 drivers
|
|
v0x88f0892c0_0 .var "sclk_sync", 2 0;
|
|
v0x88f089360_0 .net "tx_byte", 7 0, v0x88f08a580_0; 1 drivers
|
|
v0x88f089400_0 .var "tx_byte_req", 0 0;
|
|
v0x88f0894a0_0 .var "tx_shift", 7 0;
|
|
L_0x88f068000 .part v0x88f0892c0_0, 2, 1;
|
|
L_0x88f0680a0 .part v0x88f088c80_0, 2, 1;
|
|
L_0x88f068140 .part v0x88f0888c0_0, 2, 1;
|
|
S_0x104e641a0 .scope task, "spi_begin" "spi_begin" 3 150, 3 150 0, S_0x104e576b0;
|
|
.timescale -9 -12;
|
|
v0x88f089540_0 .var/i "half_bit_cycles", 31 0;
|
|
TD_tb.spi_begin ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f089c20_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a4e0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a080_0, 0, 1;
|
|
%load/vec4 v0x88f089540_0;
|
|
%muli 2, 0, 32;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f089c20_0, 0, 1;
|
|
%load/vec4 v0x88f089540_0;
|
|
%muli 2, 0, 32;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%end;
|
|
S_0x104e63720 .scope task, "spi_end" "spi_end" 3 162, 3 162 0, S_0x104e576b0;
|
|
.timescale -9 -12;
|
|
v0x88f0895e0_0 .var/i "half_bit_cycles", 31 0;
|
|
TD_tb.spi_end ;
|
|
%load/vec4 v0x88f0895e0_0;
|
|
%muli 2, 0, 32;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f089c20_0, 0, 1;
|
|
%load/vec4 v0x88f0895e0_0;
|
|
%muli 2, 0, 32;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%end;
|
|
S_0x104e638a0 .scope task, "spi_xfer_byte" "spi_xfer_byte" 3 171, 3 171 0, S_0x104e576b0;
|
|
.timescale -9 -12;
|
|
v0x88f089680_0 .var/i "half_bit_cycles", 31 0;
|
|
v0x88f089720_0 .var/i "i", 31 0;
|
|
v0x88f0897c0_0 .var "rx", 7 0;
|
|
v0x88f089860_0 .var "rx_acc", 7 0;
|
|
v0x88f089900_0 .var "tx", 7 0;
|
|
TD_tb.spi_xfer_byte ;
|
|
%pushi/vec4 0, 0, 8;
|
|
%store/vec4 v0x88f089860_0, 0, 8;
|
|
%pushi/vec4 7, 0, 32;
|
|
%store/vec4 v0x88f089720_0, 0, 32;
|
|
T_3.3 ; Top of for-loop
|
|
%load/vec4 v0x88f089720_0;
|
|
%cmpi/s 0, 0, 32;
|
|
%flag_inv 5; GE is !LT
|
|
%jmp/0xz T_3.4, 5;
|
|
%load/vec4 v0x88f089900_0;
|
|
%load/vec4 v0x88f089720_0;
|
|
%part/s 1;
|
|
%store/vec4 v0x88f08a080_0, 0, 1;
|
|
%load/vec4 v0x88f089680_0;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f08a4e0_0, 0, 1;
|
|
%load/vec4 v0x88f089f40_0;
|
|
%ix/getv/s 4, v0x88f089720_0;
|
|
%store/vec4 v0x88f089860_0, 4, 1;
|
|
%load/vec4 v0x88f089680_0;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a4e0_0, 0, 1;
|
|
%load/vec4 v0x88f089680_0;
|
|
%store/vec4 v0x88f0880a0_0, 0, 32;
|
|
%fork TD_tb.clk_wait, S_0x104e4e9b0;
|
|
%join;
|
|
T_3.5 ; for-loop step statement
|
|
%load/vec4 v0x88f089720_0;
|
|
%subi 1, 0, 32;
|
|
%store/vec4 v0x88f089720_0, 0, 32;
|
|
%jmp T_3.3;
|
|
T_3.4 ; for-loop exit label
|
|
%load/vec4 v0x88f089860_0;
|
|
%store/vec4 v0x88f0897c0_0, 0, 8;
|
|
%end;
|
|
.scope S_0x104e4eb30;
|
|
T_4 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f088d20_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.0, 8;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x88f0892c0_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x88f088c80_0, 0;
|
|
%pushi/vec4 7, 0, 3;
|
|
%assign/vec4 v0x88f0888c0_0, 0;
|
|
%jmp T_4.1;
|
|
T_4.0 ;
|
|
%load/vec4 v0x88f0892c0_0;
|
|
%parti/s 2, 0, 2;
|
|
%load/vec4 v0x88f088fa0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x88f0892c0_0, 0;
|
|
%load/vec4 v0x88f088c80_0;
|
|
%parti/s 2, 0, 2;
|
|
%load/vec4 v0x88f088b40_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x88f088c80_0, 0;
|
|
%load/vec4 v0x88f0888c0_0;
|
|
%parti/s 2, 0, 2;
|
|
%load/vec4 v0x88f0886e0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x88f0888c0_0, 0;
|
|
T_4.1 ;
|
|
%jmp T_4;
|
|
.thread T_4;
|
|
.scope S_0x104e4eb30;
|
|
T_5 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f088d20_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_5.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f0890e0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f088780_0, 0;
|
|
%jmp T_5.1;
|
|
T_5.0 ;
|
|
%load/vec4 v0x88f089220_0;
|
|
%assign/vec4 v0x88f0890e0_0, 0;
|
|
%load/vec4 v0x88f088820_0;
|
|
%assign/vec4 v0x88f088780_0, 0;
|
|
T_5.1 ;
|
|
%jmp T_5;
|
|
.thread T_5;
|
|
.scope S_0x104e4eb30;
|
|
T_6 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f088d20_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.0, 8;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x88f0883c0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x88f088e60_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x88f0894a0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x88f088dc0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f088f00_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f089400_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f088aa0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f088a00_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f0885a0_0, 0;
|
|
%jmp T_6.1;
|
|
T_6.0 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f088f00_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f089400_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f088a00_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f0885a0_0, 0;
|
|
%load/vec4 v0x88f088640_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.2, 8;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x88f0883c0_0, 0;
|
|
%load/vec4 v0x88f089360_0;
|
|
%assign/vec4 v0x88f0894a0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f089400_0, 0;
|
|
%load/vec4 v0x88f089360_0;
|
|
%parti/s 1, 7, 4;
|
|
%assign/vec4 v0x88f088aa0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f088a00_0, 0;
|
|
%jmp T_6.3;
|
|
T_6.2 ;
|
|
%load/vec4 v0x88f088960_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.4, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f0885a0_0, 0;
|
|
%jmp T_6.5;
|
|
T_6.4 ;
|
|
%load/vec4 v0x88f088500_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.6, 8;
|
|
%load/vec4 v0x88f089180_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.8, 8;
|
|
%load/vec4 v0x88f088e60_0;
|
|
%parti/s 7, 0, 2;
|
|
%load/vec4 v0x88f088be0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x88f088e60_0, 0;
|
|
%load/vec4 v0x88f0883c0_0;
|
|
%cmpi/e 7, 0, 3;
|
|
%jmp/0xz T_6.10, 4;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x88f0883c0_0, 0;
|
|
%load/vec4 v0x88f088e60_0;
|
|
%parti/s 7, 0, 2;
|
|
%load/vec4 v0x88f088be0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x88f088dc0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f088f00_0, 0;
|
|
%jmp T_6.11;
|
|
T_6.10 ;
|
|
%load/vec4 v0x88f0883c0_0;
|
|
%addi 1, 0, 3;
|
|
%assign/vec4 v0x88f0883c0_0, 0;
|
|
T_6.11 ;
|
|
%jmp T_6.9;
|
|
T_6.8 ;
|
|
%load/vec4 v0x88f089040_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.12, 8;
|
|
%load/vec4 v0x88f0883c0_0;
|
|
%cmpi/e 0, 0, 3;
|
|
%jmp/0xz T_6.14, 4;
|
|
%load/vec4 v0x88f089360_0;
|
|
%assign/vec4 v0x88f0894a0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x88f089400_0, 0;
|
|
%load/vec4 v0x88f089360_0;
|
|
%parti/s 1, 7, 4;
|
|
%assign/vec4 v0x88f088aa0_0, 0;
|
|
%jmp T_6.15;
|
|
T_6.14 ;
|
|
%load/vec4 v0x88f0894a0_0;
|
|
%parti/s 7, 0, 2;
|
|
%concati/vec4 0, 0, 1;
|
|
%assign/vec4 v0x88f0894a0_0, 0;
|
|
%load/vec4 v0x88f0894a0_0;
|
|
%parti/s 1, 6, 4;
|
|
%assign/vec4 v0x88f088aa0_0, 0;
|
|
T_6.15 ;
|
|
T_6.12 ;
|
|
T_6.9 ;
|
|
T_6.6 ;
|
|
T_6.5 ;
|
|
T_6.3 ;
|
|
T_6.1 ;
|
|
%jmp T_6;
|
|
.thread T_6;
|
|
.scope S_0x104e576b0;
|
|
T_7 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f0899a0_0, 0, 1;
|
|
T_7.0 ;
|
|
%delay 6250, 0;
|
|
%load/vec4 v0x88f0899a0_0;
|
|
%inv;
|
|
%store/vec4 v0x88f0899a0_0, 0, 1;
|
|
%jmp T_7.0;
|
|
T_7.1 ;
|
|
%end;
|
|
.thread T_7;
|
|
.scope S_0x104e576b0;
|
|
T_8 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f08a120_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_8.0, 8;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x88f08a760_0, 0;
|
|
%jmp T_8.1;
|
|
T_8.0 ;
|
|
%load/vec4 v0x88f08a440_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_8.2, 8;
|
|
%load/vec4 v0x88f08a760_0;
|
|
%load/vec4 v0x88f08a800_0;
|
|
%cmp/s;
|
|
%jmp/0xz T_8.4, 5;
|
|
%load/vec4 v0x88f08a760_0;
|
|
%addi 1, 0, 32;
|
|
%assign/vec4 v0x88f08a760_0, 0;
|
|
T_8.4 ;
|
|
T_8.2 ;
|
|
T_8.1 ;
|
|
%jmp T_8;
|
|
.thread T_8;
|
|
.scope S_0x104e576b0;
|
|
T_9 ;
|
|
%wait E_0x88ec46040;
|
|
%load/vec4 v0x88f08a760_0;
|
|
%load/vec4 v0x88f08a800_0;
|
|
%cmp/s;
|
|
%flag_mov 8, 5;
|
|
%jmp/0 T_9.0, 8;
|
|
%ix/getv/s 4, v0x88f08a760_0;
|
|
%load/vec4a v0x88f08a6c0, 4;
|
|
%jmp/1 T_9.1, 8;
|
|
T_9.0 ; End of true expr.
|
|
%pushi/vec4 0, 0, 8;
|
|
%jmp/0 T_9.1, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_9.1;
|
|
%store/vec4 v0x88f08a580_0, 0, 8;
|
|
%jmp T_9;
|
|
.thread T_9, $push;
|
|
.scope S_0x104e576b0;
|
|
T_10 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f08a120_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_10.0, 8;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x88f08a300_0, 0;
|
|
%jmp T_10.1;
|
|
T_10.0 ;
|
|
%load/vec4 v0x88f08a440_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_10.2, 8;
|
|
%load/vec4 v0x88f08a1c0_0;
|
|
%ix/getv/s 3, v0x88f08a300_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x88f08a260, 0, 4;
|
|
%load/vec4 v0x88f08a300_0;
|
|
%addi 1, 0, 32;
|
|
%assign/vec4 v0x88f08a300_0, 0;
|
|
T_10.2 ;
|
|
T_10.1 ;
|
|
%jmp T_10;
|
|
.thread T_10;
|
|
.scope S_0x104e576b0;
|
|
T_11 ;
|
|
%wait E_0x88ec46080;
|
|
%load/vec4 v0x88f08a120_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_11.0, 8;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x88f089d60_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x88f089b80_0, 0;
|
|
%jmp T_11.1;
|
|
T_11.0 ;
|
|
%load/vec4 v0x88f089cc0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_11.2, 8;
|
|
%load/vec4 v0x88f089d60_0;
|
|
%addi 1, 0, 32;
|
|
%assign/vec4 v0x88f089d60_0, 0;
|
|
T_11.2 ;
|
|
%load/vec4 v0x88f089ae0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_11.4, 8;
|
|
%load/vec4 v0x88f089b80_0;
|
|
%addi 1, 0, 32;
|
|
%assign/vec4 v0x88f089b80_0, 0;
|
|
T_11.4 ;
|
|
T_11.1 ;
|
|
%jmp T_11;
|
|
.thread T_11;
|
|
.scope S_0x104e576b0;
|
|
T_12 ;
|
|
%vpi_call/w 3 202 "$dumpfile", "sim/spi_slave.vcd" {0 0 0};
|
|
%vpi_call/w 3 203 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x104e576b0 {0 0 0};
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f089c20_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a4e0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a080_0, 0, 1;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f08a300_0, 0, 32;
|
|
%pushi/vec4 5, 0, 32;
|
|
T_12.0 %dup/vec4;
|
|
%cmpi/s 0, 0, 32;
|
|
%jmp/1xz T_12.1, 5;
|
|
%jmp/1 T_12.1, 4;
|
|
%subi 1, 0, 32;
|
|
%wait E_0x88ec46080;
|
|
%jmp T_12.0;
|
|
T_12.1 ;
|
|
%pop/vec4 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%pushi/vec4 5, 0, 32;
|
|
T_12.2 %dup/vec4;
|
|
%cmpi/s 0, 0, 32;
|
|
%jmp/1xz T_12.3, 5;
|
|
%jmp/1 T_12.3, 4;
|
|
%subi 1, 0, 32;
|
|
%wait E_0x88ec46080;
|
|
%jmp T_12.2;
|
|
T_12.3 ;
|
|
%pop/vec4 1;
|
|
%vpi_call/w 3 217 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 218 "$display", "========================================" {0 0 0};
|
|
%vpi_call/w 3 219 "$display", "SPI_SLAVE PHYSICAL LAYER TEST" {0 0 0};
|
|
%vpi_call/w 3 220 "$display", "========================================" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%store/vec4 v0x88f089ea0_0, 0, 32;
|
|
%pushi/vec4 60, 0, 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089540_0, 0, 32;
|
|
%fork TD_tb.spi_begin, S_0x104e641a0;
|
|
%join;
|
|
%pushi/vec4 165, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f0895e0_0, 0, 32;
|
|
%fork TD_tb.spi_end, S_0x104e63720;
|
|
%join;
|
|
%wait E_0x88ec46080;
|
|
%wait E_0x88ec46080;
|
|
%vpi_call/w 3 238 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 239 "$display", "TEST 1: single byte" {0 0 0};
|
|
%vpi_call/w 3 240 "$display", " MOSI sent = 0xA5, slave rx_byte = 0x%02x (expect 0xA5)", &A<v0x88f08a260, 0> {0 0 0};
|
|
%vpi_call/w 3 241 "$display", " MISO sent = 0x3C, master received = 0x%02x (expect 0x3C)", v0x88f08a3a0_0 {0 0 0};
|
|
%vpi_call/w 3 242 "$display", " cs_start pulses = %0d (expect 1), cs_end pulses = %0d (expect 1)", v0x88f089d60_0, v0x88f089b80_0 {0 0 0};
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 165, 0, 8;
|
|
%jmp/0xz T_12.4, 6;
|
|
%vpi_call/w 3 245 "$display", " FAIL: rx_byte mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.4 ;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%cmpi/ne 60, 0, 8;
|
|
%jmp/0xz T_12.6, 6;
|
|
%vpi_call/w 3 246 "$display", " FAIL: MISO readback mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.6 ;
|
|
%load/vec4 v0x88f089d60_0;
|
|
%cmpi/ne 1, 0, 32;
|
|
%jmp/0xz T_12.8, 6;
|
|
%vpi_call/w 3 247 "$display", " FAIL: cs_start count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.8 ;
|
|
%load/vec4 v0x88f089b80_0;
|
|
%cmpi/ne 1, 0, 32;
|
|
%jmp/0xz T_12.10, 6;
|
|
%vpi_call/w 3 248 "$display", " FAIL: cs_end count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.10 ;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%load/vec4 v0x88f089ea0_0;
|
|
%cmp/e;
|
|
%jmp/0xz T_12.12, 4;
|
|
%vpi_call/w 3 249 "$display", " PASS" {0 0 0};
|
|
T_12.12 ;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46080;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f08a300_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089d60_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089b80_0, 0, 32;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%store/vec4 v0x88f089ea0_0, 0, 32;
|
|
%pushi/vec4 222, 0, 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 173, 0, 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 190, 0, 8;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 239, 0, 8;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 4, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089540_0, 0, 32;
|
|
%fork TD_tb.spi_begin, S_0x104e641a0;
|
|
%join;
|
|
%pushi/vec4 17, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f089fe0, 4, 0;
|
|
%pushi/vec4 34, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f089fe0, 4, 0;
|
|
%pushi/vec4 51, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f089fe0, 4, 0;
|
|
%pushi/vec4 68, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f089fe0, 4, 0;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f0895e0_0, 0, 32;
|
|
%fork TD_tb.spi_end, S_0x104e63720;
|
|
%join;
|
|
%wait E_0x88ec46080;
|
|
%wait E_0x88ec46080;
|
|
%vpi_call/w 3 276 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 277 "$display", "TEST 2: multi-byte, one CS period" {0 0 0};
|
|
%vpi_call/w 3 278 "$display", " rx_log = %02x %02x %02x %02x (expect 11 22 33 44)", &A<v0x88f08a260, 0>, &A<v0x88f08a260, 1>, &A<v0x88f08a260, 2>, &A<v0x88f08a260, 3> {0 0 0};
|
|
%vpi_call/w 3 280 "$display", " miso = %02x %02x %02x %02x (expect de ad be ef)", &A<v0x88f089fe0, 0>, &A<v0x88f089fe0, 1>, &A<v0x88f089fe0, 2>, &A<v0x88f089fe0, 3> {0 0 0};
|
|
%vpi_call/w 3 282 "$display", " cs_start pulses = %0d (expect 1), cs_end pulses = %0d (expect 1)", v0x88f089d60_0, v0x88f089b80_0 {0 0 0};
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 17, 0, 8;
|
|
%jmp/1 T_12.18, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 34, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.18;
|
|
%jmp/1 T_12.17, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 51, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.17;
|
|
%jmp/1 T_12.16, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 68, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.16;
|
|
%jmp/0xz T_12.14, 6;
|
|
%vpi_call/w 3 287 "$display", " FAIL: rx sequence mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.14 ;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f089fe0, 4;
|
|
%cmpi/ne 222, 0, 8;
|
|
%jmp/1 T_12.23, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f089fe0, 4;
|
|
%cmpi/ne 173, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.23;
|
|
%jmp/1 T_12.22, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f089fe0, 4;
|
|
%cmpi/ne 190, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.22;
|
|
%jmp/1 T_12.21, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f089fe0, 4;
|
|
%cmpi/ne 239, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.21;
|
|
%jmp/0xz T_12.19, 6;
|
|
%vpi_call/w 3 292 "$display", " FAIL: MISO sequence mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.19 ;
|
|
%load/vec4 v0x88f089d60_0;
|
|
%cmpi/ne 1, 0, 32;
|
|
%jmp/0xz T_12.24, 6;
|
|
%vpi_call/w 3 295 "$display", " FAIL: cs_start count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.24 ;
|
|
%load/vec4 v0x88f089b80_0;
|
|
%cmpi/ne 1, 0, 32;
|
|
%jmp/0xz T_12.26, 6;
|
|
%vpi_call/w 3 296 "$display", " FAIL: cs_end count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.26 ;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%load/vec4 v0x88f089ea0_0;
|
|
%cmp/e;
|
|
%jmp/0xz T_12.28, 4;
|
|
%vpi_call/w 3 297 "$display", " PASS" {0 0 0};
|
|
T_12.28 ;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46080;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f08a300_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089d60_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089b80_0, 0, 32;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%store/vec4 v0x88f089ea0_0, 0, 32;
|
|
%pushi/vec4 1, 0, 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089540_0, 0, 32;
|
|
%fork TD_tb.spi_begin, S_0x104e641a0;
|
|
%join;
|
|
%pushi/vec4 126, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f0895e0_0, 0, 32;
|
|
%fork TD_tb.spi_end, S_0x104e63720;
|
|
%join;
|
|
%pushi/vec4 10, 0, 32;
|
|
T_12.30 %dup/vec4;
|
|
%cmpi/s 0, 0, 32;
|
|
%jmp/1xz T_12.31, 5;
|
|
%jmp/1 T_12.31, 4;
|
|
%subi 1, 0, 32;
|
|
%wait E_0x88ec46080;
|
|
%jmp T_12.30;
|
|
T_12.31 ;
|
|
%pop/vec4 1;
|
|
%pushi/vec4 2, 0, 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089540_0, 0, 32;
|
|
%fork TD_tb.spi_begin, S_0x104e641a0;
|
|
%join;
|
|
%pushi/vec4 129, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%pushi/vec4 8, 0, 32;
|
|
%store/vec4 v0x88f0895e0_0, 0, 32;
|
|
%fork TD_tb.spi_end, S_0x104e63720;
|
|
%join;
|
|
%wait E_0x88ec46080;
|
|
%wait E_0x88ec46080;
|
|
%vpi_call/w 3 325 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 326 "$display", "TEST 3: back-to-back transactions" {0 0 0};
|
|
%vpi_call/w 3 327 "$display", " rx_log = %02x %02x (expect 7e 81)", &A<v0x88f08a260, 0>, &A<v0x88f08a260, 1> {0 0 0};
|
|
%vpi_call/w 3 328 "$display", " cs_start pulses = %0d (expect 2), cs_end pulses = %0d (expect 2)", v0x88f089d60_0, v0x88f089b80_0 {0 0 0};
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 126, 0, 8;
|
|
%jmp/1 T_12.34, 6;
|
|
%flag_mov 8, 6;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 129, 0, 8;
|
|
%flag_or 6, 8;
|
|
T_12.34;
|
|
%jmp/0xz T_12.32, 6;
|
|
%vpi_call/w 3 332 "$display", " FAIL: rx sequence mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.32 ;
|
|
%load/vec4 v0x88f089d60_0;
|
|
%cmpi/ne 2, 0, 32;
|
|
%jmp/0xz T_12.35, 6;
|
|
%vpi_call/w 3 335 "$display", " FAIL: cs_start count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.35 ;
|
|
%load/vec4 v0x88f089b80_0;
|
|
%cmpi/ne 2, 0, 32;
|
|
%jmp/0xz T_12.37, 6;
|
|
%vpi_call/w 3 336 "$display", " FAIL: cs_end count" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.37 ;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%load/vec4 v0x88f089ea0_0;
|
|
%cmp/e;
|
|
%jmp/0xz T_12.39, 4;
|
|
%vpi_call/w 3 337 "$display", " PASS" {0 0 0};
|
|
T_12.39 ;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46000;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x88f08a120_0, 0, 1;
|
|
%wait E_0x88ec46080;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f08a300_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089d60_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x88f089b80_0, 0, 32;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%store/vec4 v0x88f089ea0_0, 0, 32;
|
|
%pushi/vec4 90, 0, 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x88f08a6c0, 4, 0;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x88f08a800_0, 0, 32;
|
|
%pushi/vec4 20, 0, 32;
|
|
%store/vec4 v0x88f089540_0, 0, 32;
|
|
%fork TD_tb.spi_begin, S_0x104e641a0;
|
|
%join;
|
|
%pushi/vec4 150, 0, 8;
|
|
%store/vec4 v0x88f089900_0, 0, 8;
|
|
%pushi/vec4 20, 0, 32;
|
|
%store/vec4 v0x88f089680_0, 0, 32;
|
|
%fork TD_tb.spi_xfer_byte, S_0x104e638a0;
|
|
%join;
|
|
%load/vec4 v0x88f0897c0_0;
|
|
%store/vec4 v0x88f08a3a0_0, 0, 8;
|
|
%pushi/vec4 20, 0, 32;
|
|
%store/vec4 v0x88f0895e0_0, 0, 32;
|
|
%fork TD_tb.spi_end, S_0x104e63720;
|
|
%join;
|
|
%wait E_0x88ec46080;
|
|
%wait E_0x88ec46080;
|
|
%vpi_call/w 3 358 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 359 "$display", "TEST 4: slower SCLK (200ns half-period)" {0 0 0};
|
|
%vpi_call/w 3 360 "$display", " rx_byte = 0x%02x (expect 0x96), MISO = 0x%02x (expect 0x5a)", &A<v0x88f08a260, 0>, v0x88f08a3a0_0 {0 0 0};
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x88f08a260, 4;
|
|
%cmpi/ne 150, 0, 8;
|
|
%jmp/0xz T_12.41, 6;
|
|
%vpi_call/w 3 363 "$display", " FAIL: rx_byte mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.41 ;
|
|
%load/vec4 v0x88f08a3a0_0;
|
|
%cmpi/ne 90, 0, 8;
|
|
%jmp/0xz T_12.43, 6;
|
|
%vpi_call/w 3 364 "$display", " FAIL: MISO readback mismatch" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x88f089e00_0, 0, 32;
|
|
T_12.43 ;
|
|
%load/vec4 v0x88f089e00_0;
|
|
%load/vec4 v0x88f089ea0_0;
|
|
%cmp/e;
|
|
%jmp/0xz T_12.45, 4;
|
|
%vpi_call/w 3 365 "$display", " PASS" {0 0 0};
|
|
T_12.45 ;
|
|
%vpi_call/w 3 367 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 368 "$display", "========================================" {0 0 0};
|
|
%load/vec4 v0x88f089e00_0;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_12.47, 4;
|
|
%vpi_call/w 3 370 "$display", "SPI_SLAVE TEST PASSED" {0 0 0};
|
|
%jmp T_12.48;
|
|
T_12.47 ;
|
|
%vpi_call/w 3 372 "$display", "SPI_SLAVE TEST FAILED: %0d errors", v0x88f089e00_0 {0 0 0};
|
|
T_12.48 ;
|
|
%vpi_call/w 3 373 "$display", "========================================" {0 0 0};
|
|
%vpi_call/w 3 374 "$display", "\000" {0 0 0};
|
|
%vpi_call/w 3 376 "$finish" {0 0 0};
|
|
%end;
|
|
.thread T_12;
|
|
# The file index is used to find the file name in the following table.
|
|
:file_names 5;
|
|
"N/A";
|
|
"<interactive>";
|
|
"-";
|
|
"sim/spi_slave_tb.v";
|
|
"rtl/spi_slave.v";
|