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FPGA-Neural/synth/ecp5/irq_pins/nextpnr.log
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micheleandClaude Sonnet 5 55c827bedf feat: PSRAM page-mode reads + graph engine (Type #2) + real pinout/IRQ pins 
PSRAM page-mode read burst support in psram_controller.v: enables the
ISSI IS66WVE4M16EBLL-70BLI's page mode via its configuration-register
software-access sequence at boot (disabled by default on the real
chip), then keeps CE#/OE# asserted after a read so a same-page
continuation only pays tAPA (20ns) instead of a full tAA (70ns)
random access, with automatic tCEM-safe session closing. Only a WRITE
closes the page -- byte-enable changes do not, since
int8_memory_access.v alternates them on nearly every access and an
early implementation attempt that treated them as a close condition
measured a real regression (53.25->61.25 cycles/edge) before being
corrected (53.25->37.53 cycles/edge, +42% gather bandwidth).
sim/psram_model.v gained independent tAPA/tAA and tCEM enforcement
(with a real Verilog same-timestep event-ordering race found and
fixed via a #0 sync) so the regression proves real timing compliance,
not just data correctness. New sim/psram_page_mode_tb.v; full 26-file
regression suite re-run clean. Real nextpnr-ecp5 Fmax re-measured on
the full spi_neuron_top system: 75.73MHz (P2, up from 55.59MHz) and
65.13MHz (P8) -- still under the 80MHz target but not regressed, with
the critical path confirmed (not assumed) to remain entirely inside
neuron_parallel's accumulate chain, never psram_controller.

Also includes this session's other already-validated work: the graph
engine (Type #2 sparse-graph network: act_buffer, graph_engine,
netasm host assembler), real CABGA381 pinout (.lpf, place&route
verified) and physical IRQ_N/DATA_READY_N pins, and Phase 7 timing
closure logs -- all previously uncommitted, documented in WORKLOG.md.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LH3jPeJ3eFMfF2v8SQhpkk
2026-09-03 17:12:05 +02:00

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Info: Logic utilisation before packing:
Info: Total LUT4s: 3059/43848 6%
Info: logic LUTs: 2385/43848 5%
Info: carry LUTs: 674/43848 1%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 2408/43848 5%
Info: Packing IOs..
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
Info: pin 'psram_dq[15]$tr_io' constrained to Bel 'X90/Y41/PIOD'.
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
Info: pin 'psram_dq[14]$tr_io' constrained to Bel 'X90/Y41/PIOC'.
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
Info: pin 'psram_dq[13]$tr_io' constrained to Bel 'X90/Y41/PIOA'.
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
Info: pin 'psram_dq[12]$tr_io' constrained to Bel 'X90/Y41/PIOB'.
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
Info: pin 'psram_dq[11]$tr_io' constrained to Bel 'X90/Y38/PIOD'.
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
Info: pin 'psram_dq[10]$tr_io' constrained to Bel 'X90/Y38/PIOB'.
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
Info: pin 'psram_dq[9]$tr_io' constrained to Bel 'X90/Y32/PIOD'.
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
Info: pin 'psram_dq[8]$tr_io' constrained to Bel 'X90/Y32/PIOB'.
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
Info: pin 'psram_dq[7]$tr_io' constrained to Bel 'X90/Y32/PIOC'.
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
Info: pin 'psram_dq[6]$tr_io' constrained to Bel 'X90/Y32/PIOA'.
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
Info: pin 'psram_dq[5]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
Info: pin 'psram_dq[4]$tr_io' constrained to Bel 'X90/Y29/PIOA'.
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
Info: pin 'psram_dq[3]$tr_io' constrained to Bel 'X90/Y23/PIOC'.
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
Info: pin 'psram_dq[2]$tr_io' constrained to Bel 'X90/Y11/PIOB'.
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
Info: pin 'psram_dq[1]$tr_io' constrained to Bel 'X90/Y11/PIOA'.
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
Info: pin 'psram_dq[0]$tr_io' constrained to Bel 'X90/Y29/PIOD'.
Info: pin 'sclk$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'rst$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'psram_zz_n$tr_io' constrained to Bel 'X90/Y59/PIOB'.
Info: pin 'psram_we_n$tr_io' constrained to Bel 'X90/Y44/PIOD'.
Info: pin 'psram_ub_n$tr_io' constrained to Bel 'X90/Y59/PIOA'.
Info: pin 'psram_oe_n$tr_io' constrained to Bel 'X90/Y44/PIOC'.
Info: pin 'psram_lb_n$tr_io' constrained to Bel 'X90/Y53/PIOA'.
Info: pin 'psram_ce_n$tr_io' constrained to Bel 'X90/Y44/PIOA'.
Info: pin 'psram_a[22]$tr_io' constrained to Bel 'X90/Y59/PIOD'.
Info: pin 'psram_a[21]$tr_io' constrained to Bel 'X90/Y29/PIOB'.
Info: pin 'psram_a[20]$tr_io' constrained to Bel 'X90/Y26/PIOD'.
Info: pin 'psram_a[19]$tr_io' constrained to Bel 'X90/Y26/PIOC'.
Info: pin 'psram_a[18]$tr_io' constrained to Bel 'X90/Y26/PIOB'.
Info: pin 'psram_a[17]$tr_io' constrained to Bel 'X90/Y26/PIOA'.
Info: pin 'psram_a[16]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: pin 'psram_a[15]$tr_io' constrained to Bel 'X90/Y23/PIOB'.
Info: pin 'psram_a[14]$tr_io' constrained to Bel 'X90/Y23/PIOA'.
Info: pin 'psram_a[13]$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'psram_a[12]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'psram_a[11]$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'psram_a[10]$tr_io' constrained to Bel 'X90/Y20/PIOB'.
Info: pin 'psram_a[9]$tr_io' constrained to Bel 'X90/Y17/PIOD'.
Info: pin 'psram_a[8]$tr_io' constrained to Bel 'X90/Y17/PIOB'.
Info: pin 'psram_a[7]$tr_io' constrained to Bel 'X90/Y17/PIOC'.
Info: pin 'psram_a[6]$tr_io' constrained to Bel 'X90/Y17/PIOA'.
Info: pin 'psram_a[5]$tr_io' constrained to Bel 'X90/Y14/PIOD'.
Info: pin 'psram_a[4]$tr_io' constrained to Bel 'X90/Y14/PIOC'.
Info: pin 'psram_a[3]$tr_io' constrained to Bel 'X90/Y14/PIOB'.
Info: pin 'psram_a[2]$tr_io' constrained to Bel 'X90/Y14/PIOA'.
Info: pin 'psram_a[1]$tr_io' constrained to Bel 'X90/Y11/PIOD'.
Info: pin 'psram_a[0]$tr_io' constrained to Bel 'X90/Y11/PIOC'.
Info: pin 'mosi$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'miso$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'irq_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'data_ready_n$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'cs_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 495 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc7ccff42
Info: Device utilisation:
Info: TRELLIS_IO: 53/ 245 21%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 2/ 108 1%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 2408/ 43848 5%
Info: TRELLIS_COMB: 3217/ 43848 7%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 53 cells based on constraints.
Info: Creating initial analytic placement for 3921 cells, random placement wirelen = 289147.
Info: at initial placer iter 0, wirelen = 3108
Info: at initial placer iter 1, wirelen = 2354
Info: at initial placer iter 2, wirelen = 2209
Info: at initial placer iter 3, wirelen = 2131
Info: Running main analytical placer, max placement attempts per cell = 4039903.
Info: at iteration #1, type ALL: wirelen solved = 2150, spread = 33458, legal = 36654; time = 0.06s
Info: at iteration #2, type ALL: wirelen solved = 4793, spread = 27112, legal = 30522; time = 0.05s
Info: at iteration #3, type ALL: wirelen solved = 6235, spread = 23876, legal = 26922; time = 0.05s
Info: at iteration #4, type ALL: wirelen solved = 8028, spread = 21334, legal = 23718; time = 0.05s
Info: at iteration #5, type ALL: wirelen solved = 9065, spread = 19405, legal = 22698; time = 0.04s
Info: at iteration #6, type ALL: wirelen solved = 9801, spread = 20119, legal = 22560; time = 0.04s
Info: at iteration #7, type ALL: wirelen solved = 11646, spread = 19356, legal = 21907; time = 0.04s
Info: at iteration #8, type ALL: wirelen solved = 12802, spread = 18500, legal = 21381; time = 0.04s
Info: at iteration #9, type ALL: wirelen solved = 12830, spread = 17408, legal = 20985; time = 0.04s
Info: at iteration #10, type ALL: wirelen solved = 13112, spread = 17885, legal = 20665; time = 0.04s
Info: at iteration #11, type ALL: wirelen solved = 13514, spread = 18225, legal = 20489; time = 0.04s
Info: at iteration #12, type ALL: wirelen solved = 14271, spread = 17570, legal = 20810; time = 0.04s
Info: at iteration #13, type ALL: wirelen solved = 14146, spread = 17792, legal = 21114; time = 0.04s
Info: at iteration #14, type ALL: wirelen solved = 14392, spread = 17828, legal = 20353; time = 0.04s
Info: at iteration #15, type ALL: wirelen solved = 14743, spread = 18117, legal = 20872; time = 0.04s
Info: at iteration #16, type ALL: wirelen solved = 15140, spread = 18076, legal = 21425; time = 0.04s
Info: at iteration #17, type ALL: wirelen solved = 15052, spread = 18323, legal = 21509; time = 0.04s
Info: at iteration #18, type ALL: wirelen solved = 15222, spread = 18362, legal = 21239; time = 0.04s
Info: at iteration #19, type ALL: wirelen solved = 15352, spread = 18252, legal = 21084; time = 0.04s
Info: HeAP Placer Time: 1.08s
Info: of which solving equations: 0.67s
Info: of which spreading cells: 0.13s
Info: of which strict legalisation: 0.12s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 555, wirelen = 20353
Info: at iteration #5: temp = 0.000000, timing cost = 815, wirelen = 18346
Info: at iteration #10: temp = 0.000000, timing cost = 765, wirelen = 17721
Info: at iteration #15: temp = 0.000000, timing cost = 825, wirelen = 17405
Info: at iteration #20: temp = 0.000000, timing cost = 817, wirelen = 17284
Info: at iteration #25: temp = 0.000000, timing cost = 814, wirelen = 17245
Info: at iteration #30: temp = 0.000000, timing cost = 811, wirelen = 17223
Info: at iteration #32: temp = 0.000000, timing cost = 813, wirelen = 17220
Info: SA placement time 2.13s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 68.61 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.08 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.64 ns
Info: Slack histogram:
Info: legend: * represents 18 endpoint(s)
Info: + represents [1,18) endpoint(s)
Info: [ -2076, -1375) |*+
Info: [ -1375, -674) |+
Info: [ -674, 27) |*+
Info: [ 27, 728) |+
Info: [ 728, 1429) |+
Info: [ 1429, 2130) |
Info: [ 2130, 2831) |
Info: [ 2831, 3532) |*+
Info: [ 3532, 4233) |**+
Info: [ 4233, 4934) |***********+
Info: [ 4934, 5635) |************+
Info: [ 5635, 6336) |*****************+
Info: [ 6336, 7037) |*********************************+
Info: [ 7037, 7738) |**************************************+
Info: [ 7738, 8439) |********************+
Info: [ 8439, 9140) |*************************+
Info: [ 9140, 9841) |*****************************+
Info: [ 9841, 10542) |************************************************************
Info: [ 10542, 11243) |**************************************+
Info: [ 11243, 11944) |********************+
Info: Checksum: 0xff748940
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 15978 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 375 624 | 375 624 | 15382| 0.17 0.17|
Info: 2000 | 751 1248 | 376 624 | 14828| 0.16 0.33|
Info: 3000 | 910 2089 | 159 841 | 13993| 0.08 0.41|
Info: 4000 | 1116 2883 | 206 794 | 13241| 0.09 0.50|
Info: 5000 | 1309 3690 | 193 807 | 12468| 0.08 0.59|
Info: 6000 | 1527 4472 | 218 782 | 11748| 0.12 0.71|
Info: 7000 | 1756 5243 | 229 771 | 11042| 0.12 0.83|
Info: 8000 | 1950 6017 | 194 774 | 10256| 0.09 0.91|
Info: 9000 | 2237 6667 | 287 650 | 9621| 0.08 1.00|
Info: 10000 | 2538 7323 | 301 656 | 8971| 0.10 1.10|
Info: 11000 | 2912 7901 | 374 578 | 8375| 0.09 1.18|
Info: 12000 | 3271 8539 | 359 638 | 7772| 0.11 1.29|
Info: 13000 | 3667 9143 | 396 604 | 7197| 0.11 1.40|
Info: 14000 | 3942 9865 | 275 722 | 6496| 0.12 1.51|
Info: 15000 | 4197 10579 | 255 714 | 5830| 0.13 1.64|
Info: 16000 | 4334 11306 | 137 727 | 5011| 0.10 1.75|
Info: 17000 | 4488 12042 | 154 736 | 4235| 0.12 1.87|
Info: 18000 | 4593 12840 | 105 798 | 3361| 0.10 1.97|
Info: 19000 | 4713 13639 | 120 799 | 2498| 0.13 2.10|
Info: 20000 | 4830 14469 | 117 830 | 1642| 0.09 2.19|
Info: 21000 | 4952 15297 | 122 828 | 785| 0.15 2.34|
Info: 22000 | 5062 16101 | 110 804 | 10| 0.28 2.62|
Info: 22010 | 5063 16111 | 1 10 | 0| 0.01 2.63|
Info: Routing complete.
Info: Router1 time 2.63s
Info: Checksum: 0xf5aebfcc
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_graph_engine.u_neuron.group_index_TRELLIS_FF_Q.Q
Info: routing 1.24 1.63 Net u_graph_engine.u_neuron.finishing_TRELLIS_FF_Q_DI_PFUMX_Z_C0[2] (74,16) -> (69,9)
Info: Sink u_graph_engine.x_mem[16]_LUT4_B_Z_LUT4_Z.D
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:80.33-80.44
Info: logic 0.18 1.81 Source u_graph_engine.x_mem[16]_LUT4_B_Z_LUT4_Z.F
Info: routing 0.82 2.63 Net u_graph_engine.x_mem[16]_LUT4_B_Z[1] (69,9) -> (67,4)
Info: Sink u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D_LUT4_Z_D_LUT4_Z.B
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 2.81 Source u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D_LUT4_Z_D_LUT4_Z.F
Info: routing 0.66 3.46 Net u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D_LUT4_Z_D[2] (67,4) -> (67,3)
Info: Sink u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 3.64 Source u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D_LUT4_Z.F
Info: routing 0.45 4.10 Net u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4_D[3] (67,3) -> (67,3)
Info: Sink u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.28 Source u_graph_engine.u_neuron.u_mac8.w_bus_LUT4_Z_4.F
Info: routing 1.66 5.93 Net u_graph_engine.u_neuron.w_group[10] (67,3) -> (69,22)
Info: Sink u_graph_engine.u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.B2
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:93.43-93.50
Info: logic 3.07 9.00 Source u_graph_engine.u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.P2
Info: routing 1.51 10.51 Net u_graph_engine.u_neuron.u_mac8.products[1][2] (69,22) -> (70,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB0.A
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
Info: logic 0.35 10.87 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 10.87 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_FCI_INT (70,13) -> (70,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 10.87 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 10.87 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_COUT (70,13) -> (70,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 10.93 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 10.93 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1$CCU2_FCI_INT (70,13) -> (70,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 10.93 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 10.93 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_15_B1_CCU2C_S1_COUT (70,13) -> (71,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 10.98 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 10.98 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_FCI_INT (71,13) -> (71,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 10.98 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 10.98 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT (71,13) -> (71,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 11.04 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 11.04 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_FCI_INT (71,13) -> (71,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 11.04 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 11.04 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT (71,13) -> (71,13)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 11.36 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.F
Info: routing 0.84 12.21 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_S0 (71,13) -> (71,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB0.B
Info: logic 0.35 12.56 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB0.FCO
Info: routing 0.00 12.56 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_6$CCU2_FCI_INT (71,12) -> (71,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB1.FCI
Info: logic 0.00 12.56 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB1.FCO
Info: routing 0.00 12.56 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_6_COUT (71,12) -> (71,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.62 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCO
Info: routing 0.00 12.62 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_7$CCU2_FCI_INT (71,12) -> (71,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCI
Info: logic 0.00 12.62 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCO
Info: routing 0.00 12.62 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_7_COUT (71,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.68 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO
Info: routing 0.00 12.68 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI
Info: logic 0.00 12.68 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO
Info: routing 0.00 12.68 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_14_COUT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.73 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO
Info: routing 0.00 12.73 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI
Info: logic 0.00 12.73 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO
Info: routing 0.00 12.73 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_13_COUT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.79 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCO
Info: routing 0.00 12.79 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_8$CCU2_FCI_INT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCI
Info: logic 0.00 12.79 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCO
Info: routing 0.00 12.79 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_8_COUT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.84 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCO
Info: routing 0.00 12.84 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_12$CCU2_FCI_INT (72,12) -> (72,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCI
Info: logic 0.00 12.84 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCO
Info: routing 0.00 12.84 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_12_COUT (72,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.90 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 12.90 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1$CCU2_FCI_INT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 12.90 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 12.90 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_COUT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 12.96 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCO
Info: routing 0.00 12.96 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_9$CCU2_FCI_INT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCI
Info: logic 0.00 12.96 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO
Info: routing 0.00 12.96 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_9_COUT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.01 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
Info: routing 0.00 13.01 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
Info: logic 0.00 13.01 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
Info: routing 0.00 13.01 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_10_COUT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.07 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCO
Info: routing 0.00 13.07 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_11$CCU2_FCI_INT (73,12) -> (73,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCI
Info: logic 0.00 13.07 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCO
Info: routing 0.00 13.07 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_11_COUT (73,12) -> (74,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.12 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCO
Info: routing 0.00 13.12 Net u_graph_engine.u_neuron.acc_next_CCU2C_S1_1$CCU2_FCI_INT (74,12) -> (74,12)
Info: Sink u_graph_engine.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCI
Info: logic 0.29 13.42 Source u_graph_engine.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.F
Info: routing 0.12 13.53 Net u_graph_engine.u_neuron.acc_next[31] (74,12) -> (74,12)
Info: Sink u_graph_engine.u_neuron.acc_TRELLIS_FF_Q_31.DI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
Info: setup 0.00 13.53 Source u_graph_engine.u_neuron.acc_TRELLIS_FF_Q_31.DI
Info: 6.24 ns logic, 7.30 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 3.50 3.50 Net rst$TRELLIS_IO_IN (0,14) -> (57,4)
Info: Sink graph_rst_LUT4_Z.C
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_slave.v:23.16-23.19
Info: logic 0.18 3.68 Source graph_rst_LUT4_Z.F
Info: routing 1.43 5.11 Net graph_rst (57,4) -> (64,9)
Info: Sink u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.29 Source u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z_LUT4_Z.F
Info: routing 1.67 6.95 Net u_neuron_memory.access_req_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_D_Z[1] (64,9) -> (67,21)
Info: Sink u_neuron_memory.x_mem[1]_TRELLIS_FF_Q_CE_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.14 Source u_neuron_memory.x_mem[1]_TRELLIS_FF_Q_CE_LUT4_Z.F
Info: routing 1.29 8.43 Net u_neuron_memory.x_mem[1]_TRELLIS_FF_Q_CE (67,21) -> (61,24)
Info: Sink u_neuron_memory.x_mem[1]_TRELLIS_FF_Q_4.CE
Info: setup 0.00 8.43 Source u_neuron_memory.x_mem[1]_TRELLIS_FF_Q_4.CE
Info: 0.54 ns logic, 7.89 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_graph_engine.err_TRELLIS_FF_Q.Q
Info: routing 3.73 4.12 Net graph_err (84,19) -> (3,14)
Info: Sink irq_n_LUT4_Z.D
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_engine.v:116.34-116.43
Info: logic 0.18 4.30 Source irq_n_LUT4_Z.F
Info: routing 0.35 4.65 Net irq_n$TRELLIS_IO_OUT (3,14) -> (0,14)
Info: Sink irq_n$tr_io.I
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/spi_neuron_top.v:67.17-67.22
Info: 0.57 ns logic, 4.07 ns routing
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 73.88 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.43 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.65 ns
Info: Slack histogram:
Info: legend: * represents 17 endpoint(s)
Info: + represents [1,17) endpoint(s)
Info: [ -1035, -393) |*+
Info: [ -393, 249) |*+
Info: [ 249, 891) |+
Info: [ 891, 1533) |+
Info: [ 1533, 2175) |
Info: [ 2175, 2817) |
Info: [ 2817, 3459) |
Info: [ 3459, 4101) |+
Info: [ 4101, 4743) |*+
Info: [ 4743, 5385) |***+
Info: [ 5385, 6027) |***********+
Info: [ 6027, 6669) |********************+
Info: [ 6669, 7311) |************+
Info: [ 7311, 7953) |**************************************+
Info: [ 7953, 8595) |***************************************+
Info: [ 8595, 9237) |*********************+
Info: [ 9237, 9879) |****************************************+
Info: [ 9879, 10521) |*************************************************+
Info: [ 10521, 11163) |************************************************************
Info: [ 11163, 11805) |******************************
0 warnings, 1 error
Info: Program finished normally.
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