FPGA-Neural/hardware/v3/synth/synth_mac2_dsp_packed.tcl at n16-timing-closure - FPGA-Neural - MikiLab Development

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micheleandClaude Sonnet 5 34b15cc0a7 exp: first real Vivado synthesis+P&R on XC7A100T for V3 DSP-packed core (EXP-0059)

Real Vivado 2026.1 run (not estimated) confirms the DSP48 packing
survives actual Xilinx synthesis: mac2_dsp_packed.v uses exactly 1
DSP48E1, and the full neural_processor_packed.v pipeline uses 8
DSP48E1/240 for 2 jobs -- half the DSP of two separate V2 cores for
the same work.

Post-route (real place_design+route_design, not synthesis-only):
WNS -2.414ns @ 200MHz -> Fmax ~134.9MHz, within 0.5% of the
post-synthesis-only estimate. This is the isolated compute core,
out-of-context -- not yet a real N-core system number, flagged as
such in the log entry.

Full writeup, including the two real toolchain fixes needed to get
Vivado running on this machine (CRLF line endings in installLibs.sh,
missing libncurses.so.5 on Ubuntu 26.04), in
hardware/v2/logs/experiments.log EXP-0059.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

2026-09-16 23:18:18 +02:00

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 read_verilog -sv /home/michele/Develop/FPGA-Neural/hardware/v3/rtl/mac2_dsp_packed.v
 synth_design -top mac2_dsp_packed -part xc7a100tcsg324-1 -mode out_of_context
 report_utilization -file /tmp/util_mac2.rpt
 report_timing_summary -file /tmp/timing_mac2.rpt