micheleandClaude Sonnet 5
1ce78dff6e
EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).
EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
71 lines
3.2 KiB
Verilog
71 lines
3.2 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0056 -- generic, recursive binary-tree priority encoder
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// (lowest-set-bit wins), O(log2(WIDTH)) depth.
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//
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// MOTIVATION: dependency_manager.v's own first_ready_idx scan (a
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// serial for-loop overwriting a register variable across up to
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// N_NODES=1024 iterations) is the SAME architectural anti-pattern
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// already found and fixed twice elsewhere in this project (ERR-0027,
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// neural_director.v's free-slot scan; ERR-0028, activation_fill_
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// ctrl's max-tree; ERR-0029, sdram_unified_backend.v's W-cache hit-
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// index) -- a data-dependent sequential overwrite that forces a
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// SERIAL dependency chain across every iteration, even though the
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// result does not logically require one. Those three fixes used a
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// flat one-hot compare + single-level casez priority-encode, correct
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// and efficient for their own small widths (4-8 entries). N_NODES can
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// be up to 1024 in this project's own real configs -- a single flat
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// casez at that width is impractical to hand-write and not guaranteed
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// to synthesize as a balanced tree. This module generalizes the SAME
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// underlying principle (no serial dependency chain) to arbitrary
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// width via recursive halving: each half is encoded independently
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// and in parallel (no dependency between them), and only the FINAL
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// combine step (low_valid ? low_result : high_result) depends on
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// both halves -- giving real O(log2(WIDTH)) depth instead of O(WIDTH).
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//
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// Semantics: idx = index of the LOWEST set bit in `in` (bit 0 has
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// highest priority), valid = |in. This matches dependency_manager.v's
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// own original scan exactly: it iterates ri from N_NODES-1 DOWN TO 0,
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// unconditionally overwriting first_ready_idx on every match -- the
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// LAST (i.e. lowest-index) match therefore wins, not the first one
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// found during the loop's own execution order.
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// ============================================================
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module priority_encoder_lsb #(
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parameter WIDTH = 16,
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parameter IDXW = (WIDTH <= 1) ? 1 : $clog2(WIDTH)
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)(
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input wire [WIDTH-1:0] in,
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output wire [IDXW-1:0] idx,
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output wire valid
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);
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generate
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if (WIDTH <= 1) begin : GEN_BASE
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assign valid = in[0];
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assign idx = {IDXW{1'b0}};
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end else begin : GEN_SPLIT
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localparam LOW_W = WIDTH/2;
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localparam HIGH_W = WIDTH - LOW_W;
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localparam LOW_IDXW = (LOW_W <= 1) ? 1 : $clog2(LOW_W);
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localparam HIGH_IDXW = (HIGH_W <= 1) ? 1 : $clog2(HIGH_W);
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wire [LOW_IDXW-1:0] low_idx;
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wire low_valid;
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wire [HIGH_IDXW-1:0] high_idx;
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wire high_valid;
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priority_encoder_lsb #(.WIDTH(LOW_W)) u_low (
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.in(in[LOW_W-1:0]), .idx(low_idx), .valid(low_valid)
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);
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priority_encoder_lsb #(.WIDTH(HIGH_W)) u_high (
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.in(in[WIDTH-1:LOW_W]), .idx(high_idx), .valid(high_valid)
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);
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assign valid = low_valid | high_valid;
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assign idx = low_valid
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? {{(IDXW-LOW_IDXW){1'b0}}, low_idx}
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: ({{(IDXW-HIGH_IDXW){1'b0}}, high_idx} + LOW_W[IDXW-1:0]);
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end
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endgenerate
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endmodule
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