micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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| 1 | mem_data_width_bits,words_per_tile,steady_state_cycles_per_tile,total_cycles_16tile_job,bit_exact,classification |
|---|---|
| 2 | 16,4,4,80,PASS,RTL SIMULATION isolated ideal-memory (EXP-0032) -- matches real weight_prefetch_engine.v exactly (EXP-0025/26) |
| 3 | 32,2,2,48,PASS,RTL SIMULATION isolated ideal-memory (EXP-0032) |
| 4 | 64,1,1,32,PASS,RTL SIMULATION isolated ideal-memory (EXP-0032) -- exact architectural point: matches P_IN*DATA_WIDTH=64 bits, removes weight-fetch bottleneck entirely (1 cycle/tile = 100% of neural_processor.v's own theoretical per-tile acceptance rate) |
| 5 | 128,1,1,32,PASS,RTL SIMULATION isolated ideal-memory (EXP-0032) -- IDENTICAL to 64-bit, zero further benefit (bus wider than one tile cannot deliver more than 1 tile/transaction in this design) |
| 6 | 16 (real V1 PSRAM physical bus),4,4,n/a,PASS,REAL-PSRAM SIM (EXP-0025/26/28/30) -- physical reality: real bus is fixed at 16 bits regardless of any logical-width experiment; a 64-bit LOGICAL interface backed by the real 16-bit PHYSICAL bus reproduces this exact row (DEC-0028), not the 64-bit row above |