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FPGA-Neural/hardware/v2/nms/synthesis/wt_packed_n8_t256/yosys.log
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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Running command `read_verilog hardware/v2/nms/rtl/nms_weight_packed.v hardware/v2/nms/synthesis/harness_nms_weight_packed.v; chparam -set N_SLOTS 8 -set MAX_TILES 256 harness_nms_weight_packed; synth_ecp5 -json hardware/v2/nms/synthesis/wt_packed_n8_t256/top.json -top harness_nms_weight_packed' --
1. Executing Verilog-2005 frontend: hardware/v2/nms/rtl/nms_weight_packed.v
Parsing Verilog input from `hardware/v2/nms/rtl/nms_weight_packed.v' to AST representation.
Generating RTLIL representation for module `\nms_weight_packed'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: hardware/v2/nms/synthesis/harness_nms_weight_packed.v
Parsing Verilog input from `hardware/v2/nms/synthesis/harness_nms_weight_packed.v' to AST representation.
Generating RTLIL representation for module `\harness_nms_weight_packed'.
Successfully finished Verilog frontend.
Parameter \N_SLOTS = 8
Parameter \MAX_TILES = 256
3. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_nms_weight_packed'.
Parameter \N_SLOTS = 8
Parameter \MAX_TILES = 256
Generating RTLIL representation for module `$paramod$b6de0c11d68b806477a7dcf1df36d46fb4598a85\harness_nms_weight_packed'.
4. Executing SYNTH_LATTICE pass.
4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
4.3. Executing HIERARCHY pass (managing design hierarchy).
4.3.1. Analyzing design hierarchy..
Top module: \harness_nms_weight_packed
Used module: \nms_weight_packed
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \MAX_TILES = 256
4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\nms_weight_packed'.
Parameter \DATA_WIDTH = 8
Parameter \P_IN = 8
Parameter \N_SLOTS = 8
Parameter \MAX_TILES = 256
Generating RTLIL representation for module `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed'.
4.3.3. Analyzing design hierarchy..
Top module: \harness_nms_weight_packed
Used module: $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed
4.3.4. Analyzing design hierarchy..
Top module: \harness_nms_weight_packed
Used module: $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed
Removing unused module `\nms_weight_packed'.
Removed 1 unused modules.
4.4. Executing PROC pass (convert processes to netlists).
4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300 in module harness_nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305 in module harness_nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Marked 1 switch rules as full_case in process $proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603 in module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
Removed a total of 0 dead cases.
4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 2 redundant assignments.
Promoted 194 assignments to connections.
4.4.4. Executing PROC_INIT pass (extract init attributes).
4.4.5. Executing PROC_ARST pass (detect async resets in processes).
4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~130 debug messages>
4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
1/1: $0\lfsr[31:0]
Creating decoders for process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
1/3: $0\chk[7:0]
2/3: $1\chk_next[7:0]
3/3: $1\k[31:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_EN[7:0]$1113
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_DATA[7:0]$1112
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_ADDR[7:0]$1111
4/4: $0\GEN_SLOT[7].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_EN[7:0]$1105
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_DATA[7:0]$1104
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_ADDR[7:0]$1103
4/4: $0\GEN_SLOT[7].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_EN[7:0]$1097
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_DATA[7:0]$1096
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_ADDR[7:0]$1095
4/4: $0\GEN_SLOT[7].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_EN[7:0]$1089
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_DATA[7:0]$1088
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_ADDR[7:0]$1087
4/4: $0\GEN_SLOT[7].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_EN[7:0]$1081
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_DATA[7:0]$1080
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_ADDR[7:0]$1079
4/4: $0\GEN_SLOT[7].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_EN[7:0]$1073
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_DATA[7:0]$1072
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_ADDR[7:0]$1071
4/4: $0\GEN_SLOT[7].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_EN[7:0]$1065
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_DATA[7:0]$1064
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_ADDR[7:0]$1063
4/4: $0\GEN_SLOT[7].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
1/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1057
2/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_DATA[7:0]$1056
3/4: $1$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_ADDR[7:0]$1055
4/4: $0\GEN_SLOT[7].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_EN[7:0]$1049
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_DATA[7:0]$1048
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_ADDR[7:0]$1047
4/4: $0\GEN_SLOT[6].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_EN[7:0]$1041
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_DATA[7:0]$1040
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_ADDR[7:0]$1039
4/4: $0\GEN_SLOT[6].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_EN[7:0]$1033
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_DATA[7:0]$1032
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_ADDR[7:0]$1031
4/4: $0\GEN_SLOT[6].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_EN[7:0]$1025
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_DATA[7:0]$1024
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_ADDR[7:0]$1023
4/4: $0\GEN_SLOT[6].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_EN[7:0]$1017
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_DATA[7:0]$1016
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_ADDR[7:0]$1015
4/4: $0\GEN_SLOT[6].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_EN[7:0]$1009
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_DATA[7:0]$1008
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_ADDR[7:0]$1007
4/4: $0\GEN_SLOT[6].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_EN[7:0]$1001
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_DATA[7:0]$1000
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_ADDR[7:0]$999
4/4: $0\GEN_SLOT[6].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
1/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$993
2/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_DATA[7:0]$992
3/4: $1$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_ADDR[7:0]$991
4/4: $0\GEN_SLOT[6].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_EN[7:0]$985
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_DATA[7:0]$984
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_ADDR[7:0]$983
4/4: $0\GEN_SLOT[5].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_EN[7:0]$977
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_DATA[7:0]$976
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_ADDR[7:0]$975
4/4: $0\GEN_SLOT[5].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_EN[7:0]$969
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_DATA[7:0]$968
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_ADDR[7:0]$967
4/4: $0\GEN_SLOT[5].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_EN[7:0]$961
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_DATA[7:0]$960
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_ADDR[7:0]$959
4/4: $0\GEN_SLOT[5].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_EN[7:0]$953
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_DATA[7:0]$952
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_ADDR[7:0]$951
4/4: $0\GEN_SLOT[5].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_EN[7:0]$945
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_DATA[7:0]$944
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_ADDR[7:0]$943
4/4: $0\GEN_SLOT[5].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_EN[7:0]$937
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_DATA[7:0]$936
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_ADDR[7:0]$935
4/4: $0\GEN_SLOT[5].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
1/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$929
2/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_DATA[7:0]$928
3/4: $1$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_ADDR[7:0]$927
4/4: $0\GEN_SLOT[5].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_EN[7:0]$921
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_DATA[7:0]$920
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_ADDR[7:0]$919
4/4: $0\GEN_SLOT[4].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_EN[7:0]$913
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_DATA[7:0]$912
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_ADDR[7:0]$911
4/4: $0\GEN_SLOT[4].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_EN[7:0]$905
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_DATA[7:0]$904
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_ADDR[7:0]$903
4/4: $0\GEN_SLOT[4].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_EN[7:0]$897
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_DATA[7:0]$896
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_ADDR[7:0]$895
4/4: $0\GEN_SLOT[4].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_EN[7:0]$889
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_DATA[7:0]$888
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_ADDR[7:0]$887
4/4: $0\GEN_SLOT[4].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_EN[7:0]$881
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_DATA[7:0]$880
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_ADDR[7:0]$879
4/4: $0\GEN_SLOT[4].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_EN[7:0]$873
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_DATA[7:0]$872
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_ADDR[7:0]$871
4/4: $0\GEN_SLOT[4].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
1/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$865
2/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_DATA[7:0]$864
3/4: $1$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_ADDR[7:0]$863
4/4: $0\GEN_SLOT[4].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_EN[7:0]$857
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_DATA[7:0]$856
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_ADDR[7:0]$855
4/4: $0\GEN_SLOT[3].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_EN[7:0]$849
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_DATA[7:0]$848
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_ADDR[7:0]$847
4/4: $0\GEN_SLOT[3].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_EN[7:0]$841
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_DATA[7:0]$840
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_ADDR[7:0]$839
4/4: $0\GEN_SLOT[3].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_EN[7:0]$833
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_DATA[7:0]$832
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_ADDR[7:0]$831
4/4: $0\GEN_SLOT[3].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_EN[7:0]$825
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_DATA[7:0]$824
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_ADDR[7:0]$823
4/4: $0\GEN_SLOT[3].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_EN[7:0]$817
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_DATA[7:0]$816
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_ADDR[7:0]$815
4/4: $0\GEN_SLOT[3].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_EN[7:0]$809
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_DATA[7:0]$808
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_ADDR[7:0]$807
4/4: $0\GEN_SLOT[3].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
1/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$801
2/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_DATA[7:0]$800
3/4: $1$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_ADDR[7:0]$799
4/4: $0\GEN_SLOT[3].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_EN[7:0]$793
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_DATA[7:0]$792
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_ADDR[7:0]$791
4/4: $0\GEN_SLOT[2].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_EN[7:0]$785
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_DATA[7:0]$784
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_ADDR[7:0]$783
4/4: $0\GEN_SLOT[2].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_EN[7:0]$777
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_DATA[7:0]$776
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_ADDR[7:0]$775
4/4: $0\GEN_SLOT[2].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_EN[7:0]$769
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_DATA[7:0]$768
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_ADDR[7:0]$767
4/4: $0\GEN_SLOT[2].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_EN[7:0]$761
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_DATA[7:0]$760
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_ADDR[7:0]$759
4/4: $0\GEN_SLOT[2].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_EN[7:0]$753
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_DATA[7:0]$752
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_ADDR[7:0]$751
4/4: $0\GEN_SLOT[2].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_EN[7:0]$745
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_DATA[7:0]$744
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_ADDR[7:0]$743
4/4: $0\GEN_SLOT[2].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
1/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$737
2/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_DATA[7:0]$736
3/4: $1$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_ADDR[7:0]$735
4/4: $0\GEN_SLOT[2].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_EN[7:0]$729
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_DATA[7:0]$728
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_ADDR[7:0]$727
4/4: $0\GEN_SLOT[1].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_EN[7:0]$721
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_DATA[7:0]$720
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_ADDR[7:0]$719
4/4: $0\GEN_SLOT[1].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_EN[7:0]$713
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_DATA[7:0]$712
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_ADDR[7:0]$711
4/4: $0\GEN_SLOT[1].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_EN[7:0]$705
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_DATA[7:0]$704
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_ADDR[7:0]$703
4/4: $0\GEN_SLOT[1].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_EN[7:0]$697
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_DATA[7:0]$696
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_ADDR[7:0]$695
4/4: $0\GEN_SLOT[1].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_EN[7:0]$689
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_DATA[7:0]$688
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_ADDR[7:0]$687
4/4: $0\GEN_SLOT[1].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_EN[7:0]$681
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_DATA[7:0]$680
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_ADDR[7:0]$679
4/4: $0\GEN_SLOT[1].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
1/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$673
2/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_DATA[7:0]$672
3/4: $1$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_ADDR[7:0]$671
4/4: $0\GEN_SLOT[1].GEN_LANE[0].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_EN[7:0]$665
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_DATA[7:0]$664
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_ADDR[7:0]$663
4/4: $0\GEN_SLOT[0].GEN_LANE[7].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_EN[7:0]$657
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_DATA[7:0]$656
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_ADDR[7:0]$655
4/4: $0\GEN_SLOT[0].GEN_LANE[6].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_EN[7:0]$649
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_DATA[7:0]$648
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_ADDR[7:0]$647
4/4: $0\GEN_SLOT[0].GEN_LANE[5].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_EN[7:0]$641
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_DATA[7:0]$640
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_ADDR[7:0]$639
4/4: $0\GEN_SLOT[0].GEN_LANE[4].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_EN[7:0]$633
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_DATA[7:0]$632
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_ADDR[7:0]$631
4/4: $0\GEN_SLOT[0].GEN_LANE[3].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN[7:0]$625
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_DATA[7:0]$624
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_ADDR[7:0]$623
4/4: $0\GEN_SLOT[0].GEN_LANE[2].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_EN[7:0]$617
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_DATA[7:0]$616
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_ADDR[7:0]$615
4/4: $0\GEN_SLOT[0].GEN_LANE[1].rd_data_reg[7:0]
Creating decoders for process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
1/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$609
2/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_DATA[7:0]$608
3/4: $1$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_ADDR[7:0]$607
4/4: $0\GEN_SLOT[0].GEN_LANE[0].rd_data_reg[7:0]
4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\harness_nms_weight_packed.\lfsr' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
created $dff cell `$procdff$1831' with positive edge clock.
Creating register for signal `\harness_nms_weight_packed.\k' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
created $dff cell `$procdff$1832' with positive edge clock.
Creating register for signal `\harness_nms_weight_packed.\chk' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
created $dff cell `$procdff$1833' with positive edge clock.
Creating register for signal `\harness_nms_weight_packed.\chk_next' using process `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
created $dff cell `$procdff$1834' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
created $dff cell `$procdff$1835' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
created $dff cell `$procdff$1836' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
created $dff cell `$procdff$1837' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$602_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
created $dff cell `$procdff$1838' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
created $dff cell `$procdff$1839' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
created $dff cell `$procdff$1840' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
created $dff cell `$procdff$1841' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$601_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
created $dff cell `$procdff$1842' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
created $dff cell `$procdff$1843' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
created $dff cell `$procdff$1844' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
created $dff cell `$procdff$1845' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$600_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
created $dff cell `$procdff$1846' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
created $dff cell `$procdff$1847' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
created $dff cell `$procdff$1848' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
created $dff cell `$procdff$1849' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$599_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
created $dff cell `$procdff$1850' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
created $dff cell `$procdff$1851' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
created $dff cell `$procdff$1852' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
created $dff cell `$procdff$1853' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$598_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
created $dff cell `$procdff$1854' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
created $dff cell `$procdff$1855' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
created $dff cell `$procdff$1856' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
created $dff cell `$procdff$1857' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$597_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
created $dff cell `$procdff$1858' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
created $dff cell `$procdff$1859' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
created $dff cell `$procdff$1860' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
created $dff cell `$procdff$1861' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$596_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
created $dff cell `$procdff$1862' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[7].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
created $dff cell `$procdff$1863' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
created $dff cell `$procdff$1864' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
created $dff cell `$procdff$1865' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
created $dff cell `$procdff$1866' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
created $dff cell `$procdff$1867' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
created $dff cell `$procdff$1868' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
created $dff cell `$procdff$1869' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$594_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
created $dff cell `$procdff$1870' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
created $dff cell `$procdff$1871' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
created $dff cell `$procdff$1872' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
created $dff cell `$procdff$1873' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$593_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
created $dff cell `$procdff$1874' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
created $dff cell `$procdff$1875' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
created $dff cell `$procdff$1876' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
created $dff cell `$procdff$1877' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$592_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
created $dff cell `$procdff$1878' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
created $dff cell `$procdff$1879' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
created $dff cell `$procdff$1880' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
created $dff cell `$procdff$1881' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$591_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
created $dff cell `$procdff$1882' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
created $dff cell `$procdff$1883' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
created $dff cell `$procdff$1884' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
created $dff cell `$procdff$1885' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$590_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
created $dff cell `$procdff$1886' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
created $dff cell `$procdff$1887' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
created $dff cell `$procdff$1888' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
created $dff cell `$procdff$1889' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$589_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
created $dff cell `$procdff$1890' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
created $dff cell `$procdff$1891' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
created $dff cell `$procdff$1892' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
created $dff cell `$procdff$1893' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$588_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
created $dff cell `$procdff$1894' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[6].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
created $dff cell `$procdff$1895' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
created $dff cell `$procdff$1896' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
created $dff cell `$procdff$1897' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
created $dff cell `$procdff$1898' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
created $dff cell `$procdff$1899' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
created $dff cell `$procdff$1900' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
created $dff cell `$procdff$1901' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$586_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
created $dff cell `$procdff$1902' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
created $dff cell `$procdff$1903' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
created $dff cell `$procdff$1904' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
created $dff cell `$procdff$1905' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$585_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
created $dff cell `$procdff$1906' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
created $dff cell `$procdff$1907' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
created $dff cell `$procdff$1908' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
created $dff cell `$procdff$1909' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$584_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
created $dff cell `$procdff$1910' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
created $dff cell `$procdff$1911' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
created $dff cell `$procdff$1912' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
created $dff cell `$procdff$1913' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$583_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
created $dff cell `$procdff$1914' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
created $dff cell `$procdff$1915' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
created $dff cell `$procdff$1916' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
created $dff cell `$procdff$1917' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$582_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
created $dff cell `$procdff$1918' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
created $dff cell `$procdff$1919' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
created $dff cell `$procdff$1920' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
created $dff cell `$procdff$1921' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$581_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
created $dff cell `$procdff$1922' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
created $dff cell `$procdff$1923' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
created $dff cell `$procdff$1924' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
created $dff cell `$procdff$1925' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$580_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
created $dff cell `$procdff$1926' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[5].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
created $dff cell `$procdff$1927' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
created $dff cell `$procdff$1928' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
created $dff cell `$procdff$1929' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
created $dff cell `$procdff$1930' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
created $dff cell `$procdff$1931' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
created $dff cell `$procdff$1932' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
created $dff cell `$procdff$1933' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$578_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
created $dff cell `$procdff$1934' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
created $dff cell `$procdff$1935' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
created $dff cell `$procdff$1936' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
created $dff cell `$procdff$1937' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$577_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
created $dff cell `$procdff$1938' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
created $dff cell `$procdff$1939' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
created $dff cell `$procdff$1940' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
created $dff cell `$procdff$1941' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$576_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
created $dff cell `$procdff$1942' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
created $dff cell `$procdff$1943' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
created $dff cell `$procdff$1944' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
created $dff cell `$procdff$1945' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$575_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
created $dff cell `$procdff$1946' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
created $dff cell `$procdff$1947' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
created $dff cell `$procdff$1948' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
created $dff cell `$procdff$1949' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$574_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
created $dff cell `$procdff$1950' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
created $dff cell `$procdff$1951' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
created $dff cell `$procdff$1952' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
created $dff cell `$procdff$1953' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$573_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
created $dff cell `$procdff$1954' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
created $dff cell `$procdff$1955' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
created $dff cell `$procdff$1956' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
created $dff cell `$procdff$1957' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$572_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
created $dff cell `$procdff$1958' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[4].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
created $dff cell `$procdff$1959' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
created $dff cell `$procdff$1960' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
created $dff cell `$procdff$1961' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
created $dff cell `$procdff$1962' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
created $dff cell `$procdff$1963' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
created $dff cell `$procdff$1964' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
created $dff cell `$procdff$1965' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$570_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
created $dff cell `$procdff$1966' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
created $dff cell `$procdff$1967' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
created $dff cell `$procdff$1968' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
created $dff cell `$procdff$1969' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$569_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
created $dff cell `$procdff$1970' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
created $dff cell `$procdff$1971' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
created $dff cell `$procdff$1972' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
created $dff cell `$procdff$1973' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$568_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
created $dff cell `$procdff$1974' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
created $dff cell `$procdff$1975' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
created $dff cell `$procdff$1976' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
created $dff cell `$procdff$1977' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$567_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
created $dff cell `$procdff$1978' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
created $dff cell `$procdff$1979' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
created $dff cell `$procdff$1980' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
created $dff cell `$procdff$1981' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$566_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
created $dff cell `$procdff$1982' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
created $dff cell `$procdff$1983' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
created $dff cell `$procdff$1984' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
created $dff cell `$procdff$1985' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$565_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
created $dff cell `$procdff$1986' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
created $dff cell `$procdff$1987' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
created $dff cell `$procdff$1988' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
created $dff cell `$procdff$1989' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$564_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
created $dff cell `$procdff$1990' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[3].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
created $dff cell `$procdff$1991' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
created $dff cell `$procdff$1992' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
created $dff cell `$procdff$1993' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
created $dff cell `$procdff$1994' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
created $dff cell `$procdff$1995' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
created $dff cell `$procdff$1996' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
created $dff cell `$procdff$1997' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$562_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
created $dff cell `$procdff$1998' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
created $dff cell `$procdff$1999' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
created $dff cell `$procdff$2000' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
created $dff cell `$procdff$2001' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$561_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
created $dff cell `$procdff$2002' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
created $dff cell `$procdff$2003' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
created $dff cell `$procdff$2004' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
created $dff cell `$procdff$2005' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$560_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
created $dff cell `$procdff$2006' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
created $dff cell `$procdff$2007' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
created $dff cell `$procdff$2008' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
created $dff cell `$procdff$2009' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$559_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
created $dff cell `$procdff$2010' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
created $dff cell `$procdff$2011' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
created $dff cell `$procdff$2012' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
created $dff cell `$procdff$2013' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$558_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
created $dff cell `$procdff$2014' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
created $dff cell `$procdff$2015' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
created $dff cell `$procdff$2016' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
created $dff cell `$procdff$2017' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$557_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
created $dff cell `$procdff$2018' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
created $dff cell `$procdff$2019' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
created $dff cell `$procdff$2020' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
created $dff cell `$procdff$2021' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$556_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
created $dff cell `$procdff$2022' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[2].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
created $dff cell `$procdff$2023' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
created $dff cell `$procdff$2024' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
created $dff cell `$procdff$2025' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
created $dff cell `$procdff$2026' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
created $dff cell `$procdff$2027' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
created $dff cell `$procdff$2028' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
created $dff cell `$procdff$2029' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$554_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
created $dff cell `$procdff$2030' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
created $dff cell `$procdff$2031' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
created $dff cell `$procdff$2032' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
created $dff cell `$procdff$2033' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$553_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
created $dff cell `$procdff$2034' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
created $dff cell `$procdff$2035' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
created $dff cell `$procdff$2036' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
created $dff cell `$procdff$2037' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$552_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
created $dff cell `$procdff$2038' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
created $dff cell `$procdff$2039' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
created $dff cell `$procdff$2040' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
created $dff cell `$procdff$2041' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$551_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
created $dff cell `$procdff$2042' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
created $dff cell `$procdff$2043' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
created $dff cell `$procdff$2044' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
created $dff cell `$procdff$2045' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$550_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
created $dff cell `$procdff$2046' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
created $dff cell `$procdff$2047' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
created $dff cell `$procdff$2048' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
created $dff cell `$procdff$2049' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$549_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
created $dff cell `$procdff$2050' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
created $dff cell `$procdff$2051' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
created $dff cell `$procdff$2052' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
created $dff cell `$procdff$2053' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$548_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
created $dff cell `$procdff$2054' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[1].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
created $dff cell `$procdff$2055' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
created $dff cell `$procdff$2056' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
created $dff cell `$procdff$2057' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
created $dff cell `$procdff$2058' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[7].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
created $dff cell `$procdff$2059' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
created $dff cell `$procdff$2060' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
created $dff cell `$procdff$2061' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[7].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$546_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
created $dff cell `$procdff$2062' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[6].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
created $dff cell `$procdff$2063' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
created $dff cell `$procdff$2064' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
created $dff cell `$procdff$2065' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[6].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$545_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
created $dff cell `$procdff$2066' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[5].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
created $dff cell `$procdff$2067' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
created $dff cell `$procdff$2068' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
created $dff cell `$procdff$2069' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[5].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$544_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
created $dff cell `$procdff$2070' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[4].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
created $dff cell `$procdff$2071' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
created $dff cell `$procdff$2072' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
created $dff cell `$procdff$2073' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[4].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$543_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
created $dff cell `$procdff$2074' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[3].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
created $dff cell `$procdff$2075' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
created $dff cell `$procdff$2076' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
created $dff cell `$procdff$2077' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[3].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$542_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
created $dff cell `$procdff$2078' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[2].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
created $dff cell `$procdff$2079' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
created $dff cell `$procdff$2080' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
created $dff cell `$procdff$2081' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[2].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$541_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
created $dff cell `$procdff$2082' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[1].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
created $dff cell `$procdff$2083' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
created $dff cell `$procdff$2084' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
created $dff cell `$procdff$2085' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[1].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$540_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
created $dff cell `$procdff$2086' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.\GEN_SLOT[0].GEN_LANE[0].rd_data_reg' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
created $dff cell `$procdff$2087' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_ADDR' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
created $dff cell `$procdff$2088' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_DATA' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
created $dff cell `$procdff$2089' with positive edge clock.
Creating register for signal `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN' using process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
created $dff cell `$procdff$2090' with positive edge clock.
4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
Removing empty process `harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:19$300'.
Found and cleaned up 1 empty switch in `\harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
Removing empty process `harness_nms_weight_packed.$proc$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:41$305'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1107'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1099'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1091'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1083'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1075'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1067'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1059'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1051'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1043'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1035'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1027'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1019'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1011'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$1003'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$995'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$987'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$979'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$971'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$963'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$955'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$947'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$939'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$931'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$923'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$915'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$907'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$899'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$891'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$883'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$875'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$867'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$859'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$851'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$843'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$835'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$827'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$819'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$811'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$803'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$795'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$787'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$779'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$771'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$763'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$755'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$747'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$739'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$731'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$723'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$715'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$707'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$699'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$691'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$683'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$675'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$667'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$659'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$651'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$643'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$635'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$627'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$619'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$611'.
Found and cleaned up 2 empty switches in `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
Removing empty process `$paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.$proc$hardware/v2/nms/rtl/nms_weight_packed.v:40$603'.
Cleaned up 130 empty switches.
4.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
<suppressed ~1 debug messages>
Optimizing module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
4.5. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_weight_packed...
Checking module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed...
Found and reported 0 problems.
4.6. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$179069ae10acb01da567d232a076b771a516e742\nms_weight_packed.
<suppressed ~1 debug messages>
4.7. Executing TRIBUF pass.
4.8. Executing DEMINOUT pass (demote inout ports to input or output).
4.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 588 unused cells and 1247 unused wires.
<suppressed ~703 debug messages>
4.11. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_weight_packed...
Found and reported 0 problems.
4.12. Executing OPT pass (performing simple optimizations).
4.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 72 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $flatten\dut.$procmux$1296: \lfsr [7:0] -> { \lfsr [7] 1'1 \lfsr [5:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1827: \lfsr [7:0] -> { \lfsr [7:1] 1'1 }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1560: \lfsr [7:0] -> { \lfsr [7:4] 1'1 \lfsr [2:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1736: \lfsr [7:0] -> { \lfsr [7:2] 1'1 \lfsr [0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1824: \lfsr [7:0] -> { \lfsr [7:1] 1'1 }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1475: \lfsr [7:0] -> { \lfsr [7:5] 1'1 \lfsr [3:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1472: \lfsr [7:0] -> { \lfsr [7:5] 1'1 \lfsr [3:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1648: \lfsr [7:0] -> { \lfsr [7:3] 1'1 \lfsr [1:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1384: \lfsr [7:0] -> { \lfsr [7:6] 1'1 \lfsr [4:0] }
Replacing known input bits on port B of cell $flatten\dut.$procmux$1208: \lfsr [7:0] -> { 1'1 \lfsr [6:0] }
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~68 debug messages>
4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1293:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] $flatten\dut.$0$memwr$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$587_EN[7:0]$990 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1557:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] $flatten\dut.$0$memwr$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$563_EN[7:0]$798 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1733:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] $flatten\dut.$0$memwr$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$547_EN[7:0]$670 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1821:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] $flatten\dut.$0$memwr$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$539_EN[7:0]$606 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1469:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] $flatten\dut.$0$memwr$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$571_EN[7:0]$862 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1645:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] $flatten\dut.$0$memwr$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$555_EN[7:0]$734 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1205:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] $flatten\dut.$0$memwr$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$595_EN[7:0]$1054 [0] }
Consolidated identical input bits for $mux cell $flatten\dut.$procmux$1381:
Old ports: A=8'00000000, B=8'11111111, Y=$flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926
New ports: A=1'0, B=1'1, Y=$flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0]
New connections: $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [7:1] = { $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] $flatten\dut.$0$memwr$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:42$579_EN[7:0]$926 [0] }
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 8 changes.
4.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 72 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Computing hashes of 70 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.12.6. Executing OPT_DFF pass (perform DFF optimizations).
4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>
4.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.12.9. Rerunning OPT passes. (Maybe there is more to do..)
4.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~64 debug messages>
4.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 70 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.12.13. Executing OPT_DFF pass (perform DFF optimizations).
4.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.12.16. Finished fast OPT passes. (There is nothing left to do.)
4.13. Executing FSM pass (extract and optimize FSM).
4.13.1. Executing FSM_DETECT pass (finding FSMs in design).
4.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.14. Executing OPT pass (performing simple optimizations).
4.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 70 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~64 debug messages>
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 70 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$1831 ($dff) from module harness_nms_weight_packed (D = { \lfsr [30:7] $xor$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:21$304_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001).
Adding SRST signal on $procdff$1833 ($dff) from module harness_nms_weight_packed (D = $xor$hardware/v2/nms/synthesis/harness_nms_weight_packed.v:47$313_Y, Q = \chk, rval = 8'00000000).
Adding EN signal on $flatten\dut.$procdff$2055 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[1].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$674_DATA, Q = \dut.GEN_SLOT[1].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$2087 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[0].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$610_DATA, Q = \dut.GEN_SLOT[0].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$1959 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[4].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$866_DATA, Q = \dut.GEN_SLOT[4].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$1895 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[6].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$994_DATA, Q = \dut.GEN_SLOT[6].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$1927 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[5].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$930_DATA, Q = \dut.GEN_SLOT[5].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$1863 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[7].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$1058_DATA, Q = \dut.GEN_SLOT[7].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$1991 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[3].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$802_DATA, Q = \dut.GEN_SLOT[3].GEN_LANE[0].rd_data_reg).
Adding EN signal on $flatten\dut.$procdff$2023 ($dff) from module harness_nms_weight_packed (D = $flatten\dut.$memrd$\GEN_SLOT[2].GEN_LANE[0].mem$hardware/v2/nms/rtl/nms_weight_packed.v:45$738_DATA, Q = \dut.GEN_SLOT[2].GEN_LANE[0].rd_data_reg).
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 9 unused cells and 9 unused wires.
<suppressed ~10 debug messages>
4.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.14.9. Rerunning OPT passes. (Maybe there is more to do..)
4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~46 debug messages>
4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 62 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.14.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.14.16. Finished fast OPT passes. (There is nothing left to do.)
4.15. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 bits (of 32) from mux cell harness_nms_weight_packed.$procmux$1116 ($mux).
Removed top 56 bits (of 512) from wire harness_nms_weight_packed.rd_data_flat.
Removed top 24 bits (of 32) from wire harness_nms_weight_packed.$0\lfsr[31:0].
4.16. Executing PEEPOPT pass (run peephole optimizers).
4.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>
4.18. Executing SHARE pass (SAT-based resource sharing).
4.19. Executing TECHMAP pass (map to technology primitives).
4.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
4.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
4.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.22. Executing TECHMAP pass (map to technology primitives).
4.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
4.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.23. Executing TECHMAP pass (map to technology primitives).
4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
4.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
4.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module harness_nms_weight_packed:
created 0 $alu and 0 $macc cells.
4.25. Executing OPT pass (performing simple optimizations).
4.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 62 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~46 debug messages>
4.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 62 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.25.6. Executing OPT_DFF pass (perform DFF optimizations).
4.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.25.9. Finished fast OPT passes. (There is nothing left to do.)
4.26. Executing MEMORY pass.
4.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
4.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[7].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[2].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[4].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[5].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[6].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[1].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[3].GEN_LANE[0].mem write port 0.
Analyzing harness_nms_weight_packed.dut.GEN_SLOT[0].GEN_LANE[0].mem write port 0.
4.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
4.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\dut.GEN_SLOT[7].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[2].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[4].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[5].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[6].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[1].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[3].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\dut.GEN_SLOT[0].GEN_LANE[0].mem'[0] in module `\harness_nms_weight_packed': merging output FF to cell.
Write port 0: non-transparent.
4.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 8 unused cells and 72 unused wires.
<suppressed ~9 debug messages>
4.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
4.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
4.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[6].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[3].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[2].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[5].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[7].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[1].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[4].GEN_LANE[0].mem via $__DP16KD_
mapping memory harness_nms_weight_packed.dut.GEN_SLOT[0].GEN_LANE[0].mem via $__DP16KD_
<suppressed ~4040 debug messages>
4.29. Executing TECHMAP pass (map to technology primitives).
4.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
4.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
4.29.3. Continuing TECHMAP pass.
Using template $paramod$aeda6af72dd43b6dcc814a6c1f1c1fc277ba8bab$__DP16KD_ for cells of type $__DP16KD_.
Using template $paramod$eed5c07ccc20b30fea5f07adc53d361b0ef0f8bc$__DP16KD_ for cells of type $__DP16KD_.
No more expansions possible.
<suppressed ~71 debug messages>
4.30. Executing OPT pass (performing simple optimizations).
4.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
<suppressed ~386 debug messages>
4.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 40 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Computing hashes of 38 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.
4.30.3. Executing OPT_DFF pass (perform DFF optimizations).
4.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 0 unused cells and 208 unused wires.
<suppressed ~1 debug messages>
4.30.5. Finished fast OPT passes.
4.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.32. Executing OPT pass (performing simple optimizations).
4.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 38 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
4.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 38 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.32.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 4 on $auto$mem.cc:1646:emulate_read_first$2269 ($dff) from module harness_nms_weight_packed.
Setting constant 1-bit at position 0 on $auto$mem.cc:1646:emulate_read_first$2289 ($dff) from module harness_nms_weight_packed.
4.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.32.9. Rerunning OPT passes. (Maybe there is more to do..)
4.32.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
4.32.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 38 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.32.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 4 on $auto$mem.cc:1169:emulate_transparency$2273 ($dffe) from module harness_nms_weight_packed.
Setting constant 1-bit at position 0 on $auto$mem.cc:1169:emulate_transparency$2293 ($dffe) from module harness_nms_weight_packed.
4.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.32.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.32.16. Rerunning OPT passes. (Maybe there is more to do..)
4.32.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \harness_nms_weight_packed..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
4.32.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \harness_nms_weight_packed.
Performed a total of 0 changes.
4.32.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 38 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.32.20. Executing OPT_DFF pass (perform DFF optimizations).
4.32.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.32.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.32.23. Finished fast OPT passes. (There is nothing left to do.)
4.33. Executing TECHMAP pass (map to technology primitives).
4.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
4.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $xor.
No more expansions possible.
<suppressed ~106 debug messages>
4.34. Executing OPT pass (performing simple optimizations).
4.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
<suppressed ~2 debug messages>
4.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 206 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Computing hashes of 198 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Computing hashes of 192 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Computing hashes of 190 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
<suppressed ~48 debug messages>
Removed a total of 16 cells.
4.34.3. Executing OPT_DFF pass (perform DFF optimizations).
4.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 1 unused cells and 3 unused wires.
<suppressed ~2 debug messages>
4.34.5. Finished fast OPT passes.
4.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
4.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
4.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\harness_nms_weight_packed'.
Computing hashes of 189 cells of `\harness_nms_weight_packed'.
Finding duplicate cells in `\harness_nms_weight_packed'.
Removed a total of 0 cells.
4.38. Executing TECHMAP pass (map to technology primitives).
4.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
4.38.2. Continuing TECHMAP pass.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~157 debug messages>
4.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module harness_nms_weight_packed.
4.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
4.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in harness_nms_weight_packed.
4.42. Executing ATTRMVCP pass (move or copy attributes).
4.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \harness_nms_weight_packed..
Removed 0 unused cells and 305 unused wires.
<suppressed ~1 debug messages>
4.44. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_weight_packed...
Found and reported 0 problems.
4.45. Executing TECHMAP pass (map to technology primitives).
4.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
4.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
4.46. Executing ABC9 pass.
4.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module harness_nms_weight_packed.
Found 0 SCCs.
4.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.5. Executing TECHMAP pass (map to technology primitives).
4.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.46.5.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~165 debug messages>
4.46.6. Executing OPT pass (performing simple optimizations).
4.46.6.1. Executing OPT_EXPR pass (perform const folding).
4.46.6.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
4.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.
4.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.
4.46.6.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
4.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
4.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
4.46.6.8. Executing OPT_EXPR pass (perform const folding).
4.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
4.46.7. Executing TECHMAP pass (map to technology primitives).
4.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
4.46.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>
4.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
4.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
4.46.12. Executing AIGMAP pass (map logic to AIG).
Module harness_nms_weight_packed: replaced 110 cells with 734 new cells, skipped 79 cells.
replaced 3 cell types:
23 $_MUX_
12 $_OR_
75 $_XOR_
not replaced 5 cell types:
2 $_AND_
4 $_NOT_
1 $scopeinfo
64 TRELLIS_FF
8 DP16KD
4.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9).
4.46.12.3. Executing XAIGER backend.
<suppressed ~5 debug messages>
Extracted 308 AND gates and 936 wires from module `harness_nms_weight_packed' to a netlist network with 138 inputs and 66 outputs.
4.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9).
4.46.12.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 138/ 66 and = 306 lev = 18 (2.67) mem = 0.01 MB box = 0 bb = 0
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 138/ 66 and = 702 lev = 8 (1.39) mem = 0.01 MB ch = 74 box = 0 bb = 0
ABC: cst = 0 cls = 68 lit = 74 unused = 698 proof = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 702. Ch = 68. Total mem = 0.15 MB. Peak cut mem = 0.01 MB.
ABC: P: Del = 1507.00. Ar = 129.0. Edge = 181. Cut = 10744. T = 0.00 sec
ABC: P: Del = 1507.00. Ar = 129.0. Edge = 181. Cut = 10744. T = 0.00 sec
ABC: P: Del = 1500.00. Ar = 111.0. Edge = 173. Cut = 14576. T = 0.00 sec
ABC: F: Del = 1500.00. Ar = 65.0. Edge = 177. Cut = 11121. T = 0.00 sec
ABC: A: Del = 1500.00. Ar = 65.0. Edge = 177. Cut = 11577. T = 0.00 sec
ABC: A: Del = 1500.00. Ar = 65.0. Edge = 177. Cut = 11520. T = 0.00 sec
ABC: Total time = 0.01 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: Timing manager is given but there is no GIA of boxes.
ABC: Error: Abc_FrameUpdateGia(): Transformation has failed.
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 138/ 66 and = 302 lev = 8 (1.39) mem = 0.01 MB box = 0 bb = 0
ABC: Mapping (K=7) : lut = 46 edge = 177 lev = 3 (0.50) mem = 0.00 MB
ABC: LUT = 46 : 2=4 8.7 % 3=14 30.4 % 4=15 32.6 % 5=12 26.1 % 6=0 0.0 % 7=1 2.2 % Ave = 3.85
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.01 sec
ABC: + time
ABC: elapse: 0.04 seconds, total: 0.04 seconds
4.46.12.6. Executing AIGER frontend.
<suppressed ~8 debug messages>
Removed 605 unused cells and 761 unused wires.
4.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 46
ABC RESULTS: input signals: 13
ABC RESULTS: output signals: 10
<suppressed ~408 debug messages>
Removing temp directory.
4.46.13. Executing TECHMAP pass (map to technology primitives).
4.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
4.46.13.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>
Removed 9 unused cells and 979 unused wires.
4.47. Executing TECHMAP pass (map to technology primitives).
4.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
4.47.2. Continuing TECHMAP pass.
Using template $paramod$286d6b18e782cb14d345c8422500571fedf77570$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2$lut for cells of type $lut.
Using template $paramod$45253126b628cdf0971a5565b0554bd17fb4f592$lut for cells of type $lut.
Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$58dc388ea197d12814928d84eaac2d7a0040ac8b$lut for cells of type $lut.
Using template $paramod$bab3258ad21cb83a958fbc51f2a3a88704f4353a$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$2993a811e89b51499f71434e7c0ba9630bc4a837$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$9ba6905da03a0a1c019168746d69dcdf6a73c6a5$lut for cells of type $lut.
Using template $paramod$d5e3de4774a3f694e9ddbb44f5961246b94d6c5d$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1$lut for cells of type $lut.
Using template $paramod$e83dc90c61703007ae77f8062b2696b0c632cd42$lut for cells of type $lut.
Using template $paramod$e20a0492b86457fc7f35e268ca9ddd8a1263e7c9$lut for cells of type $lut.
Using template $paramod$9c1bff8e8972a0c72143a77eacba8e7c196cfb26$lut for cells of type $lut.
Using template $paramod$5fa86a1279c620f5967326e8163848a280f59736$lut for cells of type $lut.
No more expansions possible.
<suppressed ~430 debug messages>
4.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in harness_nms_weight_packed.
Optimizing lut $abc$4525$lut$aiger4524$320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$4525$lut$aiger4524$153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$4525$lut$aiger4524$256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 106 unused wires.
4.49. Executing AUTONAME pass.
Renamed 245 objects in module harness_nms_weight_packed.
<suppressed ~245 debug messages>
4.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `harness_nms_weight_packed'. Setting top module to harness_nms_weight_packed.
4.50.1. Analyzing design hierarchy..
Top module: \harness_nms_weight_packed
4.50.2. Analyzing design hierarchy..
Top module: \harness_nms_weight_packed
Removed 0 unused modules.
4.51. Printing statistics.
=== harness_nms_weight_packed ===
+----------Local Count, excluding submodules.
|
123 wires
2936 wire bits
123 public wires
2936 public wire bits
4 ports
18 port bits
9 cells
1 $scopeinfo
8 DP16KD
148 submodules
3 L6MUX21
65 LUT4
16 PFUMX
64 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
9 harness_nms_weight_packed
+----------Count including submodules.
|
123 wires
2936 wire bits
123 public wires
2936 public wire bits
4 ports
18 port bits
- memories
- memory bits
- processes
9 cells
1 $scopeinfo
8 DP16KD
148 submodules
3 L6MUX21
65 LUT4
16 PFUMX
64 TRELLIS_FF
4.52. Executing CHECK pass (checking for obvious problems).
Checking module harness_nms_weight_packed...
Found and reported 0 problems.
4.53. Executing JSON backend.
End of script. Logfile hash: d17120ad14, time: 0.50s, user: 0.43s, system: 0.01s, MEM: 39.50 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 36% 21x read_verilog (0 sec), 29% 11x techmap (0 sec), ...
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