micheleandClaude Sonnet 5
8e014d8d49
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations, and results through one physical sdram_controller.v instance. Removes the PSRAM dependency (hardware/v1/rtl/psram_controller.v + memory_interface.v) from the V2 physical path entirely -- V1 itself remains fully unmodified, the golden reference. New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one SDRAM controller, real per-byte DQM write masking added to sdram_controller.v for correct single-byte result writes with no read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the frozen top-level). Two real bugs found and fixed via full-system testing before being accepted (ERR-0023): a deadlock and an off-by-one data-shift bug in the new arbitration logic. Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40 real AUTO REFRESH events interleaved with zero corruption, real Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245 TRELLIS_IO, a real 45-pin reduction from the prior dual-memory design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly rather than masked by the best seed. Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149 signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV found on disk during this step's own pre-commit review -- corrects an earlier draft that wrongly assumed no real pinout data was available. Chip readiness: NO. Real, disclosed blockers remain (no physical host interface exists yet -- the RTL's own reg_* ports are a 110-pin raw test-harness bus; clock source/PLL decision; power/configuration component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE, CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
3866 lines
87 KiB
Plaintext
3866 lines
87 KiB
Plaintext
.device LFE5U-45F
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.comment Part: LFE5U-45F-8CABGA381
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.tile CIB_R10C3:PVT_COUNT2
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unknown: F2B0
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unknown: F3B0
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unknown: F5B0
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unknown: F11B0
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unknown: F13B0
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.tile CIB_R11C89:CIB_LR
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arc: N3_V06N0303 JF5
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.tile CIB_R1C48:CIB
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arc: JD7 S1_V02N0401
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.tile CIB_R1C4:CIB
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arc: S3_V06S0003 JQ0
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arc: S3_V06S0303 E1_H01W0100
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.tile CIB_R1C5:CIB
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arc: E1_H02E0701 S3_V06N0203
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arc: H01W0100 JQ0
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.tile CIB_R1C6:CIB
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arc: JA0 H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R22C4:CIB_DSP
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arc: S1_V02S0301 S3_V06N0003
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.tile CIB_R23C89:CIB_LR
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R25C1:CIB_LR
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arc: E1_H02E0401 V01N0001
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arc: S1_V02S0101 H06W0103
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.tile CIB_R26C1:CIB_LR
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arc: H00L0100 V02S0101
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arc: JA3 H00L0100
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arc: N1_V01N0001 JF5
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arc: S1_V02S0501 H06W0303
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arc: S1_V02S0701 H06W0203
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enum: CIB.JB3MUX 0
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.tile CIB_R28C1:CIB_LR
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arc: JA0 N1_V02S0701
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arc: JA3 N1_V02S0501
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enum: CIB.JB0MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R28C89:CIB_LR
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arc: JA0 W1_H02E0701
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enum: CIB.JB0MUX 0
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.tile CIB_R32C1:CIB_LR
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arc: E1_H02E0501 S1_V02N0501
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arc: E1_H02E0701 JQ5
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.tile CIB_R32C89:CIB_LR
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arc: W1_H02W0501 JF5
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arc: W3_H06W0303 JQ5
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.tile CIB_R34C1:CIB_LR_S
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arc: E1_H02E0701 JF5
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arc: N1_V02N0501 JQ5
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.tile CIB_R34C3:CIB_EBR
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arc: E1_H02E0001 N1_V02S0001
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arc: E1_H02E0101 N3_V06S0103
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arc: E1_H02E0201 N3_V06S0103
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arc: E1_H02E0301 V02S0301
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arc: E1_H02E0401 V02S0401
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arc: E1_H02E0501 V06S0303
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arc: E1_H02E0601 V02S0601
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arc: E1_H02E0701 N3_V06S0203
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arc: N1_V02N0701 W1_H02E0701
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arc: N3_V06N0003 E1_H01W0000
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arc: N3_V06N0103 H06W0103
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arc: N3_V06N0203 H06W0203
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arc: N3_V06N0303 E1_H01W0100
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.tile CIB_R34C4:CIB_EBR
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arc: E1_H01E0001 JF4
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arc: E1_H02E0001 S1_V02N0001
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arc: E1_H02E0101 V06S0103
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arc: E1_H02E0201 N1_V01S0000
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arc: E1_H02E0301 N3_V06S0003
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arc: E1_H02E0401 V06S0203
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arc: E1_H02E0501 N3_V06S0303
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arc: E1_H02E0701 N3_V06S0203
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arc: H00L0000 N1_V02S0001
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arc: H00L0100 E1_H02W0301
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arc: H00R0000 V02S0601
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arc: H00R0100 V02S0701
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arc: H01W0000 JF2
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arc: H01W0100 JF0
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arc: JA0 H00L0100
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arc: JA2 V00T0000
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arc: JA3 H02E0501
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arc: JA5 V00B0000
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arc: JA7 H00L0000
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arc: JB0 V02S0301
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arc: JB1 S1_V02N0101
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arc: JB2 V02S0101
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arc: JB3 H02W0301
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arc: JB4 H00R0000
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arc: JB5 V02S0501
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arc: JB6 H02W0101
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arc: JB7 V02N0701
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arc: JC2 V02N0401
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arc: JC3 H02E0601
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arc: JC4 N1_V02S0001
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arc: JC6 N1_V02S0001
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arc: JCLK0 G_HPBX0000
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arc: JD1 N1_V02S0201
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arc: JD2 V00B0100
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arc: JD3 V00T0100
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arc: JD4 H00R0100
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arc: JD5 H02W0201
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arc: JD6 N1_V02S0401
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arc: JD7 V02S0401
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arc: N1_V02N0101 JF3
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arc: N1_V02N0301 JF1
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arc: N1_V02N0401 JF6
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arc: N1_V02N0501 JF7
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arc: N3_V06N0303 JF5
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arc: V00B0000 N1_V02S0001
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arc: V00B0100 H02E0501
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arc: V00T0000 H02E0001
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arc: V00T0100 N1_V02S0701
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JD0MUX 1
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JCE1MUX 1
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JA1MUX 1
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.tile CIB_R34C5:CIB_EBR
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arc: E1_H02E0001 W1_H02E0501
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arc: E1_H02E0101 N3_V06S0103
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arc: E1_H02E0201 N3_V06S0103
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arc: E1_H02E0301 W1_H02E0201
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arc: E1_H02E0401 W1_H02E0101
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arc: E1_H02E0601 V02S0601
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arc: E1_H02E0701 N1_V02S0701
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arc: H00L0000 N1_V02S0001
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arc: H00L0100 N1_V02S0301
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arc: H00R0000 V02S0601
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arc: H00R0100 W1_H02E0701
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arc: JA0 H00L0000
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arc: JA4 V02N0301
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arc: JA5 H02W0701
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arc: JA7 V02S0301
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arc: JB0 V02S0101
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arc: JB1 V00B0000
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arc: JB2 W1_H02E0301
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arc: JB3 H00R0000
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arc: JB4 V02S0501
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arc: JB5 V02N0501
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arc: JB6 S1_V02N0701
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arc: JB7 V00T0000
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arc: JC0 V02N0401
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arc: JC1 W1_H02E0401
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arc: JC4 N1_V02S0201
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arc: JC5 S1_V02N0201
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arc: JC6 V00T0100
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arc: JC7 V02N0001
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arc: JCE1 H02W0101
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arc: JCLK0 G_HPBX0000
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arc: JD0 W1_H02E0201
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arc: JD1 N1_V01S0000
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arc: JD2 V00B0100
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arc: JD3 H02W0001
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arc: JD4 H02E0001
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arc: JD5 H00L0100
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arc: JD6 H00R0100
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arc: N1_V02N0001 H01E0001
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arc: N1_V02N0301 E1_H01W0100
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arc: N3_V06N0203 E1_H01W0000
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arc: V00B0000 V02N0201
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arc: V00B0100 H02W0501
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arc: V00T0000 V02S0401
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arc: V00T0100 H02E0101
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arc: V01S0000 N3_V06S0103
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arc: W1_H02W0101 N1_V02S0101
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arc: W1_H02W0201 V02S0201
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arc: W1_H02W0301 N1_V01S0100
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JD7MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JCE3MUX 1
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enum: CIB.JA6MUX 0
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enum: CIB.JA1MUX 0
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.tile CIB_R34C6:CIB_EBR
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arc: E1_H02E0001 V02S0001
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arc: E1_H02E0101 V06S0103
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arc: E1_H02E0201 N1_V02S0201
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arc: E1_H02E0301 W1_H02E0301
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arc: E1_H02E0401 V02S0401
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arc: E1_H02E0601 N3_V06S0303
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arc: E1_H02E0701 N3_V06S0203
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arc: H00L0000 H02E0201
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arc: H00L0100 H02E0301
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arc: H00R0000 W1_H02E0401
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arc: H00R0100 N1_V02S0501
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arc: H01W0000 JF3
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arc: H01W0100 JF6
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arc: JA0 W1_H02E0501
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arc: JA1 H00L0100
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arc: JA2 W1_H02E0701
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arc: JA3 V02N0501
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arc: JA5 V00B0000
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arc: JA7 H00R0000
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arc: JB0 V00T0000
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arc: JB1 E1_H02W0101
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arc: JB2 N1_V02S0301
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arc: JB4 V02S0501
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arc: JB5 V02S0701
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arc: JB6 H02W0101
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arc: JB7 W1_H02E0101
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arc: JC2 H00L0000
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arc: JC3 H02W0401
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arc: JC4 W1_H02E0401
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arc: JC6 W1_H02E0401
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arc: JCLK0 G_HPBX0000
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arc: JD0 V02S0001
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arc: JD1 H02E0001
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arc: JD2 N1_V02S0201
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arc: JD3 V00B0100
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arc: JD4 H02E0001
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arc: JD5 H00R0100
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arc: JD6 W1_H02E0201
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arc: JD7 N1_V02S0401
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arc: N3_V06N0203 JF7
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arc: N3_V06N0303 JF5
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arc: V00B0000 W1_H02E0401
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arc: V00B0100 V02S0301
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arc: V00T0000 V02S0601
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arc: W1_H02W0001 N1_V01S0000
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arc: W1_H02W0101 V02S0101
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arc: W1_H02W0301 V06S0003
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arc: W1_H02W0501 V02N0501
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arc: W1_H02W0701 V02N0701
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arc: W3_H06W0103 JF2
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arc: W3_H06W0203 JF4
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JB3MUX 1
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enum: CIB.JCE1MUX 1
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enum: CIB.JC1MUX 0
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enum: CIB.JA6MUX 0
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enum: CIB.JC7MUX 0
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enum: CIB.JA4MUX 0
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enum: CIB.JC5MUX 0
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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.tile CIB_R34C7:CIB_EBR
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arc: E1_H02E0001 W1_H02E0001
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arc: H00R0000 W1_H02E0401
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arc: H00R0100 V02N0701
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arc: JA4 V02N0301
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arc: JA5 S1_V02N0301
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arc: JA6 V00T0100
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arc: JA7 H02E0701
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arc: JB0 V02N0101
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arc: JB1 H00R0100
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arc: JB2 V02S0301
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arc: JB3 W1_H02E0101
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arc: JB4 H02W0301
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arc: JB5 V02S0501
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arc: JB6 V02S0701
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arc: JB7 S1_V02N0501
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arc: JC0 V02S0401
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arc: JC1 N1_V02S0401
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arc: JC4 W1_H02E0601
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arc: JC5 H02E0601
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arc: JC6 S1_V02N0201
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arc: JC7 V02N0201
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arc: JCE1 H02E0101
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arc: JCLK0 G_HPBX0000
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arc: JD0 V00B0100
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arc: JD1 N1_V01S0000
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arc: JD2 H00R0000
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arc: JD3 V02S0201
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arc: JD4 V02N0601
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arc: JD5 V02S0601
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arc: JD6 S1_V02N0401
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arc: JD7 S1_V02N0601
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arc: N3_V06N0003 JF0
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arc: N3_V06N0103 JF1
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arc: V00B0100 W1_H02E0701
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arc: V00T0100 H02E0301
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arc: W1_H02W0101 N1_V01S0100
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arc: W1_H02W0401 N3_V06S0203
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE0MUX 1
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enum: CIB.JCE3MUX 1
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enum: CIB.JCE2MUX 1
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enum: CIB.JA0MUX 0
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enum: CIB.JA1MUX 0
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.tile CIB_R34C8:CIB_EBR
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arc: H00R0000 V02S0601
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arc: JB1 V00B0000
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arc: JB2 H00R0000
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arc: JB3 V02S0101
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arc: JD0 V00B0100
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arc: JD1 W1_H02E0201
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arc: JD2 W1_H02E0001
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arc: JD3 H02E0001
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arc: V00B0000 W1_H02E0401
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arc: V00B0100 W1_H02E0701
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arc: W1_H02W0101 V02S0101
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arc: W1_H02W0301 V02S0301
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enum: CIB.JB0MUX 1
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enum: CIB.JLSR0MUX 0
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enum: CIB.JCE1MUX 1
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enum: CIB.JCE0MUX 1
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enum: CIB.JCLK0MUX 0
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.tile CIB_R5C1:CIB_PLL1
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R5C89:CIB_PLL1
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arc: W3_H06W0303 S3_V06N0303
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C3:CIB_PLL3
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arc: E1_H02E0501 N1_V01S0100
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enum: CIB.JA3MUX 0
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enum: CIB.JB3MUX 0
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.tile CIB_R70C42:VCIB_DCU0
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C43:VCIB_DCUA
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C44:VCIB_DCUB
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
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enum: CIB.JB1MUX 0
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enum: CIB.JB3MUX 0
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enum: CIB.JB5MUX 0
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enum: CIB.JB7MUX 0
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enum: CIB.JC0MUX 0
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enum: CIB.JC2MUX 0
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enum: CIB.JC4MUX 0
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enum: CIB.JC6MUX 0
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enum: CIB.JD0MUX 0
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enum: CIB.JD2MUX 0
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enum: CIB.JD4MUX 0
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enum: CIB.JD6MUX 0
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.tile CIB_R70C45:VCIB_DCUC
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enum: CIB.JA1MUX 0
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enum: CIB.JA3MUX 0
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enum: CIB.JA5MUX 0
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enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C46:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C47:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C48:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C49:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C4:CIB
|
|
arc: E1_H02E0501 V06S0303
|
|
arc: JA0 H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C50:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C51:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C52:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C53:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C5:CIB
|
|
arc: JA0 H02E0501
|
|
enum: CIB.JB0MUX 0
|
|
|
|
.tile CIB_R70C69:VCIB_DCU0
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C6:CIB_EFB0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C70:VCIB_DCUA
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C71:VCIB_DCUB
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C72:VCIB_DCUC
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C73:VCIB_DCUD
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C74:VCIB_DCUF
|
|
enum: CIB.JA1MUX 0
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC2MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C75:VCIB_DCU3
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA7MUX 0
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JC0MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC6MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C76:VCIB_DCU2
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C77:VCIB_DCUG
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C78:VCIB_DCUH
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C79:VCIB_DCUI
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB7MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD6MUX 0
|
|
|
|
.tile CIB_R70C7:CIB_EFB1
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JA4MUX 0
|
|
enum: CIB.JA5MUX 0
|
|
enum: CIB.JA6MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB4MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JB6MUX 0
|
|
enum: CIB.JC3MUX 0
|
|
enum: CIB.JC4MUX 0
|
|
enum: CIB.JC5MUX 0
|
|
enum: CIB.JD3MUX 0
|
|
enum: CIB.JD4MUX 0
|
|
enum: CIB.JD5MUX 0
|
|
|
|
.tile CIB_R70C80:VCIB_DCU1
|
|
enum: CIB.JB1MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
enum: CIB.JB5MUX 0
|
|
enum: CIB.JD0MUX 0
|
|
enum: CIB.JD2MUX 0
|
|
|
|
.tile CIB_R70C87:CIB_PLL3
|
|
enum: CIB.JA3MUX 0
|
|
enum: CIB.JB3MUX 0
|
|
|
|
.tile MIB_R0C3:BANKREF0
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R0C40:TMID_0
|
|
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
|
|
|
|
.tile MIB_R0C4:PIOT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C5:PIOT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R0C6:PIOT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R10C0:BANKREF7
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R10C12:EBR_SPINE_UL1
|
|
arc: G_VPTX0000 G_HPRX0000
|
|
|
|
.tile MIB_R10C40:CMUX_UL_0
|
|
arc: G_DCS0CLK0 G_VPFN0000
|
|
arc: G_ULPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C41:CMUX_UR_0
|
|
arc: G_DCS0CLK1 G_VPFN0000
|
|
arc: G_URPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R10C90:BANKREF2
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R11C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R12C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
|
|
.tile MIB_R1C4:PICT0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C5:PICT1
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R1C6:PICT0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R23C90:PICR0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R24C90:PICR1
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R26C0:PICL0
|
|
arc: JDIA JPADDIA_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C0:PICL1_DQS0
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R27C90:PICR1_DQS0
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C0:PICL2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R28C90:PICR2_DQS1
|
|
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C0:PICL0
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R32C90:PICR0
|
|
arc: JDIA JPADDIA_PIO
|
|
arc: JDIB JPADDIB_PIO
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R33C0:PICL1
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOC.HYSTERESIS ON
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R33C90:PICR1
|
|
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOA.HYSTERESIS ON
|
|
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOB.HYSTERESIS ON
|
|
|
|
.tile MIB_R34C0:MIB_CIB_LR
|
|
enum: PIOC.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R45C90:PICR1
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
enum: PIOD.HYSTERESIS ON
|
|
|
|
.tile MIB_R46C90:MIB_CIB_LR_A
|
|
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
|
|
|
|
.tile MIB_R58C40:CMUX_LL_0
|
|
arc: G_DCS1CLK0 G_VPFN0000
|
|
arc: G_LLPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R58C41:CMUX_LR_0
|
|
arc: G_DCS1CLK1 G_VPFN0000
|
|
arc: G_LRPCLK0 G_VPFS0000
|
|
|
|
.tile MIB_R71C3:BANKREF8
|
|
enum: BANK.VCCIO 3V3
|
|
|
|
.tile MIB_R71C4:EFB0_PICB0
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
|
|
unknown: F54B1
|
|
unknown: F56B1
|
|
unknown: F82B1
|
|
unknown: F94B1
|
|
|
|
.tile MIB_R71C5:EFB1_PICB1
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
|
|
|
|
.tile R13C4:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R13C5:PLC2
|
|
arc: N3_V06N0203 S3_V06N0103
|
|
|
|
.tile R19C4:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R19C5:PLC2
|
|
arc: N3_V06N0103 S3_V06N0003
|
|
|
|
.tile R23C78:PLC2
|
|
word: SLICED.K1.INIT 1111111111111111
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.C1MUX 1
|
|
enum: SLICED.D1MUX 1
|
|
|
|
.tile R23C87:PLC2
|
|
arc: E1_H02E0701 V06N0203
|
|
|
|
.tile R24C4:PLC2
|
|
arc: H00R0100 V02N0501
|
|
arc: V00B0100 S1_V02N0301
|
|
arc: A7 N1_V02S0301
|
|
arc: B7 V02N0701
|
|
arc: C7 E1_H02W0601
|
|
arc: D7 V02N0401
|
|
arc: F0 F5A_SLICE
|
|
arc: F1 FXA_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: F3 FXB_SLICE
|
|
arc: F4 F5C_SLICE
|
|
arc: F5 FXC_SLICE
|
|
arc: F6 F5D_SLICE
|
|
arc: M0 V00B0100
|
|
arc: M1 H00R0100
|
|
arc: M2 V00B0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00R0100
|
|
arc: M6 V00B0100
|
|
arc: S1_V02S0101 F3
|
|
word: SLICEA.K0.INIT 0000000000000000
|
|
word: SLICEA.K1.INIT 0000000000000000
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEC.K0.INIT 0000000000000000
|
|
word: SLICEC.K1.INIT 0000000000000000
|
|
word: SLICED.K0.INIT 0000000000000000
|
|
word: SLICED.K1.INIT 1000001001000001
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.B0MUX 1
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.D0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.A1MUX 1
|
|
enum: SLICEA.B1MUX 1
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEA.D1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEC.D0MUX 1
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.A1MUX 1
|
|
enum: SLICEC.B1MUX 1
|
|
enum: SLICEC.C1MUX 1
|
|
enum: SLICEC.D1MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.A0MUX 1
|
|
enum: SLICED.B0MUX 1
|
|
enum: SLICED.C0MUX 1
|
|
enum: SLICED.D0MUX 1
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R24C5:PLC2
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
|
|
.tile R24C6:PLC2
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
|
|
.tile R25C2:PLC2
|
|
arc: E1_H02E0101 E1_H01W0100
|
|
|
|
.tile R25C3:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0401 V06N0203
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: V00T0000 V02N0601
|
|
arc: B0 E1_H02W0301
|
|
arc: C0 W1_H02E0401
|
|
arc: CE1 H00L0000
|
|
arc: CE3 H02E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0001
|
|
arc: E1_H01E0101 Q2
|
|
arc: E1_H02E0001 Q0
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0601 Q6
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0100 Q0
|
|
arc: M2 E1_H02W0601
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S3_V06S0003 Q0
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C4:PLC2
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 S1_V02N0401
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0001 V01N0001
|
|
arc: S1_V02S0201 H02E0201
|
|
arc: S1_V02S0401 N3_V06S0203
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: A0 F5
|
|
arc: A1 H02W0501
|
|
arc: A4 V00T0100
|
|
arc: A5 E1_H01W0000
|
|
arc: B0 V00B0000
|
|
arc: B1 V00B0000
|
|
arc: B4 H01E0101
|
|
arc: B5 H00L0000
|
|
arc: C0 H02E0601
|
|
arc: C1 F4
|
|
arc: C4 S1_V02N0201
|
|
arc: C5 S1_V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0001
|
|
arc: D1 V02N0201
|
|
arc: D4 V02N0601
|
|
arc: D5 V02N0401
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0100 Q1
|
|
arc: W3_H06W0103 Q1
|
|
word: SLICEC.K0.INIT 0110010101101010
|
|
word: SLICEC.K1.INIT 0110001101101100
|
|
word: SLICEA.K0.INIT 0101100101101010
|
|
word: SLICEA.K1.INIT 0100101101111000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C5:PLC2
|
|
arc: H00L0000 W1_H02E0001
|
|
arc: H00L0100 H02W0301
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 V02N0501
|
|
arc: N3_V06N0003 S3_V06N0003
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: W1_H02W0601 S1_V02N0601
|
|
arc: CE2 H00L0100
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q5
|
|
arc: M5 H00R0100
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: W1_H02W0501 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R25C6:PLC2
|
|
arc: S3_V06S0003 H06E0003
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
|
|
.tile R26C15:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R26C21:PLC2
|
|
arc: E3_H06E0303 W3_H06E0303
|
|
|
|
.tile R26C27:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R26C33:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R26C39:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C3:PLC2
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0501 S3_V06N0303
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: A1 H00L0100
|
|
arc: B0 V02N0101
|
|
arc: B1 V02N0301
|
|
arc: C0 V02N0601
|
|
arc: C1 S1_V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D1 F0
|
|
arc: E3_H06E0103 Q1
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: LSR0 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
word: SLICEA.K1.INIT 0101011010101001
|
|
word: SLICEA.K0.INIT 0000110000111111
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C45:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C4:PLC2
|
|
arc: E1_H02E0001 S3_V06N0003
|
|
arc: E1_H02E0201 S3_V06N0103
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: S1_V02S0101 N1_V02S0101
|
|
arc: V00B0100 V02N0301
|
|
arc: V00T0000 E1_H02W0201
|
|
arc: W3_H06W0203 E1_H01W0000
|
|
arc: W3_H06W0303 E1_H01W0100
|
|
arc: C4 Q4
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D4 V02N0601
|
|
arc: E1_H01E0001 F4
|
|
arc: F4 F4_SLICE
|
|
arc: LSR0 V00B0100
|
|
arc: M4 V00T0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N1_V01N0001 Q4
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0203 Q4
|
|
word: SLICEC.K0.INIT 0000111100000000
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C51:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R26C5:PLC2
|
|
arc: N1_V02N0201 H01E0001
|
|
arc: N1_V02N0301 S3_V06N0003
|
|
arc: N1_V02N0501 W1_H02E0501
|
|
arc: V00B0100 H02W0501
|
|
arc: W1_H02W0301 S3_V06N0003
|
|
arc: A0 V02N0501
|
|
arc: A1 H00L0100
|
|
arc: A4 V00T0000
|
|
arc: B0 V02N0301
|
|
arc: B1 V02N0101
|
|
arc: B2 W1_H02E0301
|
|
arc: B4 S1_V02N0701
|
|
arc: C0 F4
|
|
arc: C1 S1_V02N0401
|
|
arc: C2 V02N0401
|
|
arc: C4 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 F2
|
|
arc: D2 H02E0001
|
|
arc: D4 H02E0201
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR0 H02E0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: V00T0000 Q0
|
|
word: SLICEC.K0.INIT 0110010101101010
|
|
word: SLICEB.K0.INIT 0000110000111111
|
|
word: SLICEA.K0.INIT 0100101101111000
|
|
word: SLICEA.K1.INIT 0101011010101001
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R26C63:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R26C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C6:PLC2
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: W1_H02W0201 S1_V02N0201
|
|
arc: W1_H02W0501 S1_V02N0501
|
|
|
|
.tile R26C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R26C87:PLC2
|
|
arc: N3_V06N0203 W3_H06E0203
|
|
|
|
.tile R26C9:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C15:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R27C21:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C27:PLC2
|
|
arc: E3_H06E0103 W3_H06E0103
|
|
|
|
.tile R27C2:PLC2
|
|
arc: E1_H02E0501 E1_H01W0100
|
|
|
|
.tile R27C33:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C39:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C3:PLC2
|
|
arc: E1_H02E0101 S1_V02N0101
|
|
arc: E1_H02E0201 S1_V02N0201
|
|
arc: E1_H02E0301 V02N0301
|
|
arc: E1_H02E0701 S1_V02N0701
|
|
arc: H00L0000 S1_V02N0201
|
|
arc: H00R0100 S1_V02N0701
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 E1_H01W0100
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: S1_V02S0201 N1_V02S0201
|
|
arc: V00B0100 H02W0501
|
|
arc: V00T0000 H02W0201
|
|
arc: A0 V02N0701
|
|
arc: A1 H02W0701
|
|
arc: A2 H02E0501
|
|
arc: A3 V00T0000
|
|
arc: B0 V02N0101
|
|
arc: B1 E1_H01W0100
|
|
arc: B2 V01N0001
|
|
arc: B3 H00L0000
|
|
arc: B4 V02N0501
|
|
arc: C0 E1_H01W0000
|
|
arc: C1 V02N0401
|
|
arc: C2 H00L0000
|
|
arc: C3 H00L0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D1 V01S0100
|
|
arc: D2 V02N0001
|
|
arc: D3 V00B0100
|
|
arc: D4 H00R0100
|
|
arc: E1_H01E0001 F4
|
|
arc: E3_H06E0003 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: H00L0100 Q1
|
|
arc: H01W0100 Q0
|
|
arc: LSR1 E1_H02W0301
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0100 F3
|
|
word: SLICEB.K1.INIT 0100101101111000
|
|
word: SLICEB.K0.INIT 0110010101101010
|
|
word: SLICEA.K0.INIT 0011010111001010
|
|
word: SLICEA.K1.INIT 0100011110111000
|
|
word: SLICEC.K0.INIT 0000000011001100
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.A0MUX 1
|
|
enum: SLICEC.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C45:PLC2
|
|
arc: E3_H06E0303 W3_H06E0203
|
|
|
|
.tile R27C4:PLC2
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 V02N0601
|
|
arc: N1_V02N0201 H02E0201
|
|
arc: N1_V02N0301 H02E0301
|
|
arc: N1_V02N0401 H01E0001
|
|
arc: S1_V02S0401 N1_V02S0401
|
|
arc: S1_V02S0501 V01N0101
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02S0101
|
|
arc: V00T0000 V02N0601
|
|
arc: V00T0100 V02N0701
|
|
arc: W1_H02W0501 V02N0501
|
|
arc: A0 E1_H01E0001
|
|
arc: A3 H02E0701
|
|
arc: B0 V01N0001
|
|
arc: C0 V02N0401
|
|
arc: CE0 N1_V02S0201
|
|
arc: CE1 H02E0101
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D3 V00T0100
|
|
arc: E1_H01E0001 F3
|
|
arc: E1_H01E0101 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: H01W0100 Q0
|
|
arc: M2 V00T0000
|
|
arc: M4 V00B0000
|
|
arc: M5 E1_H02W0001
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0001 Q0
|
|
arc: N1_V02N0601 Q4
|
|
arc: N1_V02N0701 Q5
|
|
arc: S3_V06S0203 Q4
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q4
|
|
arc: V01S0100 Q0
|
|
arc: W1_H02W0201 Q2
|
|
arc: W1_H02W0701 Q7
|
|
word: SLICEB.K1.INIT 0000000010101010
|
|
word: SLICEA.K0.INIT 0100000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C51:PLC2
|
|
arc: E3_H06E0003 W3_H06E0303
|
|
|
|
.tile R27C57:PLC2
|
|
arc: E3_H06E0103 W3_H06E0003
|
|
|
|
.tile R27C5:PLC2
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00R0000 S1_V02N0401
|
|
arc: N1_V02N0101 H01E0101
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: W1_H02W0301 V02N0301
|
|
arc: CE1 S1_V02N0201
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M3 H00R0000
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V02N0501 Q7
|
|
arc: V01S0100 Q3
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R27C63:PLC2
|
|
arc: E3_H06E0203 W3_H06E0103
|
|
|
|
.tile R27C69:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C6:PLC2
|
|
arc: W1_H02W0001 V01N0001
|
|
|
|
.tile R27C75:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C81:PLC2
|
|
arc: E3_H06E0203 W3_H06E0203
|
|
|
|
.tile R27C87:PLC2
|
|
arc: S1_V02S0701 W3_H06E0203
|
|
|
|
.tile R27C9:PLC2
|
|
arc: E3_H06E0003 W3_H06E0003
|
|
|
|
.tile R28C3:PLC2
|
|
arc: E1_H02E0401 E1_H01W0000
|
|
arc: H00R0000 S1_V02N0601
|
|
arc: H00R0100 H02W0701
|
|
arc: N1_V02N0001 S3_V06N0003
|
|
arc: N1_V02N0201 S3_V06N0103
|
|
arc: N1_V02N0301 E1_H02W0301
|
|
arc: N1_V02N0401 H06W0203
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 S3_V06N0303
|
|
arc: N1_V02N0701 S3_V06N0203
|
|
arc: S1_V02S0501 E1_H01W0100
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: V00B0100 H02W0701
|
|
arc: C7 V00T0000
|
|
arc: CE0 V02S0201
|
|
arc: CE3 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D7 H00R0100
|
|
arc: E1_H01E0101 F7
|
|
arc: E3_H06E0203 Q4
|
|
arc: F7 F7_SLICE
|
|
arc: M1 H00R0000
|
|
arc: M2 V00B0100
|
|
arc: M4 E1_H02W0401
|
|
arc: M7 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V02N0101 Q1
|
|
arc: N3_V06N0203 Q4
|
|
arc: S3_V06S0103 Q2
|
|
arc: S3_V06S0203 Q4
|
|
arc: V00T0000 Q2
|
|
word: SLICED.K1.INIT 1111000000001111
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C4:PLC2
|
|
arc: H00L0000 V02N0001
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0201 H06W0103
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: N1_V02N0601 S1_V02N0601
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00T0100 V02N0501
|
|
arc: A3 V01N0101
|
|
arc: A4 N1_V01N0101
|
|
arc: A6 E1_H01W0000
|
|
arc: B3 V01N0001
|
|
arc: B6 N1_V01S0000
|
|
arc: C3 H00L0100
|
|
arc: C4 S1_V02N0001
|
|
arc: C6 E1_H01E0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D3 H00R0000
|
|
arc: D4 E1_H01W0100
|
|
arc: D6 N1_V02S0601
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: E1_H02E0201 Q0
|
|
arc: E1_H02E0501 Q7
|
|
arc: E1_H02E0601 Q4
|
|
arc: E3_H06E0203 Q4
|
|
arc: F2 F5B_SLICE
|
|
arc: F4 F4_SLICE
|
|
arc: F6 F6_SLICE
|
|
arc: H00L0100 Q3
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q7
|
|
arc: LSR0 H02W0301
|
|
arc: LSR1 H02W0301
|
|
arc: M0 V00T0100
|
|
arc: M2 V00B0000
|
|
arc: M3 H02W0201
|
|
arc: M4 V00B0100
|
|
arc: M5 H00L0000
|
|
arc: M6 H02E0401
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 F2
|
|
arc: N1_V01N0101 Q4
|
|
arc: N1_V02N0401 F6
|
|
arc: N1_V02N0701 Q7
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0401 Q6
|
|
arc: S3_V06S0003 Q0
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V00B0000 F4
|
|
arc: V00B0100 Q5
|
|
arc: V01S0000 Q3
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0701 Q5
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
word: SLICED.K0.INIT 1100010011110101
|
|
word: SLICEC.K0.INIT 1111000001010000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEC.B0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C5:PLC2
|
|
arc: E1_H02E0301 S1_V02N0301
|
|
arc: N1_V02N0301 S1_V02N0301
|
|
arc: N1_V02N0401 S3_V06N0203
|
|
arc: N1_V02N0701 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: W1_H02W0201 E1_H01W0000
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: W1_H02W0401 H01E0001
|
|
arc: CE0 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q2
|
|
arc: H01W0100 Q2
|
|
arc: M0 V00B0000
|
|
arc: M2 H02E0601
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: N1_V01N0001 Q0
|
|
arc: S3_V06S0103 Q2
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C6:PLC2
|
|
arc: N1_V02N0201 W1_H02E0201
|
|
arc: N1_V02N0501 S3_V06N0303
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: V00B0100 W1_H02E0501
|
|
arc: W3_H06W0203 S3_V06N0203
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0000 Q6
|
|
arc: LSR1 H02E0301
|
|
arc: M6 V00B0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V02N0601 Q6
|
|
arc: S3_V06S0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R28C7:PLC2
|
|
arc: S3_V06S0203 H06E0203
|
|
arc: W3_H06W0003 S3_V06N0003
|
|
arc: W3_H06W0103 S3_V06N0103
|
|
|
|
.tile R28C87:PLC2
|
|
arc: E1_H02E0701 V02S0701
|
|
|
|
.tile R29C3:PLC2
|
|
arc: E1_H02E0501 S1_V02N0501
|
|
arc: E1_H02E0601 V02S0601
|
|
arc: H00L0000 S1_V02N0001
|
|
arc: H00R0000 H02W0601
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0101 S1_V02N0001
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: V00B0100 H02W0501
|
|
arc: A0 V02N0501
|
|
arc: A2 S1_V02N0501
|
|
arc: B0 E1_H01W0100
|
|
arc: B2 S1_V02N0301
|
|
arc: C0 S1_V02N0401
|
|
arc: C2 H02W0601
|
|
arc: CE0 H00L0000
|
|
arc: CE1 N1_V02S0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V02N0201
|
|
arc: E1_H02E0001 Q0
|
|
arc: E3_H06E0303 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F5B_SLICE
|
|
arc: M2 V00B0100
|
|
arc: M3 H00R0000
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0301 Q3
|
|
arc: N1_V02N0701 Q5
|
|
word: SLICEB.K0.INIT 1000000001000000
|
|
word: SLICEB.K1.INIT 0000000000000000
|
|
word: SLICEA.K0.INIT 1000000000000000
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.A1MUX 1
|
|
enum: SLICEB.B1MUX 1
|
|
enum: SLICEB.C1MUX 1
|
|
enum: SLICEB.D1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R29C4:PLC2
|
|
arc: H00R0000 V02S0401
|
|
arc: N1_V02N0501 N1_V01S0100
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: V00B0000 S1_V02N0001
|
|
arc: V00B0100 H02E0501
|
|
arc: W1_H02W0601 V01N0001
|
|
arc: A1 V01N0101
|
|
arc: B0 V02N0301
|
|
arc: B1 V00B0000
|
|
arc: C0 N1_V02S0401
|
|
arc: C1 V02N0401
|
|
arc: C7 V02N0201
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V00B0100
|
|
arc: D1 V02N0001
|
|
arc: D7 V02N0401
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F7 F7_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 F1
|
|
arc: M2 H02E0601
|
|
arc: M5 H00R0000
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q5
|
|
arc: N1_V01N0101 Q2
|
|
arc: N1_V02N0001 Q0
|
|
arc: S1_V02S0201 Q0
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0203 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q2
|
|
arc: W1_H02W0501 F7
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICED.K1.INIT 0000000011110000
|
|
word: SLICEA.K1.INIT 1000110000100011
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.MODE LOGIC
|
|
enum: SLICED.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICED.A1MUX 1
|
|
enum: SLICED.B1MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
|
|
.tile R29C5:PLC2
|
|
arc: N1_V02N0201 S1_V02N0201
|
|
arc: N1_V02N0301 H01E0101
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S3_V06S0003 H01E0001
|
|
|
|
.tile R29C6:PLC2
|
|
arc: S3_V06S0303 H06E0303
|
|
|
|
.tile R30C3:PLC2
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0501 E1_H01W0100
|
|
arc: N1_V02N0601 V01N0001
|
|
|
|
.tile R30C4:PLC2
|
|
arc: E1_H02E0201 V02N0201
|
|
arc: H00R0100 V02S0501
|
|
arc: N1_V02N0301 H02W0301
|
|
arc: S3_V06S0003 N1_V01S0000
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: V00B0000 V02N0001
|
|
arc: A3 V02N0701
|
|
arc: B0 H02W0301
|
|
arc: B3 H00R0100
|
|
arc: C0 V02N0401
|
|
arc: C3 S1_V02N0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 S1_V02N0201
|
|
arc: D3 V02S0201
|
|
arc: E1_H01E0001 Q2
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0701 Q7
|
|
arc: F0 F0_SLICE
|
|
arc: F3 F3_SLICE
|
|
arc: H01W0100 F3
|
|
arc: M2 V00B0000
|
|
arc: M4 E1_H01E0101
|
|
arc: M7 H02W0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q7
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0201 Q0
|
|
arc: N1_V02N0401 Q4
|
|
arc: N1_V02N0601 Q4
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0103 Q2
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q4
|
|
word: SLICEA.K0.INIT 1111001111000000
|
|
word: SLICEB.K1.INIT 1000010000100001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.A0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C5:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: N1_V02N0001 H01E0001
|
|
arc: N1_V02N0301 S1_V02N0201
|
|
arc: S3_V06S0103 H01E0101
|
|
arc: S3_V06S0203 H01E0001
|
|
arc: W1_H02W0201 V02N0201
|
|
arc: W1_H02W0301 S1_V02N0301
|
|
arc: CE2 V02N0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK2 CLK0
|
|
arc: V01S0100 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R30C6:PLC2
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
|
|
.tile R31C3:PLC2
|
|
arc: E1_H02E0001 N3_V06S0003
|
|
arc: E1_H02E0301 N3_V06S0003
|
|
arc: N1_V02N0001 H06W0003
|
|
arc: N1_V02N0301 H06W0003
|
|
arc: N1_V02N0401 V01N0001
|
|
arc: N1_V02N0501 V01N0101
|
|
arc: S1_V02S0301 N3_V06S0003
|
|
arc: V00B0000 V02N0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00B0000
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: S3_V06S0303 Q6
|
|
arc: V01S0000 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C4:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0601 V01N0001
|
|
arc: H00L0000 H02E0001
|
|
arc: H00R0100 S1_V02N0501
|
|
arc: N1_V02N0001 H02E0001
|
|
arc: N1_V02N0201 S1_V02N0701
|
|
arc: N1_V02N0401 N3_V06S0203
|
|
arc: N1_V02N0701 S1_V02N0701
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0701 V01N0101
|
|
arc: S3_V06S0003 N3_V06S0003
|
|
arc: S3_V06S0103 N1_V01S0100
|
|
arc: S3_V06S0203 N1_V01S0000
|
|
arc: CE3 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H02E0501 Q7
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX CE
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C5:PLC2
|
|
arc: E1_H02E0301 W1_H02E0301
|
|
arc: H00R0000 H02W0401
|
|
arc: H00R0100 H02W0501
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0601 E1_H01W0000
|
|
arc: V00B0000 N1_V02S0001
|
|
arc: V00B0100 V02N0301
|
|
arc: A0 H02E0501
|
|
arc: A2 V00B0000
|
|
arc: B0 H02E0101
|
|
arc: B2 H00L0000
|
|
arc: C0 V02N0601
|
|
arc: C2 N1_V01S0100
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 F2
|
|
arc: D2 V02N0001
|
|
arc: E1_H02E0101 Q1
|
|
arc: E1_H02E0201 Q2
|
|
arc: F0 F0_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00B0100
|
|
arc: LSR1 V00B0100
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0100
|
|
arc: M3 H01W0100
|
|
arc: M5 H00R0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0101 Q3
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0301 Q1
|
|
arc: S1_V02S0501 Q5
|
|
arc: V00T0100 Q3
|
|
word: SLICEB.K0.INIT 0011100101101100
|
|
word: SLICEA.K0.INIT 0100011110111000
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C6:PLC2
|
|
arc: H00L0000 H02E0201
|
|
arc: H00L0100 H02E0101
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
arc: V00B0000 V02N0201
|
|
arc: A0 H00R0000
|
|
arc: B0 H02E0301
|
|
arc: C0 H00L0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 Q0
|
|
arc: F0 F0_SLICE
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q0
|
|
arc: LSR0 E1_H02W0301
|
|
arc: LSR1 E1_H02W0301
|
|
arc: M2 W1_H02E0601
|
|
arc: M4 V00B0000
|
|
arc: M5 H00L0100
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR1 LSR1
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR0
|
|
arc: N3_V06N0003 Q0
|
|
arc: S1_V02S0001 Q0
|
|
arc: S1_V02S0201 Q2
|
|
arc: S1_V02S0401 Q6
|
|
arc: S1_V02S0601 Q4
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q2
|
|
arc: V01S0000 Q5
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0401 Q4
|
|
arc: W1_H02W0501 Q5
|
|
arc: W3_H06W0003 Q0
|
|
word: SLICEA.K0.INIT 0110100110010110
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET SET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R31C8:PLC2
|
|
arc: W1_H02W0301 V02N0301
|
|
|
|
.tile R32C11:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C15:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C17:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C21:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C23:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C27:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C29:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C33:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C35:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C39:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C3:PLC2
|
|
arc: E1_H02E0201 E1_H01W0000
|
|
arc: V00B0100 V02S0301
|
|
arc: A0 W1_H02E0701
|
|
arc: A1 W1_H02E0501
|
|
arc: A2 S1_V02N0701
|
|
arc: A5 V00T0100
|
|
arc: B0 E1_H02W0301
|
|
arc: B1 V00T0000
|
|
arc: B2 E1_H02W0101
|
|
arc: B5 N1_V01S0000
|
|
arc: C5 V00T0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 V02N0201
|
|
arc: D1 E1_H02W0001
|
|
arc: D2 V00B0100
|
|
arc: D5 V02N0401
|
|
arc: E1_H01E0001 Q5
|
|
arc: E1_H02E0301 Q1
|
|
arc: E1_H02E0701 Q5
|
|
arc: F0 F0_SLICE
|
|
arc: F1 F1_SLICE
|
|
arc: F2 F2_SLICE
|
|
arc: F5 F5_SLICE
|
|
arc: H00L0000 Q0
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 F5
|
|
arc: N1_V01N0101 Q0
|
|
arc: N1_V02N0001 Q2
|
|
arc: N1_V02N0701 Q5
|
|
arc: N3_V06N0303 Q5
|
|
arc: S1_V02S0001 Q2
|
|
arc: S3_V06S0003 Q0
|
|
arc: V00T0000 Q2
|
|
arc: V00T0100 Q1
|
|
arc: V01S0000 Q1
|
|
arc: V01S0100 Q5
|
|
word: SLICEA.K0.INIT 1011101110001000
|
|
word: SLICEA.K1.INIT 1010101011001100
|
|
word: SLICEB.K0.INIT 1011101110001000
|
|
word: SLICEC.K1.INIT 1000001001000001
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEA.C1MUX 1
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 1
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.MODE LOGIC
|
|
enum: SLICEC.CCU2.INJECT1_1 _NONE_
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 1
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C41:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C45:PLC2
|
|
arc: W3_H06W0303 E3_H06W0203
|
|
|
|
.tile R32C47:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C4:PLC2
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: H00R0100 V02S0701
|
|
arc: N1_V01N0101 N3_V06S0203
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: N1_V02N0401 E1_H01W0000
|
|
arc: N3_V06N0003 S1_V02N0301
|
|
arc: N3_V06N0103 S1_V02N0101
|
|
arc: N3_V06N0203 S1_V02N0401
|
|
arc: N3_V06N0303 S1_V02N0501
|
|
arc: S1_V02S0001 N1_V02S0501
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0401 H01E0001
|
|
arc: S1_V02S0601 E1_H01W0000
|
|
arc: S1_V02S0701 E1_H02W0701
|
|
arc: V00T0100 H02W0101
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H00L0100 Q3
|
|
arc: H01W0000 Q1
|
|
arc: H01W0100 Q5
|
|
arc: LSR0 V00T0100
|
|
arc: LSR1 V00T0100
|
|
arc: M1 H00L0100
|
|
arc: M3 H01W0100
|
|
arc: M5 H00R0100
|
|
arc: M7 H02E0201
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR1
|
|
arc: MUXLSR1 LSR0
|
|
arc: MUXLSR2 LSR1
|
|
arc: MUXLSR3 LSR1
|
|
arc: N1_V01N0001 Q7
|
|
arc: S1_V02S0101 Q1
|
|
arc: S1_V02S0301 Q3
|
|
arc: S1_V02S0501 Q5
|
|
arc: V01S0100 Q7
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C51:PLC2
|
|
arc: W3_H06W0203 E3_H06W0203
|
|
|
|
.tile R32C53:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C57:PLC2
|
|
arc: W3_H06W0203 E3_H06W0103
|
|
|
|
.tile R32C59:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C5:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
arc: E1_H02E0301 E3_H06W0003
|
|
arc: N1_V02N0001 S1_V02N0001
|
|
arc: N1_V02N0201 E3_H06W0103
|
|
arc: N1_V02N0301 E3_H06W0003
|
|
arc: N1_V02N0601 S1_V02N0301
|
|
arc: N3_V06N0003 E3_H06W0003
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 V01N0001
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
arc: W1_H02W0101 E3_H06W0103
|
|
arc: W1_H02W0301 E3_H06W0003
|
|
arc: A0 E1_H01E0001
|
|
arc: B0 W1_H02E0301
|
|
arc: CLK0 G_HPBX0000
|
|
arc: D0 E1_H02W0001
|
|
arc: F0 F0_SLICE
|
|
arc: H01W0000 Q0
|
|
arc: MUXCLK0 CLK0
|
|
arc: S1_V02S0001 Q0
|
|
word: SLICEA.K0.INIT 1110111001000100
|
|
enum: SLICEA.MODE LOGIC
|
|
enum: SLICEA.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEA.C0MUX 1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 1
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C63:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C69:PLC2
|
|
arc: W3_H06W0103 E3_H06W0103
|
|
|
|
.tile R32C6:PLC2
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: H00L0000 V02S0201
|
|
arc: H00R0000 H02W0401
|
|
arc: N1_V02N0201 E1_H01W0000
|
|
arc: S1_V02S0001 N1_V01S0000
|
|
arc: S1_V02S0201 N1_V02S0701
|
|
arc: S1_V02S0301 V01N0101
|
|
arc: S1_V02S0401 V01N0001
|
|
arc: V00T0000 V02S0401
|
|
arc: CLK0 G_HPBX0000
|
|
arc: H01W0100 Q1
|
|
arc: M1 H00R0000
|
|
arc: M2 V00T0000
|
|
arc: M5 H00L0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: S1_V02S0501 Q5
|
|
arc: S3_V06S0103 Q1
|
|
arc: V01S0100 Q2
|
|
arc: W1_H02W0701 Q5
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R32C75:PLC2
|
|
arc: W3_H06W0103 E3_H06W0003
|
|
|
|
.tile R32C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C7:PLC2
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: V00B0100 H02E0701
|
|
arc: W1_H02W0001 E1_H02W0001
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q5
|
|
arc: H00R0000 Q6
|
|
arc: H01W0000 Q4
|
|
arc: LSR0 W1_H02E0301
|
|
arc: LSR1 W1_H02E0301
|
|
arc: M0 V00B0100
|
|
arc: M4 E1_H01E0101
|
|
arc: M5 H00R0000
|
|
arc: M6 V00T0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: MUXLSR0 LSR0
|
|
arc: MUXLSR2 LSR0
|
|
arc: MUXLSR3 LSR1
|
|
arc: S1_V02S0501 Q5
|
|
arc: S1_V02S0601 Q6
|
|
arc: V00T0000 Q0
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0401 Q4
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R32C81:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R32C83:PLC2
|
|
arc: W3_H06W0303 E3_H06W0303
|
|
|
|
.tile R32C87:PLC2
|
|
arc: W3_H06W0303 E1_H02W0501
|
|
|
|
.tile R32C8:PLC2
|
|
arc: N1_V02N0301 H06W0003
|
|
|
|
.tile R32C9:PLC2
|
|
arc: W1_H02W0001 E3_H06W0003
|
|
|
|
.tile R33C3:PLC2
|
|
arc: E1_H02E0301 N1_V01S0100
|
|
arc: E1_H02E0401 N1_V01S0000
|
|
arc: N1_V02N0201 E1_H02W0201
|
|
arc: N1_V02N0401 E1_H02W0401
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 N1_V01S0000
|
|
arc: S1_V02S0601 N1_V02S0301
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R33C4:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: E1_H02E0701 N1_V01S0100
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: E3_H06E0303 N3_V06S0303
|
|
arc: H00L0100 V02S0101
|
|
arc: H00R0000 V02S0601
|
|
arc: S1_V02S0101 E1_H02W0101
|
|
arc: S1_V02S0301 E1_H02W0301
|
|
arc: S1_V02S0401 H06W0203
|
|
arc: S1_V02S0501 N1_V02S0501
|
|
arc: S1_V02S0601 H06W0303
|
|
arc: V00B0100 V02S0301
|
|
arc: V00T0100 V02S0501
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q0
|
|
arc: E1_H02E0001 Q2
|
|
arc: E1_H02E0301 Q3
|
|
arc: M0 V00B0100
|
|
arc: M2 V00T0100
|
|
arc: M3 H00L0100
|
|
arc: M5 H00R0000
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V02N0501 Q5
|
|
arc: N1_V02N0701 Q5
|
|
arc: S1_V02S0701 Q5
|
|
arc: V01S0000 Q5
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C5:PLC2
|
|
arc: E1_H02E0301 N1_V02S0301
|
|
arc: E3_H06E0103 H01E0101
|
|
arc: H00L0000 N1_V02S0201
|
|
arc: H00L0100 N1_V02S0101
|
|
arc: H00R0100 N1_V02S0501
|
|
arc: S1_V02S0101 E1_H01W0100
|
|
arc: S1_V02S0201 E1_H01W0000
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 H02E0401
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: W1_H02W0201 V06S0103
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0101 Q6
|
|
arc: E1_H02E0201 Q2
|
|
arc: E1_H02E0601 Q6
|
|
arc: E1_H02E0701 Q7
|
|
arc: E3_H06E0003 Q3
|
|
arc: E3_H06E0303 Q6
|
|
arc: M2 H02W0601
|
|
arc: M3 H00R0100
|
|
arc: M5 H00L0100
|
|
arc: M6 W1_H02E0401
|
|
arc: M7 H00L0000
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: MUXCLK3 CLK0
|
|
arc: N1_V01N0001 Q6
|
|
arc: N1_V01N0101 Q5
|
|
arc: N1_V02N0401 Q6
|
|
arc: S1_V02S0501 Q7
|
|
arc: S3_V06S0303 Q5
|
|
arc: V01S0000 Q2
|
|
arc: V01S0100 Q6
|
|
arc: W1_H02W0301 Q3
|
|
arc: W1_H02W0401 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG1.SD 0
|
|
enum: SLICEC.REG1.REGSET RESET
|
|
enum: SLICEC.REG1.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG0.SD 0
|
|
enum: SLICEB.REG0.REGSET RESET
|
|
enum: SLICEB.REG0.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C6:PLC2
|
|
arc: H00R0100 W1_H02E0701
|
|
arc: S1_V02S0001 W1_H02E0001
|
|
arc: S1_V02S0101 N1_V02S0001
|
|
arc: S1_V02S0301 W1_H02E0301
|
|
arc: S1_V02S0401 W1_H02E0401
|
|
arc: S1_V02S0501 N1_V01S0100
|
|
arc: S1_V02S0601 H02E0601
|
|
arc: S1_V02S0701 H01E0101
|
|
arc: V00B0000 V02S0001
|
|
arc: V00T0100 H02E0301
|
|
arc: W1_H02W0101 N1_V01S0100
|
|
arc: W1_H02W0601 N1_V02S0601
|
|
arc: CLK0 G_HPBX0000
|
|
arc: E1_H01E0001 Q0
|
|
arc: E1_H01E0101 Q4
|
|
arc: H01W0000 Q3
|
|
arc: H01W0100 Q4
|
|
arc: M0 V00B0000
|
|
arc: M1 H00R0100
|
|
arc: M3 H02W0201
|
|
arc: M4 V00T0100
|
|
arc: MUXCLK0 CLK0
|
|
arc: MUXCLK1 CLK0
|
|
arc: MUXCLK2 CLK0
|
|
arc: N1_V01N0001 Q3
|
|
arc: N1_V01N0101 Q1
|
|
arc: V01S0000 Q0
|
|
arc: W1_H02W0301 Q1
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG1.SD 0
|
|
enum: SLICEA.REG1.REGSET RESET
|
|
enum: SLICEA.REG1.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEA.GSR DISABLED
|
|
enum: SLICEA.REG0.SD 0
|
|
enum: SLICEA.REG0.REGSET RESET
|
|
enum: SLICEA.REG0.LSRMODE LSR
|
|
enum: SLICEA.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEB.GSR DISABLED
|
|
enum: SLICEB.REG1.SD 0
|
|
enum: SLICEB.REG1.REGSET RESET
|
|
enum: SLICEB.REG1.LSRMODE LSR
|
|
enum: SLICEB.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICEC.GSR DISABLED
|
|
enum: SLICEC.REG0.SD 0
|
|
enum: SLICEC.REG0.REGSET RESET
|
|
enum: SLICEC.REG0.LSRMODE LSR
|
|
enum: SLICEC.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C7:PLC2
|
|
arc: H00R0100 V02S0501
|
|
arc: S1_V02S0201 W1_H02E0201
|
|
arc: S1_V02S0301 H01E0101
|
|
arc: S1_V02S0401 H06E0203
|
|
arc: S1_V02S0501 H06E0303
|
|
arc: S1_V02S0601 H01E0001
|
|
arc: S1_V02S0701 W1_H02E0701
|
|
arc: V00T0000 V02S0601
|
|
arc: W1_H02W0201 N1_V01S0000
|
|
arc: CLK0 G_HPBX0000
|
|
arc: M6 V00T0000
|
|
arc: M7 H00R0100
|
|
arc: MUXCLK3 CLK0
|
|
arc: V01S0000 Q7
|
|
arc: V01S0100 Q6
|
|
arc: W3_H06W0203 Q7
|
|
arc: W3_H06W0303 Q6
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG0.SD 0
|
|
enum: SLICED.REG0.REGSET RESET
|
|
enum: SLICED.REG0.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
enum: SLICED.GSR DISABLED
|
|
enum: SLICED.REG1.SD 0
|
|
enum: SLICED.REG1.REGSET RESET
|
|
enum: SLICED.REG1.LSRMODE LSR
|
|
enum: SLICED.CEMUX 1
|
|
enum: LSR0.SRMODE LSR_OVER_CE
|
|
enum: LSR0.LSRMUX LSR
|
|
enum: LSR1.SRMODE LSR_OVER_CE
|
|
enum: LSR1.LSRMUX LSR
|
|
enum: CLK0.CLKMUX CLK
|
|
|
|
.tile R33C8:PLC2
|
|
arc: S1_V02S0101 H06E0103
|
|
arc: S1_V02S0301 H06E0003
|
|
arc: S1_V02S0601 H06E0303
|
|
|
|
.tile R35C3:PLC2
|
|
arc: E1_H02E0301 V06S0003
|
|
|
|
.tile R35C4:PLC2
|
|
arc: E1_H02E0401 N3_V06S0203
|
|
arc: E1_H02E0501 N3_V06S0303
|
|
arc: E1_H02E0701 N1_V02S0701
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N3_V06S0103
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R35C5:PLC2
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0201 N1_V01S0000
|
|
arc: N1_V02N0301 W1_H02E0301
|
|
arc: N1_V02N0401 H02E0401
|
|
arc: N1_V02N0501 H02E0501
|
|
|
|
.tile R35C6:PLC2
|
|
arc: E1_H02E0101 V06S0103
|
|
arc: E1_H02E0601 N3_V06S0303
|
|
arc: N1_V02N0501 N3_V06S0303
|
|
arc: N1_V02N0701 W1_H02E0701
|
|
|
|
.tile R35C7:PLC2
|
|
arc: N1_V02N0101 H02E0101
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0601 H02E0601
|
|
arc: N1_V02N0701 H06E0203
|
|
|
|
.tile R36C4:PLC2
|
|
arc: E3_H06E0003 N3_V06S0003
|
|
arc: E3_H06E0103 N1_V01S0100
|
|
arc: E3_H06E0203 N3_V06S0203
|
|
arc: E3_H06E0303 N1_V01S0100
|
|
arc: N1_V02N0001 N3_V06S0003
|
|
arc: N1_V02N0101 N3_V06S0103
|
|
arc: V01S0000 N3_V06S0103
|
|
|
|
.tile R36C5:PLC2
|
|
arc: E1_H02E0601 V06S0303
|
|
arc: N1_V02N0201 N3_V06S0103
|
|
arc: N1_V02N0701 N3_V06S0203
|
|
|
|
.tile R36C7:PLC2
|
|
arc: N1_V02N0201 H06E0103
|
|
arc: N1_V02N0301 H06E0003
|
|
arc: N1_V02N0401 H06E0203
|
|
arc: N1_V02N0501 H06E0303
|
|
arc: N1_V02N0601 W1_H02E0601
|
|
|
|
.tile R37C4:PLC2
|
|
arc: N1_V02N0401 N1_V01S0000
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R39C3:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R3C48:PLC2
|
|
arc: N1_V02N0401 S1_V02N0401
|
|
|
|
.tile R40C16:PLC2
|
|
word: SLICEB.K0.INIT 0000000000000000
|
|
enum: SLICEB.MODE LOGIC
|
|
enum: SLICEB.CCU2.INJECT1_0 _NONE_
|
|
enum: SLICEB.A0MUX 1
|
|
enum: SLICEB.B0MUX 1
|
|
enum: SLICEB.C0MUX 1
|
|
enum: SLICEB.D0MUX 1
|
|
|
|
.tile R43C4:PLC2
|
|
arc: S3_V06S0103 N3_V06S0103
|
|
|
|
.tile R45C3:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
|
|
.tile R49C4:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R51C3:PLC2
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R55C4:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R57C3:PLC2
|
|
arc: S3_V06S0203 N3_V06S0103
|
|
|
|
.tile R5C47:PLC2
|
|
arc: E1_H01E0001 E3_H06W0003
|
|
|
|
.tile R5C48:PLC2
|
|
arc: N1_V02N0401 H01E0001
|
|
|
|
.tile R5C53:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R5C59:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R5C65:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R5C71:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R5C77:PLC2
|
|
arc: W3_H06W0003 E3_H06W0003
|
|
|
|
.tile R5C83:PLC2
|
|
arc: W3_H06W0003 E3_H06W0303
|
|
|
|
.tile R61C4:PLC2
|
|
arc: S3_V06S0203 N3_V06S0203
|
|
|
|
.tile R63C3:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R67C4:PLC2
|
|
arc: S3_V06S0303 N3_V06S0203
|
|
|
|
.tile R69C3:PLC2
|
|
arc: V01S0100 N3_V06S0303
|
|
|
|
.tile R7C4:PLC2
|
|
arc: S3_V06S0003 N3_V06S0303
|
|
arc: S3_V06S0103 N3_V06S0003
|
|
|
|
.tile R7C5:PLC2
|
|
arc: N3_V06N0203 S3_V06N0203
|
|
|
|
.tile TAP_R25C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R26C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R27C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R28C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R29C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R30C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R31C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R32C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R33C13:TAP_DRIVE
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.tile TAP_R34C13:TAP_DRIVE_CIB
|
|
arc: L_HPBX0000 G_VPTX0000
|
|
|
|
.bram_init 3
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
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|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
|
000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
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000 000 000 000 000 000 000 000
|
|
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.tile_group MIB_R34C6:MIB_EBR2 MIB_R34C7:MIB_EBR3 MIB_R34C8:MIB_EBR4
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word: EBR1.WID 110000000
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word: EBR1.CSDECODE_A 111
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word: EBR1.CSDECODE_B 111
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enum: EBR1.MODE PDPW16KD
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enum: EBR1.PDPW16KD.DATA_WIDTH_R 36
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enum: EBR1.REGMODE_A NOREG
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enum: EBR1.REGMODE_B NOREG
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enum: EBR1.RESETMODE ASYNC
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enum: EBR1.ASYNC_RESET_RELEASE ASYNC
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enum: EBR1.GSR DISABLED
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enum: EBR1.CLKAMUX CLKA
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enum: EBR1.CLKBMUX CLKB
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enum: EBR1.RSTAMUX INV
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enum: EBR1.RSTBMUX INV
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enum: EBR1.CEAMUX CEA
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enum: EBR1.CEBMUX CEB
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enum: EBR1.OCEAMUX INV
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enum: EBR1.OCEBMUX OCEB
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.tile_group MIB_R34C4:MIB_EBR0 MIB_R34C5:MIB_EBR1
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word: EBR0.WID 001000000
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word: EBR0.CSDECODE_A 111
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word: EBR0.CSDECODE_B 111
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enum: EBR0.MODE PDPW16KD
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enum: EBR0.PDPW16KD.DATA_WIDTH_R 36
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enum: EBR0.REGMODE_A NOREG
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enum: EBR0.REGMODE_B NOREG
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enum: EBR0.RESETMODE ASYNC
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enum: EBR0.ASYNC_RESET_RELEASE ASYNC
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enum: EBR0.GSR DISABLED
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enum: EBR0.CLKAMUX CLKA
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enum: EBR0.CLKBMUX CLKB
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enum: EBR0.RSTAMUX INV
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enum: EBR0.RSTBMUX INV
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enum: EBR0.CEAMUX CEA
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enum: EBR0.CEBMUX CEB
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enum: EBR0.OCEAMUX INV
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enum: EBR0.OCEBMUX OCEB
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