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FPGA-Neural/hardware/v2/nms/synthesis/act_rep_n2/top.config
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micheleandClaude Sonnet 5 8e014d8d49 V2.0.0 hardware freeze - single SDRAM 
FASE #1 hardware freeze for FPGA-Neural V2, N4/P8, single external
SDRAM (Alliance Memory AS4C4M16SA-6TIN) serving weights, activations,
and results through one physical sdram_controller.v instance. Removes
the PSRAM dependency (hardware/v1/rtl/psram_controller.v +
memory_interface.v) from the V2 physical path entirely -- V1 itself
remains fully unmodified, the golden reference.

New RTL: sdram_unified_backend.v (2-way W/AR arbitration over one
SDRAM controller, real per-byte DQM write masking added to
sdram_controller.v for correct single-byte result writes with no
read-modify-write), nms_neural_multiprocessor_sdram_unified.v (the
frozen top-level). Two real bugs found and fixed via full-system
testing before being accepted (ERR-0023): a deadlock and an off-by-one
data-shift bug in the new arbitration logic.

Real results: N=4 and N=2 D-Stress bit-exact (256/256 neurons), 40
real AUTO REFRESH events interleaved with zero corruption, real
Yosys+nextpnr-ecp5 synthesis/P&R for LFE5U-45F-8CABGA381 (149/245
TRELLIS_IO, a real 45-pin reduction from the prior dual-memory
design). Timing is MARGINAL (1/8 P&R seeds >=80MHz), reported honestly
rather than masked by the best seed.

Real, sourced ball-level pinout for the SDRAM bus + clk/rst (39/149
signals, P&R-verified) using the official Lattice ECP5U-45 pinout CSV
found on disk during this step's own pre-commit review -- corrects an
earlier draft that wrongly assumed no real pinout data was available.

Chip readiness: NO. Real, disclosed blockers remain (no physical host
interface exists yet -- the RTL's own reg_* ports are a 110-pin raw
test-harness bus; clock source/PLL decision; power/configuration
component selection) -- see hardware/v2/docs/{HARDWARE_FREEZE,
CHIP_READINESS,OPEN_ITEMS}.md for the complete, itemized status.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-06 13:39:55 +02:00

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.device LFE5U-45F
.comment Part: LFE5U-45F-8CABGA381
.tile CIB_R10C3:PVT_COUNT2
unknown: F2B0
unknown: F3B0
unknown: F5B0
unknown: F11B0
unknown: F13B0
.tile CIB_R11C1:CIB_LR
arc: E3_H06E0303 JQ5
.tile CIB_R1C34:CIB
arc: S3_V06S0003 H06W0003
.tile CIB_R1C36:CIB
arc: S1_V02S0201 JQ0
arc: S3_V06S0003 E3_H06W0003
.tile CIB_R1C37:CIB
arc: E1_H02E0501 S1_V02N0501
arc: E3_H06E0203 S3_V06N0203
arc: W3_H06W0003 JQ0
.tile CIB_R1C38:CIB
arc: JA0 H02E0501
enum: CIB.JB0MUX 0
.tile CIB_R1C41:CIB
arc: E1_H02E0701 V06N0203
.tile CIB_R1C42:CIB
arc: W3_H06W0003 JQ0
.tile CIB_R1C43:CIB
arc: E3_H06E0303 W3_H06E0203
arc: JA0 W1_H02E0701
enum: CIB.JB0MUX 0
.tile CIB_R1C48:CIB
arc: JD7 E1_H01W0100
.tile CIB_R1C49:CIB
arc: H01W0100 W3_H06E0303
.tile CIB_R34C13:CIB_EBR
arc: E3_H06E0003 W3_H06E0003
.tile CIB_R34C19:CIB_EBR
arc: E3_H06E0003 W3_H06E0003
.tile CIB_R34C1:CIB_LR_S
arc: E3_H06E0303 S3_V06N0303
.tile CIB_R34C25:CIB_EBR
arc: E3_H06E0003 W3_H06E0003
.tile CIB_R34C31:CIB_EBR
arc: E3_H06E0103 W3_H06E0003
arc: S1_V02S0301 W3_H06E0003
.tile CIB_R34C34:CIB_EBR
arc: S1_V02S0101 H06E0103
.tile CIB_R34C37:CIB_EBR
arc: S1_V02S0101 W3_H06E0103
.tile CIB_R34C7:CIB_EBR
arc: E3_H06E0003 W3_H06E0303
.tile CIB_R35C1:CIB_LR
arc: E3_H06E0303 JF5
arc: JA3 E1_H02W0701
enum: CIB.JB3MUX 0
.tile CIB_R35C89:CIB_LR
arc: JA0 W1_H02E0701
arc: S1_V02S0501 H06E0303
arc: W3_H06W0303 JQ5
enum: CIB.JB0MUX 0
.tile CIB_R37C1:CIB_LR
arc: E3_H06E0303 JQ5
arc: JA0 H02W0701
enum: CIB.JB0MUX 0
.tile CIB_R37C89:CIB_LR
arc: JA0 N1_V02S0501
arc: S1_V02S0501 W3_H06E0303
enum: CIB.JB0MUX 0
.tile CIB_R38C1:CIB_LR
arc: E3_H06E0303 JQ5
.tile CIB_R38C89:CIB_LR
arc: JA3 V02S0501
enum: CIB.JB3MUX 0
.tile CIB_R40C1:CIB_LR
arc: E3_H06E0303 JQ5
arc: JA0 E1_H02W0501
arc: N3_V06N0303 JQ5
enum: CIB.JB0MUX 0
.tile CIB_R5C1:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R5C89:CIB_PLL1
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C3:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile CIB_R70C42:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C43:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C44:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C45:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C46:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C47:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C48:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C49:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C50:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C51:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C52:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C53:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C69:VCIB_DCU0
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C6:CIB_EFB0
enum: CIB.JB3MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C70:VCIB_DCUA
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C71:VCIB_DCUB
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C72:VCIB_DCUC
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C73:VCIB_DCUD
enum: CIB.JA1MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C74:VCIB_DCUF
enum: CIB.JA1MUX 0
enum: CIB.JA3MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC2MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C75:VCIB_DCU3
enum: CIB.JA5MUX 0
enum: CIB.JA7MUX 0
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JC0MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC6MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C76:VCIB_DCU2
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C77:VCIB_DCUG
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C78:VCIB_DCUH
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C79:VCIB_DCUI
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB7MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD6MUX 0
.tile CIB_R70C7:CIB_EFB1
enum: CIB.JA3MUX 0
enum: CIB.JA4MUX 0
enum: CIB.JA5MUX 0
enum: CIB.JA6MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB4MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JB6MUX 0
enum: CIB.JC3MUX 0
enum: CIB.JC4MUX 0
enum: CIB.JC5MUX 0
enum: CIB.JD3MUX 0
enum: CIB.JD4MUX 0
enum: CIB.JD5MUX 0
.tile CIB_R70C80:VCIB_DCU1
enum: CIB.JB1MUX 0
enum: CIB.JB3MUX 0
enum: CIB.JB5MUX 0
enum: CIB.JD0MUX 0
enum: CIB.JD2MUX 0
.tile CIB_R70C87:CIB_PLL3
enum: CIB.JA3MUX 0
enum: CIB.JB3MUX 0
.tile MIB_R0C36:PIOT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
.tile MIB_R0C37:PIOT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R0C38:PIOT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C3:BANKREF0
enum: BANK.VCCIO 3V3
.tile MIB_R0C40:TMID_0
arc: G_TDCC0CLKI G_JTRQPCLKCIB1
.tile MIB_R0C42:PIOT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
.tile MIB_R0C43:PIOT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R0C87:BANKREF1
enum: BANK.VCCIO 3V3
.tile MIB_R10C40:CMUX_UL_0
arc: G_DCS0CLK0 G_VPFN0000
arc: G_ULPCLK0 G_VPFS0000
.tile MIB_R10C41:CMUX_UR_0
arc: G_DCS0CLK1 G_VPFN0000
arc: G_URPCLK0 G_VPFS0000
.tile MIB_R11C0:PICL0
arc: JDIB JPADDIB_PIO
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R12C0:PICL1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R1C36:PICT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C37:PICT1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C38:PICT0
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R1C42:PICT0
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R1C43:PICT1
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R35C0:PICL0
arc: JDIA JPADDIA_PIO
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R35C90:PICR0
arc: JDIB JPADDIB_PIO
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R36C0:PICL1
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOD.HYSTERESIS ON
enum: PIOA.BASE_TYPE INPUT_LVCMOS33
enum: PIOA.HYSTERESIS ON
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R36C90:PICR1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R37C0:PICL2
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R37C90:PICR2
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R38C0:PICL0
arc: JDIB JPADDIB_PIO
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
.tile MIB_R38C90:PICR0
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R39C0:PICL1_DQS0
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOD.HYSTERESIS ON
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R39C90:PICR1_DQS0
enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R40C0:PICL2_DQS1
enum: PIOD.BASE_TYPE INPUT_LVCMOS33
enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33
.tile MIB_R58C30:EBR_SPINE_LL0
arc: G_VPTX0000 G_HPRX0000
.tile MIB_R58C40:CMUX_LL_0
arc: G_DCS1CLK0 G_VPFN0000
arc: G_LLPCLK0 G_VPFS0000
.tile MIB_R58C41:CMUX_LR_0
arc: G_DCS1CLK1 G_VPFN0000
arc: G_LRPCLK0 G_VPFS0000
.tile MIB_R71C1:BANKREF6
enum: BANK.VCCIO 3V3
.tile MIB_R71C4:EFB0_PICB0
unknown: F54B1
unknown: F56B1
unknown: F82B1
unknown: F94B1
.tile MIB_R71C7:EFB3_PICB1
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.BASE_TYPE INPUT_LVCMOS33
enum: PIOB.HYSTERESIS ON
.tile MIB_R71C89:BANKREF3
enum: BANK.VCCIO 3V3
.tile R11C13:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R11C19:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R11C25:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R11C31:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R11C37:PLC2
arc: N1_V02N0101 W3_H06E0103
arc: N1_V02N0601 S3_V06N0303
.tile R11C7:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R12C41:PLC2
arc: N3_V06N0203 S3_V06N0203
.tile R13C34:PLC2
arc: S3_V06S0103 N3_V06S0103
.tile R13C36:PLC2
arc: S3_V06S0103 N3_V06S0003
.tile R15C36:PLC2
arc: S3_V06S0203 N3_V06S0203
.tile R17C37:PLC2
arc: N3_V06N0303 S3_V06N0203
.tile R18C41:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R19C34:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R19C36:PLC2
arc: S3_V06S0103 N3_V06S0103
.tile R21C36:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R23C37:PLC2
arc: N3_V06N0203 S3_V06N0103
.tile R24C41:PLC2
arc: N3_V06N0103 S3_V06N0103
.tile R25C34:PLC2
arc: S3_V06S0303 N3_V06S0203
.tile R25C36:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R27C36:PLC2
arc: S3_V06S0003 N3_V06S0303
.tile R29C37:PLC2
arc: N3_V06N0103 S3_V06N0003
.tile R30C41:PLC2
arc: N3_V06N0103 S3_V06N0003
.tile R31C34:PLC2
arc: S3_V06S0303 N3_V06S0303
.tile R31C36:PLC2
arc: S3_V06S0203 N3_V06S0203
.tile R33C36:PLC2
arc: S1_V02S0301 N3_V06S0003
.tile R35C13:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R35C15:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R35C19:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R35C21:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R35C25:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R35C27:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R35C31:PLC2
arc: E1_H02E0301 V02S0301
arc: E3_H06E0203 W3_H06E0103
.tile R35C32:PLC2
arc: E1_H02E0401 V01N0001
.tile R35C33:PLC2
arc: S1_V02S0101 E1_H01W0100
arc: S1_V02S0301 E1_H01W0100
arc: S1_V02S0501 E1_H01W0100
arc: V00T0000 E1_H02W0001
arc: A0 H00L0000
arc: B0 E1_H01W0100
arc: B1 V00T0000
arc: C0 S1_V02N0601
arc: C1 H00L0100
arc: CLK0 G_HPBX0000
arc: D0 V01S0100
arc: D1 V02N0201
arc: E1_H02E0001 Q0
arc: E1_H02E0201 Q0
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H00L0000 Q0
arc: H00L0100 Q1
arc: LSR0 W1_H02E0301
arc: LSR1 W1_H02E0301
arc: M4 V00B0000
arc: M6 H02E0401
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: S1_V02S0201 Q0
arc: V00B0000 Q6
arc: V01S0000 Q0
arc: V01S0100 Q4
arc: W3_H06W0103 Q1
word: SLICEA.K0.INIT 0110100110010110
word: SLICEA.K1.INIT 1100001100111100
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET SET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.A1MUX 1
.tile R35C34:PLC2
arc: S1_V02S0401 H06E0203
arc: A0 S1_V02N0701
arc: B0 V02S0101
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: E1_H01E0101 Q0
arc: E1_H02E0201 Q0
arc: F0 F0_SLICE
arc: H01W0100 Q0
arc: MUXCLK0 CLK0
arc: S1_V02S0001 Q0
arc: V01S0000 Q0
arc: V01S0100 Q0
word: SLICEA.K0.INIT 1011101110001000
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.C0MUX 1
.tile R35C35:PLC2
arc: H00L0000 H02E0201
arc: H00L0100 S1_V02N0101
arc: S1_V02S0001 W1_H02E0001
arc: S1_V02S0101 V01N0101
arc: S1_V02S0301 V01N0101
arc: S1_V02S0401 E3_H06W0203
arc: S1_V02S0501 H01E0101
arc: V00B0000 V02N0001
arc: V00T0000 W1_H02E0001
arc: A0 S1_V02N0501
arc: A1 S1_V02N0701
arc: A2 S1_V02N0701
arc: A3 S1_V02N0701
arc: A4 V02N0301
arc: A5 V00B0000
arc: B0 V01N0001
arc: B1 V01N0001
arc: B2 V01N0001
arc: B3 V01N0001
arc: B4 H01E0101
arc: B5 S1_V02N0501
arc: C0 S1_V02N0601
arc: C1 S1_V02N0601
arc: C2 S1_V02N0401
arc: C3 S1_V02N0401
arc: C4 V02N0201
arc: C5 S1_V02N0201
arc: CE0 H00L0000
arc: CE1 H00L0000
arc: CLK1 G_HPBX0000
arc: D0 S1_V02N0001
arc: D1 S1_V02N0001
arc: D2 S1_V02N0201
arc: D3 S1_V02N0001
arc: D4 H00L0100
arc: D5 S1_V02N0401
arc: E1_H01E0101 Q1
arc: E1_H02E0201 Q0
arc: E1_H02E0301 Q3
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: LSR1 V00T0000
arc: MUXCLK0 CLK1
arc: MUXCLK1 CLK1
arc: W1_H02W0001 Q2
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEC.MODE RAMW
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.WREMUX WRE
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
.tile R35C36:PLC2
arc: S1_V02S0001 H06E0003
arc: S1_V02S0601 N1_V02S0301
arc: V00T0100 H02W0101
arc: A1 V01N0101
arc: B0 V01N0001
arc: B1 Q1
arc: C0 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 H01E0101
arc: E3_H06E0003 Q0
arc: E3_H06E0103 Q1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H00L0000 Q0
arc: LSR0 V00T0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
word: SLICEA.K0.INIT 1100001100111100
word: SLICEA.K1.INIT 1001100101100110
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.C1MUX 1
.tile R35C37:PLC2
arc: V00B0100 V02S0101
arc: W1_H02W0101 V02S0101
arc: B0 W1_H02E0301
arc: C0 V02N0401
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: F0 F0_SLICE
arc: LSR0 V00B0100
arc: MUXCLK0 CLK0
arc: MUXLSR0 LSR0
arc: N3_V06N0003 Q0
word: SLICEA.K0.INIT 1100001100111100
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R35C3:PLC2
arc: W1_H02W0701 E3_H06W0203
.tile R35C41:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R35C42:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0103 W3_H06E0103
.tile R35C47:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R35C48:PLC2
arc: E3_H06E0103 W3_H06E0003
arc: E3_H06E0203 W3_H06E0103
.tile R35C53:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R35C54:PLC2
arc: E3_H06E0203 W3_H06E0103
arc: E3_H06E0303 W3_H06E0203
.tile R35C59:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R35C60:PLC2
arc: E3_H06E0003 W3_H06E0303
arc: E3_H06E0303 W3_H06E0203
.tile R35C65:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R35C66:PLC2
arc: E3_H06E0003 W3_H06E0303
arc: E3_H06E0103 W3_H06E0003
.tile R35C71:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R35C72:PLC2
arc: E3_H06E0003 W3_H06E0003
arc: E3_H06E0203 W3_H06E0103
.tile R35C77:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R35C78:PLC2
arc: E1_H01E0001 W3_H06E0003
arc: E3_H06E0303 W3_H06E0203
.tile R35C79:PLC2
arc: E3_H06E0203 H01E0001
.tile R35C7:PLC2
arc: E3_H06E0303 W3_H06E0303
.tile R35C83:PLC2
arc: W3_H06W0003 E3_H06W0303
.tile R35C84:PLC2
arc: E1_H02E0601 W3_H06E0303
.tile R35C85:PLC2
arc: E1_H02E0701 W3_H06E0203
.tile R35C86:PLC2
arc: E3_H06E0303 W1_H02E0601
.tile R35C87:PLC2
arc: E1_H02E0701 W1_H02E0701
.tile R35C9:PLC2
arc: W3_H06W0203 E3_H06W0203
.tile R36C31:PLC2
arc: E1_H02E0301 N1_V02S0301
arc: E1_H02E0601 S1_V02N0601
.tile R36C32:PLC2
arc: S1_V02S0401 E1_H01W0000
arc: V00B0000 H02E0601
arc: V00T0100 S1_V02N0701
arc: B0 E1_H01W0100
arc: C0 H00L0000
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: H00L0000 Q0
arc: LSR0 V00B0000
arc: LSR1 H02E0301
arc: M2 V00T0100
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: N1_V01N0001 Q2
word: SLICEA.K0.INIT 1100001100111100
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R36C33:PLC2
arc: E1_H02E0001 N1_V01S0000
arc: E1_H02E0701 W1_H02E0601
arc: H00L0000 H02W0001
arc: H00L0100 H02W0301
arc: N1_V02N0201 H06W0103
arc: V00B0000 V02S0201
arc: V00T0000 H02W0001
arc: V00T0100 H02W0301
arc: A0 H00L0000
arc: A1 H00L0000
arc: A2 V00T0000
arc: A3 V00T0000
arc: A4 E1_H01W0000
arc: A5 V02S0101
arc: B0 V02S0301
arc: B1 V02S0101
arc: B2 V02S0301
arc: B3 V02S0101
arc: B4 V02S0501
arc: B5 H00L0000
arc: C0 H00L0100
arc: C1 H00L0100
arc: C2 H00L0100
arc: C3 H00L0100
arc: C4 V00T0100
arc: C5 V02N0201
arc: CE0 V02S0201
arc: CE1 V02S0201
arc: CLK1 G_HPBX0000
arc: D0 V02S0201
arc: D1 N1_V01S0000
arc: D2 N1_V01S0000
arc: D3 V02S0201
arc: D4 V02N0401
arc: D5 E1_H01W0100
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: H01W0000 Q3
arc: H01W0100 Q2
arc: LSR1 V00B0000
arc: MUXCLK0 CLK1
arc: MUXCLK1 CLK1
arc: V01S0000 Q1
arc: V01S0100 Q0
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEC.MODE RAMW
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.WREMUX WRE
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
.tile R36C34:PLC2
arc: E1_H02E0101 N1_V01S0100
arc: E1_H02E0401 V02S0401
arc: E1_H02E0701 E1_H01W0100
arc: S1_V02S0701 H02E0701
arc: A0 H02E0701
arc: A1 H02E0701
arc: C0 V02N0401
arc: C1 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 V00T0100
arc: D1 N1_V01S0000
arc: E1_H01E0001 Q1
arc: E1_H01E0101 Q0
arc: E1_H02E0001 Q0
arc: E1_H02E0201 Q0
arc: E1_H02E0301 Q1
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0000 Q0
arc: H01W0100 Q1
arc: MUXCLK0 CLK0
arc: V00T0100 Q1
arc: V01S0000 Q1
arc: V01S0100 Q0
arc: W1_H02W0001 Q0
arc: W1_H02W0301 Q1
word: SLICEA.K0.INIT 1111010110100000
word: SLICEA.K1.INIT 1111010110100000
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.B1MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R36C35:PLC2
arc: E1_H02E0101 W1_H02E0001
arc: N1_V02N0201 H01E0001
arc: N1_V02N0301 H01E0101
arc: S1_V02S0701 W1_H02E0701
arc: V00B0100 W1_H02E0701
arc: A0 W1_H02E0701
arc: A2 V00T0000
arc: C0 V02S0401
arc: C2 H02E0401
arc: CLK0 G_HPBX0000
arc: D0 V02N0201
arc: D2 V00B0100
arc: E1_H02E0001 Q2
arc: F0 F0_SLICE
arc: F2 F2_SLICE
arc: H01W0100 Q0
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: N1_V01N0001 Q0
arc: N1_V01N0101 Q0
arc: N1_V02N0001 Q0
arc: V00T0000 Q0
arc: V01S0000 Q2
arc: V01S0100 Q2
word: SLICEA.K0.INIT 1111010110100000
word: SLICEB.K0.INIT 1111000010101010
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
enum: SLICEB.MODE LOGIC
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEB.B0MUX 1
.tile R36C36:PLC2
arc: H00L0000 W1_H02E0201
arc: H00L0100 W1_H02E0301
arc: S1_V02S0001 W1_H02E0001
arc: V00B0000 V02S0001
arc: V00T0000 W1_H02E0001
arc: V00T0100 W1_H02E0301
arc: A0 H00L0000
arc: A1 H00L0000
arc: A2 V00T0000
arc: A3 V00T0000
arc: A4 V00T0000
arc: A5 W1_H02E0701
arc: B0 W1_H02E0101
arc: B1 W1_H02E0101
arc: B2 W1_H02E0101
arc: B3 W1_H02E0101
arc: B4 W1_H02E0101
arc: B5 S1_V02N0501
arc: C0 H00L0100
arc: C1 H00L0100
arc: C2 H00L0100
arc: C3 H00L0100
arc: C4 V00T0100
arc: C5 V01N0101
arc: CE0 H02E0101
arc: CE1 H02E0101
arc: CLK1 G_HPBX0000
arc: D0 V02S0001
arc: D1 V02S0001
arc: D2 V02S0001
arc: D3 V02S0001
arc: D4 V02N0401
arc: D5 H02E0001
arc: E1_H01E0001 Q3
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: LSR1 V00B0000
arc: MUXCLK0 CLK1
arc: MUXCLK1 CLK1
arc: N1_V01N0001 Q0
arc: N1_V01N0101 Q1
arc: W3_H06W0103 Q2
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEC.MODE RAMW
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.WREMUX WRE
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
.tile R36C37:PLC2
arc: N1_V02N0401 H01E0001
.tile R36C38:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R36C41:PLC2
arc: N3_V06N0003 H06E0003
.tile R37C13:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R37C14:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R37C15:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R37C19:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R37C20:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R37C21:PLC2
arc: W3_H06W0103 E3_H06W0103
.tile R37C25:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R37C26:PLC2
arc: W3_H06W0003 E3_H06W0003
.tile R37C27:PLC2
arc: W3_H06W0103 E3_H06W0003
.tile R37C2:PLC2
arc: W1_H02W0701 E3_H06W0203
.tile R37C31:PLC2
arc: E3_H06E0203 W3_H06E0103
arc: H00R0100 H02W0501
arc: V00T0000 V02N0601
arc: CLK0 G_HPBX0000
arc: H00R0000 Q6
arc: LSR0 V00T0000
arc: LSR1 V00T0000
arc: M0 V00B0100
arc: M1 H00R0100
arc: M4 V00T0100
arc: M6 V00B0000
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR2 LSR0
arc: MUXLSR3 LSR1
arc: S1_V02S0001 Q0
arc: V00B0000 Q4
arc: V00B0100 Q7
arc: V00T0100 Q1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R37C32:PLC2
arc: E1_H02E0301 V02N0301
arc: H00L0000 V02N0201
arc: H00R0000 E1_H02W0601
arc: N1_V02N0201 H06W0103
arc: V00B0100 V02N0301
arc: B0 V00T0000
arc: C0 V02S0401
arc: CLK0 G_HPBX0000
arc: D0 E1_H02W0201
arc: E1_H02E0101 Q1
arc: F0 F0_SLICE
arc: LSR0 V00B0100
arc: LSR1 V00B0100
arc: M1 V01S0100
arc: M3 H00L0000
arc: M7 H00R0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR1
arc: MUXLSR1 LSR0
arc: MUXLSR3 LSR1
arc: V00T0000 Q0
arc: V01S0100 Q3
arc: W1_H02W0501 Q7
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 1100001100111100
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R37C33:PLC2
arc: E1_H02E0201 E1_H01W0000
arc: E1_H02E0601 N1_V01S0000
arc: H00L0100 H02E0101
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0401 E1_H01W0000
arc: B0 V00T0000
arc: C0 N1_V01S0100
arc: CLK0 G_HPBX0000
arc: D0 E1_H02W0001
arc: F0 F0_SLICE
arc: H00R0000 Q6
arc: H01W0100 Q1
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M1 H00R0000
arc: M3 H01W0100
arc: M4 V00B0100
arc: M5 H00L0100
arc: M6 V00B0000
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR0
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: N1_V02N0601 Q6
arc: V00B0000 Q4
arc: V00B0100 Q5
arc: V00T0000 Q0
arc: V01S0000 Q3
arc: W3_H06W0003 Q0
word: SLICEA.K0.INIT 1100001100111100
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 0
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 0
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG0.SD 0
enum: SLICED.REG0.REGSET RESET
enum: SLICED.REG0.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R37C34:PLC2
arc: E1_H02E0001 N1_V02S0001
arc: E1_H02E0201 N1_V01S0000
arc: E1_H02E0301 N1_V01S0100
arc: E1_H02E0401 N1_V01S0000
arc: E1_H02E0701 N1_V01S0100
arc: N1_V02N0401 E1_H02W0401
arc: N1_V02N0601 N3_V06S0303
arc: N1_V02N0701 H06E0203
arc: V00T0000 E1_H02W0201
arc: V00T0100 V02S0701
arc: W1_H02W0201 E1_H01W0000
arc: B0 H02W0101
arc: C0 H02E0601
arc: CLK0 G_HPBX0000
arc: D0 Q0
arc: E1_H01E0001 F6
arc: E1_H01E0101 F6
arc: E3_H06E0003 Q0
arc: F0 F0_SLICE
arc: F6 F6_SLICE
arc: H01W0000 F6
arc: LSR0 V00T0100
arc: M4 V00T0000
arc: MUXCLK0 CLK0
arc: MUXCLK2 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR2 LSR0
arc: W1_H02W0601 Q4
word: SLICED.K0.INIT 1111111111111111
word: SLICEA.K0.INIT 1100001100111100
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG0.SD 0
enum: SLICEC.REG0.REGSET RESET
enum: SLICEC.REG0.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_0 _NONE_
enum: SLICED.A0MUX 1
enum: SLICED.B0MUX 1
enum: SLICED.C0MUX 1
enum: SLICED.D0MUX 1
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.A0MUX 1
.tile R37C35:PLC2
arc: E1_H02E0201 N1_V01S0000
arc: E1_H02E0401 H01E0001
arc: E1_H02E0701 V02S0701
arc: H00L0000 H02E0001
arc: N1_V02N0001 E1_H01W0000
arc: N1_V02N0101 H01E0101
arc: N1_V02N0201 E1_H01W0000
arc: N1_V02N0401 N1_V01S0000
arc: N1_V02N0501 E1_H01W0100
arc: N1_V02N0601 N1_V01S0000
arc: N1_V02N0701 E1_H01W0100
arc: V00B0000 N1_V02S0001
arc: V00T0000 H02E0001
arc: V00T0100 H02W0101
arc: A0 E1_H02W0501
arc: A1 E1_H02W0701
arc: A2 E1_H02W0701
arc: A3 E1_H02W0701
arc: A4 H02E0701
arc: A5 V00T0000
arc: B0 N1_V02S0301
arc: B1 N1_V02S0301
arc: B2 N1_V02S0101
arc: B3 N1_V02S0101
arc: B4 N1_V02S0501
arc: B5 H02E0301
arc: C0 N1_V01S0100
arc: C1 N1_V01S0100
arc: C2 N1_V01S0100
arc: C3 N1_V01S0100
arc: C4 H02E0401
arc: C5 H01E0001
arc: CE0 H00L0000
arc: CE1 H00L0000
arc: CLK1 G_HPBX0000
arc: D0 V00T0100
arc: D1 V00T0100
arc: D2 V00T0100
arc: D3 V00T0100
arc: D4 W1_H02E0201
arc: D5 H02E0201
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: F2 F2_SLICE
arc: F3 F3_SLICE
arc: H01W0000 Q3
arc: LSR1 V00B0000
arc: MUXCLK0 CLK1
arc: MUXCLK1 CLK1
arc: W1_H02W0001 Q0
arc: W1_H02W0101 Q1
arc: W3_H06W0103 Q2
word: SLICEC.K0.INIT 0000000000000000
word: SLICEC.K1.INIT 0000000000000000
word: SLICEB.K1.INIT 0000000000000000
word: SLICEB.K0.INIT 0000000000000000
word: SLICEA.K1.INIT 0000000000000000
word: SLICEA.K0.INIT 0000000000000000
enum: SLICEC.MODE RAMW
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_1 _NONE_
enum: SLICEB.MODE DPRAM
enum: SLICEB.CCU2.INJECT1_0 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.MODE DPRAM
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.WREMUX WRE
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 1
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG1.SD 1
enum: SLICEB.REG1.REGSET RESET
enum: SLICEB.REG1.LSRMODE LSR
enum: SLICEB.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX CE
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK1.CLKMUX CLK
.tile R37C36:PLC2
arc: N1_V02N0401 H02E0401
arc: W1_H02W0401 N3_V06S0203
arc: A0 H02E0701
arc: A1 H02E0701
arc: C0 N1_V02S0601
arc: C1 V02N0601
arc: CLK0 G_HPBX0000
arc: D0 H02E0201
arc: D1 V02S0001
arc: E1_H01E0101 Q0
arc: F0 F0_SLICE
arc: F1 F1_SLICE
arc: H01W0000 Q1
arc: H01W0100 Q0
arc: MUXCLK0 CLK0
arc: N1_V01N0101 Q1
arc: V01S0100 Q0
arc: W1_H02W0101 Q1
arc: W1_H02W0201 Q0
word: SLICEA.K1.INIT 1111010110100000
word: SLICEA.K0.INIT 1111010110100000
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 1
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG1.SD 1
enum: SLICEA.REG1.REGSET RESET
enum: SLICEA.REG1.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_1 _NONE_
enum: SLICEA.B1MUX 1
enum: SLICEA.MODE LOGIC
enum: SLICEA.CCU2.INJECT1_0 _NONE_
enum: SLICEA.B0MUX 1
.tile R37C37:PLC2
arc: W1_H02W0501 H01E0101
arc: W1_H02W0701 H01E0101
.tile R37C3:PLC2
arc: S3_V06S0303 E3_H06W0303
.tile R37C40:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R37C46:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R37C52:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R37C58:PLC2
arc: E3_H06E0103 W3_H06E0103
.tile R37C64:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R37C70:PLC2
arc: E3_H06E0203 W3_H06E0203
.tile R37C76:PLC2
arc: E3_H06E0203 W3_H06E0203
.tile R37C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R37C82:PLC2
arc: E1_H01E0101 W3_H06E0203
.tile R37C83:PLC2
arc: E3_H06E0303 H01E0101
.tile R37C8:PLC2
arc: W3_H06W0203 E3_H06W0103
.tile R37C9:PLC2
arc: W3_H06W0303 E3_H06W0203
.tile R38C13:PLC2
arc: E3_H06E0103 W3_H06E0003
.tile R38C19:PLC2
arc: E3_H06E0203 W3_H06E0103
.tile R38C25:PLC2
arc: E3_H06E0303 W3_H06E0203
.tile R38C31:PLC2
arc: E1_H02E0301 S1_V02N0301
arc: E3_H06E0303 W3_H06E0303
arc: N1_V02N0601 S1_V02N0301
arc: V00B0000 V02S0001
arc: V00B0100 S1_V02N0301
arc: CLK0 G_HPBX0000
arc: E1_H02E0201 Q2
arc: LSR0 V00B0100
arc: M2 V00B0000
arc: MUXCLK1 CLK0
arc: MUXLSR1 LSR0
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R38C32:PLC2
arc: N1_V02N0301 H02E0301
arc: V00T0000 H02E0201
arc: CLK0 G_HPBX0000
arc: LSR1 H02E0301
arc: M2 V00T0000
arc: M7 E1_H02W0201
arc: MUXCLK1 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR1 LSR1
arc: MUXLSR3 LSR1
arc: N1_V02N0201 Q2
arc: N1_V02N0701 Q7
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R38C33:PLC2
arc: E1_H02E0201 N1_V01S0000
arc: E1_H02E0301 W1_H02E0301
.tile R38C34:PLC2
arc: CLK0 G_HPBX0000
arc: H00R0100 Q7
arc: LSR0 H02E0301
arc: LSR1 H02E0301
arc: M0 V00B0100
arc: M2 V00T0000
arc: M5 H00R0100
arc: M7 H02E0201
arc: MUXCLK0 CLK0
arc: MUXCLK1 CLK0
arc: MUXCLK2 CLK0
arc: MUXCLK3 CLK0
arc: MUXLSR0 LSR0
arc: MUXLSR1 LSR1
arc: MUXLSR2 LSR1
arc: MUXLSR3 LSR0
arc: V00B0100 Q5
arc: V00T0000 Q0
arc: W1_H02W0201 Q2
enum: SLICEB.GSR DISABLED
enum: SLICEB.REG0.SD 0
enum: SLICEB.REG0.REGSET RESET
enum: SLICEB.REG0.LSRMODE LSR
enum: SLICEB.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEA.GSR DISABLED
enum: SLICEA.REG0.SD 0
enum: SLICEA.REG0.REGSET RESET
enum: SLICEA.REG0.LSRMODE LSR
enum: SLICEA.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICEC.GSR DISABLED
enum: SLICEC.REG1.SD 0
enum: SLICEC.REG1.REGSET RESET
enum: SLICEC.REG1.LSRMODE LSR
enum: SLICEC.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
enum: SLICED.GSR DISABLED
enum: SLICED.REG1.SD 0
enum: SLICED.REG1.REGSET RESET
enum: SLICED.REG1.LSRMODE LSR
enum: SLICED.CEMUX 1
enum: LSR0.SRMODE LSR_OVER_CE
enum: LSR0.LSRMUX LSR
enum: LSR1.SRMODE LSR_OVER_CE
enum: LSR1.LSRMUX LSR
enum: CLK0.CLKMUX CLK
.tile R38C36:PLC2
arc: N1_V02N0501 N1_V01S0100
arc: N1_V02N0601 H02W0601
.tile R38C37:PLC2
arc: W1_H02W0601 W3_H06E0303
.tile R38C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R3C36:PLC2
arc: S3_V06S0103 N1_V02S0201
.tile R3C37:PLC2
arc: N1_V02N0501 S3_V06N0303
.tile R40C13:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R40C19:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R40C25:PLC2
arc: E3_H06E0003 W3_H06E0003
.tile R40C31:PLC2
arc: N1_V02N0301 W3_H06E0003
.tile R40C3:PLC2
arc: W1_H02W0501 V06S0303
.tile R40C7:PLC2
arc: E3_H06E0003 W3_H06E0303
.tile R4C41:PLC2
arc: N3_V06N0203 S1_V02N0401
.tile R51C82:PLC2
word: SLICED.K1.INIT 0000000000000000
enum: SLICED.MODE LOGIC
enum: SLICED.CCU2.INJECT1_1 _NONE_
enum: SLICED.A1MUX 1
enum: SLICED.B1MUX 1
enum: SLICED.C1MUX 1
enum: SLICED.D1MUX 1
.tile R6C41:PLC2
arc: N1_V02N0401 S3_V06N0203
.tile R7C34:PLC2
arc: S3_V06S0103 N3_V06S0003
.tile R7C36:PLC2
arc: S3_V06S0003 N3_V06S0003
.tile R7C37:PLC2
arc: N3_V06N0203 S1_V02N0401
.tile R9C36:PLC2
arc: S3_V06S0203 N3_V06S0103
.tile R9C37:PLC2
arc: N1_V02N0401 S1_V02N0101
arc: N3_V06N0303 S1_V02N0601
.tile TAP_R35C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R36C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R37C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
.tile TAP_R38C31:TAP_DRIVE
arc: R_HPBX0000 G_VPTX0000
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