micheleandClaude Sonnet 5
ee5a68f6e6
EXP-0053: sdram_cdc_bridge.v decouples the SDRAM clock (115.2MHz, real value derived from the board's own existing PLL VCO=576MHz, verified via ecppll) from the 64MHz compute domain. Isolated: 137/137 tests, 0 errors, but real measured speedup is only 1.095x (not the naive 1.8x clock-ratio estimate) -- the CDC handshake's own synchronizer round-trip is a fixed per-transaction tax. EXP-0054: sdram_controller_openrow.v implements the page-hit/ keep-row-open optimization sdram_controller.v's own header had always deferred. weight_prefetch_engine_wide.v's real production traffic is strictly sequential per job and mostly stays within one SDRAM row -- closing/reopening it every tile (today's fixed auto-precharge policy) wastes tRP+tRCD for no reason. Isolated: 154/154 tests, 0 errors, 0 protocol violations (including the new refresh-while-row-open hazard, fixed via an explicit precharge-before-refresh path). Real measured speedup on the actual sequential access pattern: 1.141x. EXP-0055: composed both, then integrated into the real D-Stress benchmark (N=4/N=8, 256/256 bit-exact in every config). Result: open-row ALONE gives a real, consistent ~5% cycle-count improvement (47445/47468 vs baseline 49927/49909). CDC alone is a real ~8% REGRESSION. Combined is still a ~4% regression -- the CDC's fixed tax is paid on every transaction regardless of row-hit, and real D-Stress traffic interleaves weight-fetch/activation-result access far more than the isolated same-row test exercised, so open-row's real saving doesn't offset it. Decision: do not adopt the CDC approach; open-row alone is the disclosed, real win worth considering for production next, pending an explicit go-ahead (not applied to the real board top in this commit -- all additive, existing production RTL untouched). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
461 lines
20 KiB
Verilog
461 lines
20 KiB
Verilog
`timescale 1ns/1ps
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// ============================================================
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// EXP-0054 -- open-row (page-hit) SDR SDRAM controller, forked from
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// sdram_controller.v (STEP16). Implements the "page-hit/keep-row-open
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// optimization" that sdram_controller.v's own header explicitly
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// deferred:
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// "ALWAYS uses auto-precharge... NOT the fastest possible design
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// (no page-hit/keep-row-open optimization, unlike psram_
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// controller.v's own real page-mode), but it is trivially correct"
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//
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// MOTIVATION: weight_prefetch_engine_wide.v (real production traffic,
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// instantiated by nms_dataflow_core_sdram.v, PREFETCH_DISTANCE=8)
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// already issues a stream of STRICTLY SEQUENTIAL tile addresses per
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// job. With ROW_BITS=13/COL_BITS=10 (AS4C32M16SA: 1024 columns/row,
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// 4 words/tile at 16-bit words -- see sdram_controller.v's own TILE
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// comment), a single row holds 256 consecutive tiles before crossing
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// a row boundary -- most real jobs' weight streams never leave the
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// row they started in. Closing and reopening that row on EVERY single
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// tile (today's fixed auto-precharge policy) pays tRP+tRCD twice per
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// transaction for no reason when the next transaction is going to hit
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// the SAME row anyway.
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//
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// POLICY: never auto-precharge (A10=0 on every READ/WRITE). Track the
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// single currently-open bank+row (this controller has always modeled
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// "one transaction in flight" -- this experiment keeps that same
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// single-open-row scope, not per-bank tracking across multiple
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// simultaneously-open banks, matching the project's own established
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// risk posture). On the NEXT request (evaluated in S_IDLE, exactly
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// where every prior request was already evaluated):
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// - SAME bank+row as currently open ("row hit"): skip ACTIVATE
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// entirely -- issue READ/WRITE directly, saving tRCD.
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// - DIFFERENT bank+row while a row IS open ("row miss"): issue an
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// explicit PRECHARGE first (this controller no longer gets that
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// for free via auto-precharge), wait tRP, THEN activate the new
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// row exactly as before -- same total cost as today's design,
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// just paid on-demand instead of unconditionally after every
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// transaction.
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// - no row open (e.g. right after reset/refresh): activate directly,
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// unchanged from today.
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//
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// REFRESH INTERACTION (the one real correctness hazard this policy
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// introduces, absent from the original always-precharged design):
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// JEDEC AUTO REFRESH requires ALL banks precharged first. The
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// original S_IDLE refresh branch's own comment ("no row is ever left
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// open between transactions... so we can refresh immediately") is no
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// longer true under this policy -- fixed here by precharging first
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// (S_PRE_THEN_REF_WAIT) whenever row_open is set at the moment
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// refresh comes due, before issuing AUTO REFRESH exactly as before.
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//
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// WRITE RECOVERY (tWR): the original design folded tWR into its
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// always-paid post-burst precharge wait ("T_RP + 1'b1 // tWR folded
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// in conservatively"). This design no longer precharges after every
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// write, so tWR is now paid explicitly and alone (T_WR=2 CLK, real
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// AS4C32M16SA datasheet value, same explicit-CLK-units treatment as
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// T_MRD) via a new S_WRITE_RECOVERY_WAIT state, before the row-open
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// path returns to S_IDLE and can accept a same-row follow-on command.
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//
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// DISCLOSED, NOT INDEPENDENTLY VERIFIED: read-burst-end -> next
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// command (read-to-read or read-to-write, same open row) has NO extra
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// wait beyond the existing 1-cycle-minimum S_IDLE turnaround, on the
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// reasoning that JEDEC SDR SDRAM page-mode reads support back-to-back
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// column access with no additional bubble. sdram_model.v (this
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// project's own real-command-sequence checker) does NOT itself assert
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// tCCD/tRTW/tWTR -- it only checks ACTIVATE-while-active, tRP, tRAS
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// (min), refresh spacing, and access-with-no-active-row (see its own
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// VIOLATION messages). tb_sdram_controller_openrow.v exercises
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// read-after-read and write-after-read same-row sequences explicitly
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// and checks DATA correctness, but a genuine read-to-write DQ bus
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// turnaround hazard would not be caught by sdram_model.v itself if
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// present -- flagged here exactly as this project's own convention
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// requires, not silently assumed safe.
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//
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// Every timing constant, the mrs_value encoding, the req_pending
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// unconditional-latch fix, and the address decomposition are carried
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// over UNCHANGED from sdram_controller.v -- only the state machine's
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// precharge policy and the two new wait states are new.
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// ============================================================
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module sdram_controller_openrow #(
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parameter CLK_FREQ_MHZ = 64,
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parameter BURST_LEN = 4, // 1, 4, or 8 -- same real scope as sdram_controller.v (see its own mrs_value)
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parameter ROW_BITS = 13,
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parameter COL_BITS = 10,
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parameter BANK_BITS = 2,
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parameter ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire [16*BURST_LEN-1:0] wdata,
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input wire [2*BURST_LEN-1:0] wmask,
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output reg [16*BURST_LEN-1:0] rdata,
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output reg ready,
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output reg busy,
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output reg sdram_cke,
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output reg sdram_cs_n,
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output reg sdram_ras_n,
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output reg sdram_cas_n,
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output reg sdram_we_n,
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output reg [1:0] sdram_ba,
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output reg [ROW_BITS-1:0] sdram_a,
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inout wire [15:0] sdram_dq,
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output reg [1:0] sdram_dqm
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);
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localparam BURST_IDXW = (BURST_LEN <= 1) ? 1 : $clog2(BURST_LEN);
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initial if (ADDR_WIDTH != BANK_BITS + ROW_BITS + COL_BITS) begin
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$display("FATAL sdram_controller_openrow: ADDR_WIDTH=%0d != BANK_BITS(%0d)+ROW_BITS(%0d)+COL_BITS(%0d)=%0d",
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ADDR_WIDTH, BANK_BITS, ROW_BITS, COL_BITS, BANK_BITS+ROW_BITS+COL_BITS);
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$finish;
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end
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function integer ns_to_cycles;
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input integer ns;
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begin
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ns_to_cycles = (ns * CLK_FREQ_MHZ + 999) / 1000;
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end
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endfunction
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localparam T_RCD = ns_to_cycles(15);
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localparam T_RP = ns_to_cycles(15);
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localparam T_MRD = 2;
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localparam T_WR = 2; // real AS4C32M16SA datasheet value, explicit CLK units (same treatment as T_MRD)
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localparam T_INIT_US= 200;
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localparam T_INIT = T_INIT_US * CLK_FREQ_MHZ;
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localparam CAS_LATENCY = 3;
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localparam T_REFI = ns_to_cycles(64000000 / (1 << ROW_BITS) + 1);
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localparam CNTW = $clog2((T_INIT>T_REFI ? T_INIT : T_REFI) + 1);
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function [CNTW-1:0] T_RC_MINUS1;
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localparam integer T_RC = ns_to_cycles(65);
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begin
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T_RC_MINUS1 = T_RC[CNTW-1:0] - 1'b1;
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end
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endfunction
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localparam
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S_INIT_WAIT = 5'd0,
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S_INIT_PRE_WAIT = 5'd2,
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S_INIT_REF = 5'd3,
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S_INIT_REF_WAIT = 5'd4,
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S_INIT_MRS_WAIT = 5'd6,
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S_IDLE = 5'd7,
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S_REFRESH_WAIT = 5'd9,
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S_ACTIVATE_WAIT = 5'd11,
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S_CAS_WAIT = 5'd13,
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S_BURST_READ = 5'd14,
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S_BURST_WRITE = 5'd15,
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S_PRE_THEN_ACT_WAIT = 5'd17,
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S_PRE_THEN_REF_WAIT = 5'd18,
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S_WRITE_RECOVERY_WAIT= 5'd19;
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reg [4:0] state;
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reg [CNTW-1:0] wait_cnt;
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reg [3:0] init_ref_cnt;
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reg [CNTW-1:0] refresh_timer;
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reg [BURST_IDXW-1:0] burst_idx;
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reg req_wr_reg;
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reg [BANK_BITS-1:0] req_bank_reg;
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reg [ROW_BITS-1:0] req_row_reg;
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reg [COL_BITS-1:0] req_col_reg;
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reg [16*BURST_LEN-1:0] wdata_reg;
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reg [2*BURST_LEN-1:0] wmask_reg;
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// ---- open-row tracking (new vs sdram_controller.v) ----
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reg row_open;
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reg [BANK_BITS-1:0] open_bank;
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reg [ROW_BITS-1:0] open_row;
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wire [BANK_BITS-1:0] addr_bank = addr[ADDR_WIDTH-1 -: BANK_BITS];
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wire [ROW_BITS-1:0] addr_row = addr[ADDR_WIDTH-BANK_BITS-1 -: ROW_BITS];
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wire [COL_BITS-1:0] addr_col = addr[COL_BITS-1:0];
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reg req_pending;
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wire eff_wr = req ? wr : req_wr_reg;
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wire [BANK_BITS-1:0] eff_bank = req ? addr_bank : req_bank_reg;
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wire [ROW_BITS-1:0] eff_row = req ? addr_row : req_row_reg;
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wire [COL_BITS-1:0] eff_col = req ? addr_col : req_col_reg;
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wire [16*BURST_LEN-1:0] eff_wdata = req ? wdata : wdata_reg;
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wire [2*BURST_LEN-1:0] eff_wmask = req ? wmask : wmask_reg;
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reg dq_out_en;
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reg [15:0] dq_out;
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assign sdram_dq = dq_out_en ? dq_out : 16'hzzzz;
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function [ROW_BITS-1:0] mrs_value;
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input integer burst_len;
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reg [2:0] bl_code;
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reg [ROW_BITS-1:0] v;
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begin
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bl_code = (burst_len==1) ? 3'b000 :
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(burst_len==2) ? 3'b001 :
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(burst_len==4) ? 3'b010 :
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(burst_len==8) ? 3'b011 : 3'b111;
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v = {ROW_BITS{1'b0}};
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v[6:4] = 3'b011;
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v[3] = 1'b0;
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v[2:0] = bl_code;
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mrs_value = v;
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end
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endfunction
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always @(posedge clk) begin
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if (rst) begin
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state <= S_INIT_WAIT;
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wait_cnt <= T_INIT[CNTW-1:0];
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init_ref_cnt <= 4'd0;
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refresh_timer <= T_REFI[CNTW-1:0];
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sdram_cke <= 1'b1;
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sdram_cs_n <= 1'b1;
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sdram_ras_n <= 1'b1;
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sdram_cas_n <= 1'b1;
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sdram_we_n <= 1'b1;
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sdram_ba <= 2'b00;
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sdram_a <= {ROW_BITS{1'b0}};
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sdram_dqm <= 2'b00;
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dq_out_en <= 1'b0;
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ready <= 1'b0;
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busy <= 1'b1;
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req_pending <= 1'b0;
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row_open <= 1'b0;
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open_bank <= {BANK_BITS{1'b0}};
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open_row <= {ROW_BITS{1'b0}};
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end else begin
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sdram_cs_n <= 1'b0;
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sdram_ras_n <= 1'b1;
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sdram_cas_n <= 1'b1;
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sdram_we_n <= 1'b1;
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ready <= 1'b0;
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dq_out_en <= 1'b0;
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sdram_dqm <= 2'b00;
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if (refresh_timer != 0) refresh_timer <= refresh_timer - 1'b1;
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if (req) begin
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req_wr_reg <= wr;
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req_bank_reg <= addr_bank;
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req_row_reg <= addr_row;
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req_col_reg <= addr_col;
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wdata_reg <= wdata;
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wmask_reg <= wmask;
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req_pending <= 1'b1;
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end
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case (state)
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S_INIT_WAIT: begin
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busy <= 1'b1;
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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sdram_ras_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_a[10] <= 1'b1;
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wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
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state <= S_INIT_PRE_WAIT;
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end
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end
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S_INIT_PRE_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else state <= S_INIT_REF;
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end
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S_INIT_REF: begin
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0;
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wait_cnt <= T_RC_MINUS1();
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state <= S_INIT_REF_WAIT;
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end
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S_INIT_REF_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else if (init_ref_cnt < 4'd7) begin
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init_ref_cnt <= init_ref_cnt + 1'b1;
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state <= S_INIT_REF;
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end else begin
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_ba <= 2'b00;
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sdram_a <= mrs_value(BURST_LEN);
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wait_cnt <= T_MRD[CNTW-1:0] - 1'b1;
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state <= S_INIT_MRS_WAIT;
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end
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end
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S_INIT_MRS_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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busy <= 1'b0;
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state <= S_IDLE;
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end
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end
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S_IDLE: begin
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busy <= 1'b0;
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if (refresh_timer == 0) begin
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busy <= 1'b1;
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if (row_open) begin
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// JEDEC: all banks must be precharged before
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// AUTO REFRESH -- no longer free/automatic
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// under the open-row policy (see header).
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sdram_ras_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_ba <= open_bank;
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sdram_a[10] <= 1'b1;
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row_open <= 1'b0;
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wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
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state <= S_PRE_THEN_REF_WAIT;
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end else begin
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0;
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wait_cnt <= T_RC_MINUS1();
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refresh_timer <= T_REFI[CNTW-1:0];
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state <= S_REFRESH_WAIT;
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end
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end else if (req || req_pending) begin
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busy <= 1'b1;
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req_wr_reg <= eff_wr;
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req_bank_reg <= eff_bank;
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req_row_reg <= eff_row;
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req_col_reg <= eff_col;
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wdata_reg <= eff_wdata;
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wmask_reg <= eff_wmask;
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req_pending <= 1'b0;
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if (row_open && eff_bank == open_bank && eff_row == open_row) begin
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// ROW HIT: skip ACTIVATE entirely, saves tRCD.
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burst_idx <= {BURST_IDXW{1'b0}};
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sdram_cas_n <= 1'b0;
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sdram_we_n <= eff_wr ? 1'b0 : 1'b1;
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sdram_ba <= eff_bank;
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sdram_a <= {{(ROW_BITS-11){1'b0}}, 1'b0, {(10-COL_BITS){1'b0}}, eff_col}; // A10=0: no auto-precharge
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if (eff_wr) begin
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dq_out_en <= 1'b1;
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dq_out <= eff_wdata[15:0];
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sdram_dqm <= eff_wmask[1:0];
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state <= S_BURST_WRITE;
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end else begin
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wait_cnt <= CAS_LATENCY[CNTW-1:0];
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state <= S_CAS_WAIT;
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end
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end else if (row_open) begin
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// ROW MISS, a different row is open: precharge
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// it first (paid on-demand, same total cost as
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// today's unconditional auto-precharge, just
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// deferred until actually needed).
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sdram_ras_n <= 1'b0; sdram_we_n <= 1'b0;
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sdram_ba <= open_bank;
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sdram_a[10] <= 1'b1;
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row_open <= 1'b0;
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wait_cnt <= T_RP[CNTW-1:0] - 1'b1;
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state <= S_PRE_THEN_ACT_WAIT;
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end else begin
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// no row open at all: activate directly.
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sdram_ras_n <= 1'b0;
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sdram_ba <= eff_bank;
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sdram_a <= eff_row;
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wait_cnt <= T_RCD[CNTW-1:0] - 1'b1;
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state <= S_ACTIVATE_WAIT;
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end
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end
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end
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S_PRE_THEN_REF_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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sdram_ras_n <= 1'b0; sdram_cas_n <= 1'b0;
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wait_cnt <= T_RC_MINUS1();
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refresh_timer <= T_REFI[CNTW-1:0];
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state <= S_REFRESH_WAIT;
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end
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end
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S_PRE_THEN_ACT_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else begin
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sdram_ras_n <= 1'b0;
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sdram_ba <= req_bank_reg;
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sdram_a <= req_row_reg;
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wait_cnt <= T_RCD[CNTW-1:0] - 1'b1;
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state <= S_ACTIVATE_WAIT;
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end
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end
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S_REFRESH_WAIT: begin
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if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
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else state <= S_IDLE;
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end
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S_ACTIVATE_WAIT: begin
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if (wait_cnt != 0) begin
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wait_cnt <= wait_cnt - 1'b1;
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end else begin
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sdram_cas_n <= 1'b0;
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sdram_we_n <= req_wr_reg ? 1'b0 : 1'b1;
|
|
sdram_ba <= req_bank_reg;
|
|
sdram_a <= {{(ROW_BITS-11){1'b0}}, 1'b0, {(10-COL_BITS){1'b0}}, req_col_reg}; // A10=0
|
|
burst_idx <= {BURST_IDXW{1'b0}};
|
|
row_open <= 1'b1;
|
|
open_bank <= req_bank_reg;
|
|
open_row <= req_row_reg;
|
|
if (req_wr_reg) begin
|
|
dq_out_en <= 1'b1;
|
|
dq_out <= wdata_reg[15:0];
|
|
sdram_dqm <= wmask_reg[1:0];
|
|
state <= S_BURST_WRITE;
|
|
end else begin
|
|
wait_cnt <= CAS_LATENCY[CNTW-1:0];
|
|
state <= S_CAS_WAIT;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_CAS_WAIT: begin
|
|
if (wait_cnt != 0) begin
|
|
wait_cnt <= wait_cnt - 1'b1;
|
|
end else begin
|
|
rdata[0 +: 16] <= sdram_dq;
|
|
if (BURST_LEN == 1) begin
|
|
ready <= 1'b1;
|
|
state <= S_IDLE; // row stays open, no precharge
|
|
end else begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
state <= S_BURST_READ;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_BURST_READ: begin
|
|
rdata[burst_idx*16 +: 16] <= sdram_dq;
|
|
if (burst_idx == BURST_LEN[BURST_IDXW-1:0] - 1'b1) begin
|
|
ready <= 1'b1;
|
|
state <= S_IDLE; // row stays open, no precharge
|
|
end else begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
end
|
|
end
|
|
|
|
S_BURST_WRITE: begin
|
|
if (burst_idx < BURST_LEN[BURST_IDXW-1:0] - 1'b1) begin
|
|
burst_idx <= burst_idx + 1'b1;
|
|
dq_out_en <= 1'b1;
|
|
dq_out <= wdata_reg[(burst_idx+1'b1)*16 +: 16];
|
|
sdram_dqm <= wmask_reg[(burst_idx+1'b1)*2 +: 2];
|
|
end else begin
|
|
ready <= 1'b1;
|
|
// tWR now paid alone (no longer folded with tRP,
|
|
// since we no longer precharge unconditionally --
|
|
// see header).
|
|
wait_cnt <= T_WR[CNTW-1:0] - 1'b1;
|
|
state <= S_WRITE_RECOVERY_WAIT;
|
|
end
|
|
end
|
|
|
|
S_WRITE_RECOVERY_WAIT: begin
|
|
if (wait_cnt != 0) wait_cnt <= wait_cnt - 1'b1;
|
|
else state <= S_IDLE; // row stays open, no precharge
|
|
end
|
|
|
|
default: state <= S_IDLE;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|