micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
452 lines
12 KiB
Verilog
452 lines
12 KiB
Verilog
`timescale 1ns/1ps
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module tb;
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parameter DATA_WIDTH = 8;
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parameter N_INPUTS = 32;
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parameter PARALLEL = 8;
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parameter ACC_WIDTH = 32;
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reg clk;
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reg rst;
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reg start;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] w_bus;
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reg signed [DATA_WIDTH-1:0] bias;
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reg [1:0] activation;
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reg [15:0] n_inputs_real;
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wire signed [DATA_WIDTH-1:0] y;
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wire busy;
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wire done;
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integer i;
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integer errors;
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localparam ACT_NONE = 2'd0;
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localparam ACT_RELU = 2'd1;
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neuron_parallel #(
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) dut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.w_bus(w_bus),
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.bias(bias),
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.activation(activation),
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.n_inputs_real(n_inputs_real),
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.y(y),
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.busy(busy),
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.done(done)
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);
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// Clock: 10 ns
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// ------------------------------------------------------------
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// Start neuron and wait for completion
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// ------------------------------------------------------------
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task run_neuron;
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begin
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@(posedge clk);
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start = 1;
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@(posedge clk);
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start = 0;
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wait(done == 1);
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@(posedge clk);
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end
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endtask
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// ------------------------------------------------------------
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// TEST 1
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//
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// Diverse vector:
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//
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// x0 = 3 w0 = 2 -> 6
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// x1 = 4 w1 = -1 -> -4
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// x2 = 2 w2 = 1 -> 2
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//
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// bias = 1
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//
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// total = 6 - 4 + 2 + 1 = 5
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// ------------------------------------------------------------
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task test_1;
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begin
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$display("");
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$display("TEST 1: DIVERSE VECTOR");
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x_bus = 0;
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w_bus = 0;
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bias = 8'sd1;
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x_bus[0*DATA_WIDTH +: DATA_WIDTH] = 8'sd3;
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w_bus[0*DATA_WIDTH +: DATA_WIDTH] = 8'sd2;
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x_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd4;
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w_bus[1*DATA_WIDTH +: DATA_WIDTH] = -8'sd1;
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x_bus[2*DATA_WIDTH +: DATA_WIDTH] = 8'sd2;
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w_bus[2*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 5");
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if (y !== 8'sd5) begin
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$display("FAIL - TEST 1");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 1");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 2
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//
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// All products negative.
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// ReLU must force output to zero.
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// ------------------------------------------------------------
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task test_2;
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begin
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$display("");
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$display("TEST 2: RELU");
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1;
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 0");
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if (y !== 8'sd0) begin
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$display("FAIL - TEST 2");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 2");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 3
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//
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// Large positive result.
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// Must saturate to +127 (INT8).
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// ------------------------------------------------------------
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task test_3;
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begin
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$display("");
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$display("TEST 3: POSITIVE SATURATION");
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd100;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd2;
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 127");
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if (y !== 8'sd127) begin
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$display("FAIL - TEST 3");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 3");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 4
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//
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// Mixed positive/negative products.
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//
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// 16 x (2 * 1) = 32
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// 16 x (-1 * 1) = -16
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// sum = 16
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// bias = -16
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//
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// total = 0 -> ReLU boundary -> 0
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// ------------------------------------------------------------
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task test_4;
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begin
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$display("");
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$display("TEST 4: MIXED VALUES + NEGATIVE BIAS");
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x_bus = 0;
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w_bus = 0;
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bias = -8'sd16;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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if ((i % 2) == 0) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd2;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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end
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else begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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end
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = 0");
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if (y !== 8'sd0) begin
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$display("FAIL - TEST 4");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 4");
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end
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end
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endtask
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// ------------------------------------------------------------
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// TEST 5: activation=ACT_NONE (linear)
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//
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// Same "all products negative" vector as TEST 2, where ReLU
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// forces y=0. Under ACT_NONE the negative result must pass
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// through unclamped instead.
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//
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// 4 lanes active: x=1, w=-1 -> -4 total, bias=-3 -> -7
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// ------------------------------------------------------------
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task test_5;
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begin
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$display("");
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$display("TEST 5: ACT_NONE (linear, negative passes through)");
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x_bus = 0;
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w_bus = 0;
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bias = -8'sd3;
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activation = ACT_NONE;
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for (i = 0; i < 4; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1;
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = -7");
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if (y !== -8'sd7) begin
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$display("FAIL - TEST 5");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 5");
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end
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activation = ACT_RELU;
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end
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endtask
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// ------------------------------------------------------------
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// TEST 6: activation=ACT_NONE, negative saturation
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//
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// Large negative accumulator must saturate to -128, not wrap.
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// ------------------------------------------------------------
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task test_6;
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begin
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$display("");
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$display("TEST 6: ACT_NONE, NEGATIVE SATURATION");
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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activation = ACT_NONE;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd100;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd2;
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end
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run_neuron;
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$display("RTL = %0d", y);
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$display("EXPECTED = -128");
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if (y !== -8'sd128) begin
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$display("FAIL - TEST 6");
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errors = errors + 1;
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end
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else begin
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$display("PASS - TEST 6");
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end
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activation = ACT_RELU;
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end
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endtask
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// ------------------------------------------------------------
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// TEST 7: n_inputs_real < N_INPUTS (runtime early termination)
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//
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// Only lanes 0..7 carry real data (x=1, w=1 -> 8 total); lanes
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// 8..31 are deliberately loaded with garbage (x=99, w=99) that
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// would swamp the sum if read. n_inputs_real=8 with PARALLEL=8
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// means groups_real=1 group instead of the full GROUPS=4 --
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// both the correct RESULT (garbage lanes never read) and a
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// shorter RUNTIME (fewer cycles than a full-width run) are
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// checked.
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// ------------------------------------------------------------
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integer t_start, t_done;
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integer cycles_full, cycles_reduced;
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task test_7;
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reg pass_7;
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begin
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$display("");
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$display("TEST 7: n_inputs_real < N_INPUTS (early termination)");
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pass_7 = 1;
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// -- baseline: full-width run (32 lanes, x=1 w=1 -> 32) --
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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activation = ACT_RELU;
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n_inputs_real = N_INPUTS;
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for (i = 0; i < N_INPUTS; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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end
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t_start = $time;
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run_neuron;
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t_done = $time;
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cycles_full = (t_done - t_start) / 10;
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if (y !== 8'sd32) begin
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$display(" FAIL: full-width result = %0d, expected 32", y);
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errors = errors + 1;
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pass_7 = 0;
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end
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// -- reduced: only 8 real lanes, rest garbage --
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x_bus = 0;
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w_bus = 0;
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for (i = 0; i < 8; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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end
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for (i = 8; i < N_INPUTS; i = i + 1) begin
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd99;
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w_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd99;
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end
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n_inputs_real = 16'd8;
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t_start = $time;
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run_neuron;
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t_done = $time;
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cycles_reduced = (t_done - t_start) / 10;
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$display(" full-width : y=%0d, %0d cycles", 32, cycles_full);
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$display(" reduced : y=%0d, %0d cycles (expected y=8)", y, cycles_reduced);
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if (y !== 8'sd8) begin
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$display(" FAIL: reduced-width result = %0d, expected 8 (garbage lanes must not be read)", y);
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errors = errors + 1;
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pass_7 = 0;
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end
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if (cycles_reduced >= cycles_full) begin
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$display(" FAIL: reduced run (%0d cycles) did not complete faster than full-width run (%0d cycles)", cycles_reduced, cycles_full);
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errors = errors + 1;
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pass_7 = 0;
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end
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n_inputs_real = N_INPUTS;
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if (pass_7)
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$display("PASS - TEST 7");
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else
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$display("FAIL - TEST 7");
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end
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endtask
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// ------------------------------------------------------------
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// MAIN
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// ------------------------------------------------------------
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initial begin
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$dumpfile("sim/neuron_parallel.vcd");
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$dumpvars(0, tb);
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rst = 1;
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start = 0;
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x_bus = 0;
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w_bus = 0;
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bias = 0;
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activation = ACT_RELU;
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n_inputs_real = N_INPUTS;
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errors = 0;
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repeat (2) @(posedge clk);
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rst = 0;
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$display("");
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$display("==============================");
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$display("NEURON_PARALLEL TESTBENCH (INT8)");
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$display("==============================");
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test_1;
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test_2;
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test_3;
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test_4;
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test_5;
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test_6;
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test_7;
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$display("");
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$display("==============================");
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if (errors == 0) begin
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$display("ALL TESTS PASSED");
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end
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else begin
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$display("FAILURES = %0d", errors);
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end
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$display("==============================");
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$display("");
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$finish;
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end
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endmodule
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