micheleandClaude Sonnet 5
97a21be240
Adds FPGA-exclusive access to the onboard W25Q128JV SPI NOR flash for weights/bias/network persistence, layered as spi_flash_master (raw SPI, USRMCLK-driven) -> flash_copy_engine (flash<->PSRAM streaming, erase- before-write, Page Program loop) -> flash_slot_manager (16-slot catalog with CRC32), exposed via 8 new SPI opcodes (0x40-0x47). Fixes two pre-existing bugs found during bring-up: a psram_controller.v request lost during power-up, and a one-cycle-pulse race in the PSRAM arbiter request handshake. Full simulation + real Yosys/nextpnr-ecp5 synthesis verification (0 errors, Fmax 66.68MHz) in WORKLOG.md and docs/FPGA-Neural-Flash-Subsystem-Verification.md. Also updates docs/pinout to reflect the 56-signal real .lpf (3 new flash pins) and documents the WRITE_RAM/READ_RAM host backpressure risk found while testing this subsystem. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
231 lines
12 KiB
Plaintext
231 lines
12 KiB
Plaintext
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 308/43848 0%
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Info: logic LUTs: 284/43848 0%
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Info: carry LUTs: 24/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 184/43848 0%
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Info: Packing IOs..
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Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
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Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
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Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
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Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
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Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
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Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
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Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
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Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
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Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
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Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
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Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
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Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
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Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
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Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
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Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
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Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 92 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x6432f0fa
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Info: Device utilisation:
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Info: TRELLIS_IO: 107/ 245 43%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 184/ 43848 0%
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Info: TRELLIS_COMB: 334/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 337 cells, random placement wirelen = 30937.
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Info: at initial placer iter 0, wirelen = 7548
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Info: at initial placer iter 1, wirelen = 7178
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Info: at initial placer iter 2, wirelen = 6972
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Info: at initial placer iter 3, wirelen = 6965
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Info: Running main analytical placer, max placement attempts per cell = 48984.
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Info: at iteration #1, type ALL: wirelen solved = 6930, spread = 7503, legal = 7561; time = 0.01s
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Info: HeAP Placer Time: 0.03s
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Info: of which solving equations: 0.01s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 31, wirelen = 7561
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Info: at iteration #5: temp = 0.000000, timing cost = 59, wirelen = 6348
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Info: at iteration #9: temp = 0.000000, timing cost = 101, wirelen = 6395
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Info: SA placement time 0.06s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 236.80 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.98 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.40 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 8277, 8435) |******
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Info: [ 8435, 8593) |***********
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Info: [ 8593, 8751) |*****************
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Info: [ 8751, 8909) |***************
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Info: [ 8909, 9067) |******************
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Info: [ 9067, 9225) |****************************************
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Info: [ 9225, 9383) |************************************
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Info: [ 9383, 9541) |**********************************************
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Info: [ 9541, 9699) |**********************
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Info: [ 9699, 9857) |**********************
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Info: [ 9857, 10015) |************************
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Info: [ 10015, 10173) |*****
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Info: [ 10173, 10331) |**********
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Info: [ 10331, 10489) |*******
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Info: [ 10489, 10647) |****
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Info: [ 10647, 10805) |*****
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Info: [ 10805, 10963) |*******
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Info: [ 10963, 11121) |
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Info: [ 11121, 11279) |**
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Info: [ 11279, 11437) |***
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Info: Checksum: 0xa39bec75
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 1732 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 270 721 | 270 721 | 1030| 0.09 0.09|
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Info: 2000 | 389 1543 | 119 822 | 154| 0.19 0.28|
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Info: 2162 | 398 1695 | 9 152 | 0| 0.03 0.31|
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Info: Routing complete.
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Info: Router1 time 0.31s
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Info: Checksum: 0xd6f72769
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source state_TRELLIS_FF_Q_5.Q
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Info: routing 0.59 0.99 Net page_hit_reg_LUT4_D_Z_LUT4_Z_D_LUT4_D_Z_LUT4_Z_C[1] (36,20) -> (37,20)
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Info: Sink req_pending_LUT4_D.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.17 Source req_pending_LUT4_D.F
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Info: routing 0.75 1.91 Net req_pending_LUT4_D_Z[2] (37,20) -> (35,20)
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Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.09 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
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Info: routing 0.45 2.54 Net psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D[3] (35,20) -> (35,20)
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Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.72 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F
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Info: routing 1.06 3.79 Net psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z_C[2] (35,20) -> (34,17)
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Info: Sink psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.97 Source psram_oe_n_TRELLIS_FF_Q_DI_LUT4_Z.F
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Info: routing 0.12 4.09 Net psram_oe_n_TRELLIS_FF_Q_DI (34,17) -> (34,17)
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Info: Sink psram_oe_n_TRELLIS_FF_Q.DI
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Info: setup 0.00 4.09 Source psram_oe_n_TRELLIS_FF_Q.DI
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Info: 1.12 ns logic, 2.97 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source mem_addr[13]$tr_io.O
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Info: routing 4.11 4.11 Net mem_addr[13]$TRELLIS_IO_IN (15,71) -> (38,20)
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Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.B
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Info: Defined in:
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Info: rtl/psram_controller.v:15.35-15.43
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Info: logic 0.18 4.30 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F
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Info: routing 0.16 4.45 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z_D[3] (38,20) -> (38,20)
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Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 4.63 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D_LUT4_Z.F
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Info: routing 0.63 5.27 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1_D[2] (38,20) -> (39,20)
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Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.45 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_1.F
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Info: routing 0.66 6.10 Net page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (39,20) -> (39,19)
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Info: Sink page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 6.28 Source page_hit_reg_TRELLIS_FF_Q_DI_LUT4_Z.F
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Info: routing 0.12 6.40 Net page_hit_reg_TRELLIS_FF_Q_DI (39,19) -> (39,19)
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Info: Sink page_hit_reg_TRELLIS_FF_Q.DI
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Info: setup 0.00 6.40 Source page_hit_reg_TRELLIS_FF_Q.DI
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Info: 0.72 ns logic, 5.68 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dq_oe_TRELLIS_FF_Q.Q
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Info: routing 3.49 3.89 Net dq_oe (35,20) -> (18,67)
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Info: Sink psram_dq[1]$tr_io$invert_T.A
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Info: Defined in:
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Info: rtl/psram_controller.v:188.27-188.32
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Info: logic 0.18 4.07 Source psram_dq[1]$tr_io$invert_T.F
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Info: routing 0.67 4.74 Net psram_dq[1]$tr_io$invert_T$conn$Z (18,67) -> (18,71)
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Info: Sink psram_dq[1]$tr_io.T
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Info: 0.57 ns logic, 4.16 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 244.74 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.40 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.74 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 8414, 8558) |*****
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Info: [ 8558, 8702) |****
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Info: [ 8702, 8846) |****************
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Info: [ 8846, 8990) |**************************
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Info: [ 8990, 9134) |**********************
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Info: [ 9134, 9278) |**********************************************
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Info: [ 9278, 9422) |**********************
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Info: [ 9422, 9566) |********************
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Info: [ 9566, 9710) |**************************
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Info: [ 9710, 9854) |********************************
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Info: [ 9854, 9998) |*****************
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Info: [ 9998, 10142) |*************
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Info: [ 10142, 10286) |**********
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Info: [ 10286, 10430) |********
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Info: [ 10430, 10574) |***********
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Info: [ 10574, 10718) |******
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Info: [ 10718, 10862) |********
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Info: [ 10862, 11006) |****
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Info: [ 11006, 11150) |*
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Info: [ 11150, 11294) |***
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Info: Program finished normally.
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