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micheleandClaude Sonnet 5 5f0d7f101c feat(v2): M3 activation/weight/result buffers, real BRAM mapping 
Implements M3: three parametric dual-port buffers for the §12
data-plane (Input/Weight/Result), reusing the proven BRAM-inference
idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write,
synchronous REGISTERED read, no reset on the read register -- keeps
Yosys off the LUT-RAM path).

Verified with Verilator: 10/10 tests pass (write-then-read
correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit
tile width round-tripping, undisturbed re-reads).

Real synthesis at two depths per module (6 configs total): 0 CHECK
problems, every configuration correctly infers DP16KD (never
LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is
driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth
reduction (512->64) left DP16KD usage unchanged at 2, while
activation_buffer/result_buffer (byte-wide) scale as naively expected
(2->1). All default-depth configs PASS at 80MHz with large margin
(287-367 MHz) via real nextpnr-ecp5 place&route.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-05 14:19:11 +02:00

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/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
-- Running command `
read_verilog hardware/v2/rtl/activation_buffer.v
chparam -set DEPTH 256 activation_buffer
synth_ecp5 -json hardware/v2/synthesis/activation_buffer_d256/top.json -top activation_buffer
' --
1. Executing Verilog-2005 frontend: hardware/v2/rtl/activation_buffer.v
Parsing Verilog input from `hardware/v2/rtl/activation_buffer.v' to AST representation.
Generating RTLIL representation for module `\activation_buffer'.
Successfully finished Verilog frontend.
Parameter \DEPTH = 256
2. Executing AST frontend in derive mode using pre-parsed AST for module `\activation_buffer'.
Parameter \DEPTH = 256
Generating RTLIL representation for module `$paramod\activation_buffer\DEPTH=s32'00000000000000000000000100000000'.
3. Executing SYNTH_LATTICE pass.
3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\VLO'.
Generating RTLIL representation for module `\VHI'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\DP16KD'.
Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261.
Generating RTLIL representation for module `\FD1P3AX'.
Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261.
Generating RTLIL representation for module `\FD1P3AY'.
Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261.
Generating RTLIL representation for module `\FD1P3BX'.
Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261.
Generating RTLIL representation for module `\FD1P3DX'.
Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261.
Generating RTLIL representation for module `\FD1P3IX'.
Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261.
Generating RTLIL representation for module `\FD1P3JX'.
Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261.
Generating RTLIL representation for module `\FD1S3AX'.
Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261.
Generating RTLIL representation for module `\FD1S3AY'.
Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261.
Generating RTLIL representation for module `\FD1S3BX'.
Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261.
Generating RTLIL representation for module `\FD1S3DX'.
Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261.
Generating RTLIL representation for module `\FD1S3IX'.
Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261.
Generating RTLIL representation for module `\FD1S3JX'.
Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301.
Generating RTLIL representation for module `\IFS1P3BX'.
Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301.
Generating RTLIL representation for module `\IFS1P3DX'.
Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301.
Generating RTLIL representation for module `\IFS1P3IX'.
Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301.
Generating RTLIL representation for module `\IFS1P3JX'.
Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302.
Generating RTLIL representation for module `\OFS1P3BX'.
Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302.
Generating RTLIL representation for module `\OFS1P3DX'.
Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302.
Generating RTLIL representation for module `\OFS1P3IX'.
Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302.
Generating RTLIL representation for module `\OFS1P3JX'.
Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157.
Generating RTLIL representation for module `\IB'.
Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157.
Generating RTLIL representation for module `\IBPU'.
Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157.
Generating RTLIL representation for module `\IBPD'.
Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157.
Generating RTLIL representation for module `\OB'.
Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164.
Generating RTLIL representation for module `\OBZ'.
Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164.
Generating RTLIL representation for module `\OBZPU'.
Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164.
Generating RTLIL representation for module `\OBZPD'.
Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90.
Generating RTLIL representation for module `\OBCO'.
Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179.
Generating RTLIL representation for module `\BB'.
Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179.
Generating RTLIL representation for module `\BBPU'.
Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179.
Generating RTLIL representation for module `\BBPD'.
Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139.
Generating RTLIL representation for module `\ILVDS'.
Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DCUA'.
Successfully finished Verilog frontend.
3.3. Executing HIERARCHY pass (managing design hierarchy).
3.3.1. Analyzing design hierarchy..
Top module: \activation_buffer
3.3.2. Analyzing design hierarchy..
Top module: \activation_buffer
Removed 0 unused modules.
3.4. Executing PROC pass (convert processes to netlists).
3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$hardware/v2/rtl/activation_buffer.v:38$12 in module activation_buffer.
Removed a total of 0 dead cases.
3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.
3.4.4. Executing PROC_INIT pass (extract init attributes).
3.4.5. Executing PROC_ARST pass (detect async resets in processes).
3.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>
3.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
1/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$18
2/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_DATA[7:0]$17
3/3: $1$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_ADDR[7:0]$16
Creating decoders for process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'.
3.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_ADDR' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
created $dff cell `$procdff$255' with positive edge clock.
Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_DATA' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
created $dff cell `$procdff$256' with positive edge clock.
Creating register for signal `\activation_buffer.$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
created $dff cell `$procdff$257' with positive edge clock.
Creating register for signal `\activation_buffer.\rd_data' using process `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'.
created $dff cell `$procdff$258' with positive edge clock.
3.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:38$12'.
Removing empty process `activation_buffer.$proc$hardware/v2/rtl/activation_buffer.v:43$19'.
Cleaned up 1 empty switch.
3.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.5. Executing CHECK pass (checking for obvious problems).
Checking module activation_buffer...
Found and reported 0 problems.
3.6. Executing FLATTEN pass (flatten design).
3.7. Executing TRIBUF pass.
3.8. Executing DEMINOUT pass (demote inout ports to input or output).
3.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
Removed 3 unused cells and 13 unused wires.
<suppressed ~4 debug messages>
3.11. Executing CHECK pass (checking for obvious problems).
Checking module activation_buffer...
Found and reported 0 problems.
3.12. Executing OPT pass (performing simple optimizations).
3.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \activation_buffer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \activation_buffer.
Consolidated identical input bits for $mux cell $procmux$247:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15
New ports: A=1'0, B=1'1, Y=$0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0]
New connections: $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [7:1] = { $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] $0$memwr$\mem$hardware/v2/rtl/activation_buffer.v:40$11_EN[7:0]$15 [0] }
Optimizing cells in module \activation_buffer.
Performed a total of 1 changes.
3.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.12.6. Executing OPT_DFF pass (perform DFF optimizations).
3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.12.9. Rerunning OPT passes. (Maybe there is more to do..)
3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \activation_buffer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \activation_buffer.
Performed a total of 0 changes.
3.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.12.13. Executing OPT_DFF pass (perform DFF optimizations).
3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.12.16. Finished fast OPT passes. (There is nothing left to do.)
3.13. Executing FSM pass (extract and optimize FSM).
3.13.1. Executing FSM_DETECT pass (finding FSMs in design).
3.13.2. Executing FSM_EXTRACT pass (extracting FSM from design).
3.13.3. Executing FSM_OPT pass (simple optimizations of FSMs).
3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.13.5. Executing FSM_OPT pass (simple optimizations of FSMs).
3.13.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
3.13.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
3.13.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
3.14. Executing OPT pass (performing simple optimizations).
3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \activation_buffer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \activation_buffer.
Performed a total of 0 changes.
3.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.14.6. Executing OPT_DFF pass (perform DFF optimizations).
3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.14.9. Finished fast OPT passes. (There is nothing left to do.)
3.15. Executing WREDUCE pass (reducing word size of cells).
3.16. Executing PEEPOPT pass (run peephole optimizers).
3.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.18. Executing SHARE pass (SAT-based resource sharing).
3.19. Executing TECHMAP pass (map to technology primitives).
3.19.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
3.19.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
3.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.22. Executing TECHMAP pass (map to technology primitives).
3.22.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
3.22.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
3.23. Executing TECHMAP pass (map to technology primitives).
3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation.
Generating RTLIL representation for module `$__MUL18X18'.
Successfully finished Verilog frontend.
3.23.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
3.24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module activation_buffer:
created 0 $alu and 0 $macc cells.
3.25. Executing OPT pass (performing simple optimizations).
3.25.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.25.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.25.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \activation_buffer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>
3.25.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \activation_buffer.
Performed a total of 0 changes.
3.25.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 6 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.25.6. Executing OPT_DFF pass (perform DFF optimizations).
3.25.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.25.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.25.9. Finished fast OPT passes. (There is nothing left to do.)
3.26. Executing MEMORY pass.
3.26.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
3.26.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
3.26.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing activation_buffer.mem write port 0.
3.26.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
3.26.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\mem'[0] in module `\activation_buffer': merging output FF to cell.
Write port 0: non-transparent.
3.26.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>
3.26.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
3.26.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
3.26.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.26.10. Executing MEMORY_COLLECT pass (generating $mem cells).
3.27. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.28. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory activation_buffer.mem via $__DP16KD_
<suppressed ~481 debug messages>
3.29. Executing TECHMAP pass (map to technology primitives).
3.29.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.
3.29.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation.
Generating RTLIL representation for module `$__DP16KD_'.
Generating RTLIL representation for module `$__PDPW16KD_'.
Successfully finished Verilog frontend.
3.29.3. Continuing TECHMAP pass.
Using template $paramod$eed5c07ccc20b30fea5f07adc53d361b0ef0f8bc$__DP16KD_ for cells of type $__DP16KD_.
No more expansions possible.
<suppressed ~35 debug messages>
3.30. Executing OPT pass (performing simple optimizations).
3.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
<suppressed ~6 debug messages>
3.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 9 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.30.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$mem.cc:1169:emulate_transparency$277 ($dffe) from module activation_buffer.
3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
Removed 0 unused cells and 26 unused wires.
<suppressed ~1 debug messages>
3.30.5. Rerunning OPT passes. (Removed registers in this run.)
3.30.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.30.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 9 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.30.8. Executing OPT_DFF pass (perform DFF optimizations).
3.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.30.10. Finished fast OPT passes.
3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
3.32. Executing OPT pass (performing simple optimizations).
3.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 9 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \activation_buffer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>
3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \activation_buffer.
Performed a total of 0 changes.
3.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 9 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.32.6. Executing OPT_DFF pass (perform DFF optimizations).
3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.32.9. Finished fast OPT passes. (There is nothing left to do.)
3.33. Executing TECHMAP pass (map to technology primitives).
3.33.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
3.33.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation.
Generating RTLIL representation for module `\_80_ccu2c_alu'.
Successfully finished Verilog frontend.
3.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
No more expansions possible.
<suppressed ~85 debug messages>
3.34. Executing OPT pass (performing simple optimizations).
3.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 52 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.34.3. Executing OPT_DFF pass (perform DFF optimizations).
3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
3.34.5. Finished fast OPT passes.
3.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
3.37. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\activation_buffer'.
Computing hashes of 52 cells of `\activation_buffer'.
Finding duplicate cells in `\activation_buffer'.
Removed a total of 0 cells.
3.38. Executing TECHMAP pass (map to technology primitives).
3.38.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
3.38.2. Continuing TECHMAP pass.
Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~108 debug messages>
3.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module activation_buffer.
3.40. Executing SIMPLEMAP pass (map simple cells to gate primitives).
3.41. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in activation_buffer.
3.42. Executing ATTRMVCP pass (move or copy attributes).
3.43. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \activation_buffer..
Removed 0 unused cells and 104 unused wires.
<suppressed ~1 debug messages>
3.44. Executing CHECK pass (checking for obvious problems).
Checking module activation_buffer...
Found and reported 0 problems.
3.45. Executing TECHMAP pass (map to technology primitives).
3.45.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation.
Generating RTLIL representation for module `$_DLATCH_N_'.
Generating RTLIL representation for module `$_DLATCH_P_'.
Successfully finished Verilog frontend.
3.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
3.46. Executing ABC9 pass.
3.46.1. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.2. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module activation_buffer.
Found 0 SCCs.
3.46.4. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.5. Executing TECHMAP pass (map to technology primitives).
3.46.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
3.46.5.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~165 debug messages>
3.46.6. Executing OPT pass (performing simple optimizations).
3.46.6.1. Executing OPT_EXPR pass (perform const folding).
3.46.6.2. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
3.46.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Removed 0 multiplexer ports.
3.46.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Performed a total of 0 changes.
3.46.6.5. Executing OPT_MERGE pass (detect identical cells).
Removed a total of 0 cells.
3.46.6.6. Executing OPT_DFF pass (perform DFF optimizations).
3.46.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
3.46.6.8. Executing OPT_EXPR pass (perform const folding).
3.46.6.9. Finished fast OPT passes. (There is nothing left to do.)
3.46.7. Executing TECHMAP pass (map to technology primitives).
3.46.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.
3.46.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~2 debug messages>
3.46.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.
3.46.9. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.10. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>
3.46.12. Executing AIGMAP pass (map logic to AIG).
Module activation_buffer: replaced 23 cells with 140 new cells, skipped 29 cells.
replaced 3 cell types:
8 $_MUX_
7 $_OR_
8 $_XOR_
not replaced 4 cell types:
1 $_AND_
1 $_NOT_
26 TRELLIS_FF
1 DP16KD
3.46.12.1. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.12.2. Executing ABC9_OPS pass (helper functions for ABC9).
3.46.12.3. Executing XAIGER backend.
<suppressed ~5 debug messages>
Extracted 56 AND gates and 204 wires from module `activation_buffer' to a netlist network with 60 inputs and 26 outputs.
3.46.12.4. Executing ABC9_EXE pass (technology mapping using ABC9).
3.46.12.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_lut <abc-temp-dir>/input.lut
ABC: + read_box <abc-temp-dir>/input.box
ABC: + &read <abc-temp-dir>/input.xaig
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0
ABC: + &scorr
ABC: Warning: The network is combinational.
ABC: + &sweep
ABC: + &dc2
ABC: + &dch -f -r
ABC: + &ps
ABC: <abc-temp-dir>/input : i/o = 60/ 26 and = 119 lev = 6 (0.85) mem = 0.00 MB ch = 13 box = 0 bb = 0
ABC: cst = 0 cls = 12 lit = 13 unused = 154 proof = 0
ABC: + &if -W 300 -v
ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no
ABC: Node = 119. Ch = 12. Total mem = 0.03 MB. Peak cut mem = 0.02 MB.
ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 648. T = 0.00 sec
ABC: P: Del = 1612.00. Ar = 33.0. Edge = 58. Cut = 634. T = 0.00 sec
ABC: P: Del = 1612.00. Ar = 27.0. Edge = 59. Cut = 849. T = 0.00 sec
ABC: F: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 756. T = 0.00 sec
ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 729. T = 0.00 sec
ABC: A: Del = 1581.00. Ar = 21.0. Edge = 58. Cut = 725. T = 0.00 sec
ABC: Total time = 0.00 sec
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &mfs
ABC: Timing manager is given but there is no GIA of boxes.
ABC: Error: Abc_FrameUpdateGia(): Transformation has failed.
ABC: + &ps -l
ABC: <abc-temp-dir>/input : i/o = 60/ 26 and = 56 lev = 6 (0.85) mem = 0.00 MB box = 0 bb = 0
ABC: Mapping (K=6) : lut = 16 edge = 58 lev = 3 (0.42) mem = 0.00 MB
ABC: LUT = 16 : 2=1 6.2 % 3=8 50.0 % 4=4 25.0 % 5=2 12.5 % 6=1 6.2 % Ave = 3.62
ABC: + &write -n <abc-temp-dir>/output.aig
ABC: + &verify
ABC: Networks are equivalent. Time = 0.01 sec
ABC: + time
ABC: elapse: 0.01 seconds, total: 0.01 seconds
3.46.12.6. Executing AIGER frontend.
<suppressed ~8 debug messages>
Removed 89 unused cells and 158 unused wires.
3.46.12.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module).
ABC RESULTS: $lut cells: 16
ABC RESULTS: input signals: 8
ABC RESULTS: output signals: 5
<suppressed ~172 debug messages>
Removing temp directory.
3.46.13. Executing TECHMAP pass (map to technology primitives).
3.46.13.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.
3.46.13.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>
Removed 8 unused cells and 233 unused wires.
3.47. Executing TECHMAP pass (map to technology primitives).
3.47.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v
Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation.
Generating RTLIL representation for module `$_DFF_N_'.
Generating RTLIL representation for module `$_DFF_P_'.
Generating RTLIL representation for module `$_DFFE_NN_'.
Generating RTLIL representation for module `$_DFFE_PN_'.
Generating RTLIL representation for module `$_DFFE_NP_'.
Generating RTLIL representation for module `$_DFFE_PP_'.
Generating RTLIL representation for module `$_DFF_NP0_'.
Generating RTLIL representation for module `$_DFF_NP1_'.
Generating RTLIL representation for module `$_DFF_PP0_'.
Generating RTLIL representation for module `$_DFF_PP1_'.
Generating RTLIL representation for module `$_SDFF_NP0_'.
Generating RTLIL representation for module `$_SDFF_NP1_'.
Generating RTLIL representation for module `$_SDFF_PP0_'.
Generating RTLIL representation for module `$_SDFF_PP1_'.
Generating RTLIL representation for module `$_DFFE_NP0P_'.
Generating RTLIL representation for module `$_DFFE_NP1P_'.
Generating RTLIL representation for module `$_DFFE_PP0P_'.
Generating RTLIL representation for module `$_DFFE_PP1P_'.
Generating RTLIL representation for module `$_DFFE_NP0N_'.
Generating RTLIL representation for module `$_DFFE_NP1N_'.
Generating RTLIL representation for module `$_DFFE_PP0N_'.
Generating RTLIL representation for module `$_DFFE_PP1N_'.
Generating RTLIL representation for module `$_SDFFE_NP0P_'.
Generating RTLIL representation for module `$_SDFFE_NP1P_'.
Generating RTLIL representation for module `$_SDFFE_PP0P_'.
Generating RTLIL representation for module `$_SDFFE_PP1P_'.
Generating RTLIL representation for module `$_SDFFE_NP0N_'.
Generating RTLIL representation for module `$_SDFFE_NP1N_'.
Generating RTLIL representation for module `$_SDFFE_PP0N_'.
Generating RTLIL representation for module `$_SDFFE_PP1N_'.
Generating RTLIL representation for module `$_ALDFF_NP_'.
Generating RTLIL representation for module `$_ALDFF_PP_'.
Generating RTLIL representation for module `$_ALDFFE_NPN_'.
Generating RTLIL representation for module `$_ALDFFE_NPP_'.
Generating RTLIL representation for module `$_ALDFFE_PPN_'.
Generating RTLIL representation for module `$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `$lut'.
Successfully finished Verilog frontend.
3.47.2. Continuing TECHMAP pass.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de$lut for cells of type $lut.
Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$977bf81c91b9e0cdfe901822d1642d278c1b0ecd$lut for cells of type $lut.
Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c$lut for cells of type $lut.
Using template $paramod$adb3580ae7f1e000bff662054d4f52a48cec1e58$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut.
No more expansions possible.
<suppressed ~218 debug messages>
3.48. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in activation_buffer.
Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$1022$lut$aiger1021$88.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$1022$lut$aiger1021$70.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$1022$lut$aiger$o2.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Removed 0 unused cells and 37 unused wires.
3.49. Executing AUTONAME pass.
Renamed 89 objects in module activation_buffer.
<suppressed ~89 debug messages>
3.50. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `activation_buffer'. Setting top module to activation_buffer.
3.50.1. Analyzing design hierarchy..
Top module: \activation_buffer
3.50.2. Analyzing design hierarchy..
Top module: \activation_buffer
Removed 0 unused modules.
3.51. Printing statistics.
=== activation_buffer ===
+----------Local Count, excluding submodules.
|
43 wires
159 wire bits
43 public wires
159 public wire bits
6 ports
34 port bits
1 cells
1 DP16KD
52 submodules
1 L6MUX21
21 LUT4
4 PFUMX
26 TRELLIS_FF
=== design hierarchy ===
+----------Count including submodules.
|
1 activation_buffer
+----------Count including submodules.
|
43 wires
159 wire bits
43 public wires
159 public wire bits
6 ports
34 port bits
- memories
- memory bits
- processes
1 cells
1 DP16KD
52 submodules
1 L6MUX21
21 LUT4
4 PFUMX
26 TRELLIS_FF
3.52. Executing CHECK pass (checking for obvious problems).
Checking module activation_buffer...
Found and reported 0 problems.
3.53. Executing JSON backend.
End of script. Logfile hash: 6a34f02f72, time: 0.30s, user: 0.27s, system: 0.01s, MEM: 28.34 MB peak
Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)
Time spent: 56% 20x read_verilog (0 sec), 24% 11x techmap (0 sec), ...
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