micheleandClaude Sonnet 5
481b5d223f
Real critical-path trace after the flash #1 revert showed a NEW bottleneck (neural_director.job_out_slot -> dependency_manager. node_resolved/node_state, 76-84% routing) distinct from every prior fix this session -- already a flat, parallel 64-way compare, not a serial chain, so the established restructuring fix class doesn't apply. Root cause: any_pending (added for FPGA_DATA_READY) reads node_state[0:N_NODES-1] combinationally every cycle, adding real fan-out onto the same congested signal. User's own suggestion: replace the combinational scan with a synchronous up/down counter. pending_count +1 on registration acceptance, -1 on dispatch acceptance; any_pending = (pending_count != 0) -- mathematically identical (DEC-0008: nodes never reclaimed mid-run) but reads one small register instead of scanning a 16-wide array every cycle. Verified: D-Stress N=4 bit-exact (49927 cycles, data_ready PASS). Fresh 8-seed P&R: N_SLOTS=4 @ 64MHz now 8/8 PASS (was 7/8 after the flash revert), worst seed1 64.55MHz, best seed0 72.37MHz. See decisions.log DEC-0042. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
231 lines
11 KiB
Verilog
231 lines
11 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// FPGA-Neural V2 -- Dependency Manager (M6, docs/v2-description.md §10)
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//
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// Holds a small table of N_NODES job descriptors, each tracking:
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// node_id, state (EMPTY/WAITING/READY/DISPATCHED),
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// required_dependencies, resolved_dependencies, producer_ids[MAX_DEPS]
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// (§10's exact field list), plus the job descriptor fields
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// (x_base/w_base/n_tiles/result_addr) needed to hand the node off to
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// the Neural Director (M5) once it becomes READY.
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//
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// A node with required_dependencies==0 is immediately READY on
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// registration (no producers to wait for -- a graph's own input
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// nodes, or a fully-independent job). When a PRODUCER completes
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// (producer_done_valid/producer_done_node_id, tagged by whichever
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// node just finished -- fed from the Director's own job_out_done/
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// job_out_slot, resolved back to a node_id by the caller), every
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// OTHER node that lists that producer among its own producer_ids
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// gets its resolved_dependencies incremented -- a single producer
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// can satisfy MULTIPLE waiting consumers this way (§10 "risultati
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// condivisi... più consumer"), and a node depending on several
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// producers accumulates resolved_dependencies across separate
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// producer-done events ("dipendenze multiple").
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//
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// Ready nodes are handed to the Director one at a time via a
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// valid/ready producer interface (ready_valid/ready_ready), backpressure-
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// safe (§10 "backpressure"): a node stays READY, occupying its table
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// slot, until the consumer (Director) actually accepts it.
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//
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// Scope note (see hardware/v2/logs/decisions.log DEC-0008): §11's
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// direct producer-to-consumer VALUE forwarding (bypassing the Result
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// Buffer / external memory round-trip) is NOT implemented here --
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// this module tracks dependency COUNTS/readiness only ("has this
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// node's data become available", not the data itself), which is what
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// actually gates scheduling; the job descriptor's result_addr already
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// points at wherever the Memory Manager (M4) wrote the producer's
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// result, which is how a ready consumer finds its inputs today. Real
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// zero-copy forwarding is a possible future optimization (§11 itself:
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// "quando possibile"), deferred until measured to matter (§22).
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// ================================================================
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module dependency_manager #(
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parameter N_NODES = 16,
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parameter MAX_DEPS = 4,
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parameter ADDR_WIDTH = 26
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)(
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input wire clk,
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input wire rst,
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// ---- node registration (host / graph loader) ----
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input wire reg_valid,
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output wire reg_ready,
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input wire [$clog2(N_NODES)-1:0] reg_node_id,
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input wire [$clog2(MAX_DEPS+1)-1:0] reg_required,
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input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids,
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input wire [ADDR_WIDTH-1:0] reg_x_base,
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input wire [ADDR_WIDTH-1:0] reg_w_base,
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input wire [15:0] reg_n_tiles,
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input wire [ADDR_WIDTH-1:0] reg_result_addr,
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// ---- producer completion notification ----
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input wire producer_done_valid,
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input wire [$clog2(N_NODES)-1:0] producer_done_node_id,
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// ---- ready job output (to neural_director.v's job_in_* port) ----
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output reg ready_valid,
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input wire ready_ready,
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output reg [$clog2(N_NODES)-1:0] ready_node_id,
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output reg [ADDR_WIDTH-1:0] ready_x_base,
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output reg [ADDR_WIDTH-1:0] ready_w_base,
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output reg [15:0] ready_n_tiles,
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output reg [ADDR_WIDTH-1:0] ready_result_addr,
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// FPGA_DATA_READY support: high while at least one registered node
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// has not yet been handed to the Director (ST_WAITING or ST_READY --
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// ST_DISPATCHED is deliberately excluded, since dispatched work is
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// tracked downstream by neural_director.v's own queue/slot state,
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// not here -- see this file's own ST_DISPATCHED comment).
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output wire any_pending
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);
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localparam ST_EMPTY = 2'd0;
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localparam ST_WAITING = 2'd1;
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localparam ST_READY = 2'd2;
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localparam ST_DISPATCHED = 2'd3;
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localparam NODE_IDW = $clog2(N_NODES);
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localparam REQW = $clog2(MAX_DEPS+1);
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reg [1:0] node_state [0:N_NODES-1];
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reg [REQW-1:0] node_required [0:N_NODES-1];
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reg [REQW-1:0] node_resolved [0:N_NODES-1];
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reg [NODE_IDW-1:0] node_producer_ids [0:N_NODES-1][0:MAX_DEPS-1];
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reg [ADDR_WIDTH-1:0] node_x_base [0:N_NODES-1];
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reg [ADDR_WIDTH-1:0] node_w_base [0:N_NODES-1];
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reg [15:0] node_n_tiles [0:N_NODES-1];
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reg [ADDR_WIDTH-1:0] node_result_addr [0:N_NODES-1];
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// A node id doubles as its own table slot index (§10's example
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// literally addresses nodes by id: "node 37") -- N_NODES must
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// therefore cover the full id range a caller intends to use.
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assign reg_ready = (node_state[reg_node_id] == ST_EMPTY);
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// ---- priority-encoded first READY node (first-found scan, same
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// idiom as neural_director's own free-slot scan) ----
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reg [NODE_IDW-1:0] first_ready_idx;
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reg any_ready;
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integer ri;
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always @(*) begin
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first_ready_idx = {NODE_IDW{1'b0}};
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any_ready = 1'b0;
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for (ri = N_NODES-1; ri >= 0; ri = ri - 1) begin
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if (node_state[ri] == ST_READY) begin
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first_ready_idx = ri[NODE_IDW-1:0];
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any_ready = 1'b1;
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end
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end
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end
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// ---- FPGA_DATA_READY support (see any_pending port comment above).
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// Originally a combinational OR-reduce over node_state[0:N_NODES-1]
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// (16-wide), which added real fan-out load onto node_state -- a
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// signal this session's own real P&R critical-path traces later
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// showed sitting on the SAME already-congested job_out_slot ->
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// node_resolved/node_state broadcast path (routing-dominated,
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// 76-84%). Replaced with a synchronous up/down counter: +1 on a
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// node's own registration acceptance (reg_valid&®_ready --
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// exactly when it enters WAITING/READY), -1 on its own dispatch
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// acceptance (ready_valid&&ready_ready -- exactly when it leaves
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// WAITING/READY for DISPATCHED). registered-minus-dispatched is
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// mathematically identical to the original OR-reduce's own
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// "any node currently WAITING or READY" condition (DEC-0008: nodes
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// are never reclaimed mid-run, so every node visits EMPTY ->
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// {WAITING or READY} -> DISPATCHED exactly once), but reads a
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// single small registered counter instead of scanning a wide array
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// every cycle -- zero added fan-out on the congested signals. ----
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localparam PENDW = $clog2(N_NODES+1);
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reg [PENDW-1:0] pending_count;
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assign any_pending = (pending_count != {PENDW{1'b0}});
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integer ni, di;
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always @(posedge clk) begin
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if (rst) begin
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for (ni = 0; ni < N_NODES; ni = ni + 1) begin
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node_state[ni] <= ST_EMPTY;
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node_required[ni] <= {REQW{1'b0}};
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node_resolved[ni] <= {REQW{1'b0}};
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end
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ready_valid <= 1'b0;
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pending_count <= {PENDW{1'b0}};
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end else begin
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// pending_count: +1 on registration acceptance, -1 on
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// dispatch acceptance; a same-cycle occurrence of both is a
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// net zero change (no assignment needed, old value holds).
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case ({(reg_valid && reg_ready), (ready_valid && ready_ready)})
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2'b10: pending_count <= pending_count + 1'b1;
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2'b01: pending_count <= pending_count - 1'b1;
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default: ; // 00 or 11: no net change
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endcase
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// ---- registration: create a new WAITING (or immediately
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// READY, if required==0) node entry. ----
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if (reg_valid && reg_ready) begin
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node_required[reg_node_id] <= reg_required;
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node_resolved[reg_node_id] <= {REQW{1'b0}};
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node_x_base[reg_node_id] <= reg_x_base;
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node_w_base[reg_node_id] <= reg_w_base;
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node_n_tiles[reg_node_id] <= reg_n_tiles;
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node_result_addr[reg_node_id] <= reg_result_addr;
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for (di = 0; di < MAX_DEPS; di = di + 1)
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node_producer_ids[reg_node_id][di] <= reg_producer_ids[di*NODE_IDW +: NODE_IDW];
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node_state[reg_node_id] <= (reg_required == {REQW{1'b0}}) ? ST_READY : ST_WAITING;
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end
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// ---- wake-up: a completed producer increments
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// resolved_dependencies for EVERY WAITING node that lists
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// it, independent of the registration above (a node can
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// be registered and immediately woken by an in-flight
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// producer-done event the same cycle, since both read the
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// PRE-edge node_state/node_producer_ids consistently). ----
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if (producer_done_valid) begin
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for (ni = 0; ni < N_NODES; ni = ni + 1) begin
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if (node_state[ni] == ST_WAITING) begin
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for (di = 0; di < MAX_DEPS; di = di + 1) begin
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if (di < node_required[ni] &&
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node_producer_ids[ni][di] == producer_done_node_id) begin
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if (node_resolved[ni] + 1'b1 >= node_required[ni])
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node_state[ni] <= ST_READY;
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node_resolved[ni] <= node_resolved[ni] + 1'b1;
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end
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end
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end
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end
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end
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// ---- dispatch: hand the first READY node to the
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// Director, one at a time, backpressure-safe. ----
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if (ready_valid && ready_ready) begin
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node_state[ready_node_id] <= ST_DISPATCHED;
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// ST_DISPATCHED is terminal here (M6 does not yet
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// reclaim slots for re-use -- see decisions.log
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// DEC-0008): a full graph run allocates N_NODES once.
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ready_valid <= 1'b0;
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end else if (!ready_valid && any_ready) begin
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// Deliberately NOT combined with the dispatch branch
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// above into "!ready_valid || (ready_valid&&ready_ready)"
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// -- the scan for first_ready_idx is combinational
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// over node_state's PRE-edge value, which still shows
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// the about-to-be-dispatched node as READY this same
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// edge; reloading in the same cycle as a dispatch
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// could re-present the SAME node that is simultaneously
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// transitioning to DISPATCHED. Reloading strictly the
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// cycle AFTER (once ready_valid has genuinely gone
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// low and node_state has committed) costs one extra
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// idle cycle between consecutive dispatches but is
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// unambiguously correct.
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ready_valid <= 1'b1;
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ready_node_id <= first_ready_idx;
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ready_x_base <= node_x_base[first_ready_idx];
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ready_w_base <= node_w_base[first_ready_idx];
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ready_n_tiles <= node_n_tiles[first_ready_idx];
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ready_result_addr <= node_result_addr[first_ready_idx];
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end
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end
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end
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endmodule
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