micheleandClaude Sonnet 5
dc0b331d3e
Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
105 lines
2.8 KiB
Verilog
105 lines
2.8 KiB
Verilog
module memory_model #(
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parameter ADDR_WIDTH = 23,
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parameter DATA_WIDTH = 16,
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parameter DEPTH = 4096,
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parameter READ_LATENCY = 2
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)(
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input wire clk,
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input wire rst,
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input wire req,
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input wire wr,
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input wire [ADDR_WIDTH-1:0] addr,
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input wire [DATA_WIDTH-1:0] wdata,
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output reg [DATA_WIDTH-1:0] rdata,
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output reg ready
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);
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reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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reg busy;
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reg pending_wr;
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reg [ADDR_WIDTH-1:0] pending_addr;
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reg [DATA_WIDTH-1:0] pending_wdata;
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integer delay_count;
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integer i;
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always @(posedge clk) begin
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if (rst) begin
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rdata <= {DATA_WIDTH{1'b0}};
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ready <= 1'b0;
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busy <= 1'b0;
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pending_wr <= 1'b0;
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pending_addr <= {ADDR_WIDTH{1'b0}};
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pending_wdata <= {DATA_WIDTH{1'b0}};
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delay_count <= 0;
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for (i = 0; i < DEPTH; i = i + 1)
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mem[i] <= {DATA_WIDTH{1'b0}};
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end else begin
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// ready is a one-cycle pulse
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ready <= 1'b0;
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// ----------------------------------------------------
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// Accept request
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// ----------------------------------------------------
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if (!busy) begin
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if (req) begin
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busy <= 1'b1;
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pending_wr <= wr;
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pending_addr <= addr;
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pending_wdata <= wdata;
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delay_count <= READ_LATENCY;
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end
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end else begin
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// ------------------------------------------------
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// Wait
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// ------------------------------------------------
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if (delay_count > 0) begin
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delay_count <= delay_count - 1;
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end else begin
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// --------------------------------------------
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// Complete transaction
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// --------------------------------------------
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if (pending_wr) begin
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// WRITE
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if (pending_addr < DEPTH)
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mem[pending_addr] <= pending_wdata;
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end else begin
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// READ
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if (pending_addr < DEPTH)
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rdata <= mem[pending_addr];
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else
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rdata <= {DATA_WIDTH{1'b0}};
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end
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ready <= 1'b1;
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busy <= 1'b0;
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end
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end
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end
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end
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endmodule |