micheleandClaude Sonnet 5
81a9619214
hardware/v1/ was created (dc0b331) as a frozen snapshot of the V1
project that then lived at the repo root (rtl/, sim/, synth/, tools/,
docs/). Root received zero further commits to those files after the
freeze -- confirmed byte-identical to the hardware/v1/ copy for every
file removed here. Root was the "before", hardware/v1/ is the
curated, canonical "after".
Removed (all verified exact-hash duplicates of hardware/v1/ content):
- rtl/ (20 files, 100% covered by hardware/v1/rtl/)
- tools/{netasm,pinout,run_regression.py,flash_catalog,validation,
fpga_benchmark.py} (19 files, 100% covered by hardware/v1/tools/;
tools/neural_sim/ kept -- unique, post-freeze, no counterpart)
- sim/*.v (47 testbenches, 100% covered by hardware/v1/sim/; the
~38 remaining sim/ entries are compiled binaries and .vcd
waveform dumps, left as a separate cleanup decision)
- synth/ecp5/{p2,p4,p8,post_fix_verify} (25 files, exact duplicates
of hardware/v1/synthesis/; the other ~84 synth/ecp5/* experiment
build directories are historical artifacts never carried into the
freeze, left as a separate decision)
- WORKLOG.md (duplicate of hardware/v1/docs/WORKLOG.md)
- docs/{FPGA-Neural-Datapatch-Benchmark,FPGA-Neural-Hardware-Design,
FPGA-NeuralNetwork-Engine}.md, docs/validation/*.md (18 files),
docs/FPGA-Neural-Datasheet-{EN,IT}.pdf -- all exact duplicates of
hardware/v1/docs/ content
- hardware/v1/docs/DatasheetLatex/ (24 files) -- exact duplicate of
hardware/v2/docs/datasheet/files/docs/datasheet/en/ (discovered
during this audit; not the same DatasheetLatex already removed
from hardware/v2/docs/ in an earlier commit)
Moved (genuine, unique, post-freeze V2 content -- not duplicated
anywhere, just living in the wrong/legacy root docs/ location):
- docs/architecture/*.md -> hardware/v2/docs/architecture/
- docs/pinouts.md, docs/FPGA_NEURAL_V2_DATASHEET.md,
docs/FPGA_NEURAL_V2_SCHEMATIC.md,
docs/FPGA-Neural-V2-Datasheet-EN.pdf -> hardware/v2/docs/
Left untouched (separate decisions, not part of this cleanup):
- docs/FPGA-Neural-Flash-Subsystem-Verification.md, docs/
v2-description.md -- orphaned root-only content, no duplicate
found anywhere, but also not part of the reviewed plan
- synth/ecp5/* experiment dirs and sim/*_sim + sim/*.vcd build
artifacts -- not literal duplicates, flagged as candidates for a
future, separate cleanup pass
Verified no functional breakage: grepped all remaining scripts/docs
for references to every removed path -- only prose/comment mentions
found, no executable imports or build-script paths broken.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
FPGA-Neural V1 — Golden Reference (FROZEN)
Questo albero è una copia bit-esatta del codice V1 così come esisteva al commit
07a48e4 (fix: close 7 zero-value/mid-run guard gaps found in re-certification
campaign) del repository principale. Verificato byte-per-byte al momento della
creazione (diff -rq contro rtl/ e sim/*.v dell'albero principale, 0
differenze).
Regola non negoziabile
Questo albero non deve mai essere modificato. È il riferimento funzionale,
numerico, prestazionale e bit-exact per ogni sviluppo V2 (hardware/v2/), per
policy esplicita di docs/v2-description.md §1 e §34 ("V1 rimane intatta").
Se un bug o miglioramento V1 viene scoperto durante lo sviluppo V2, non
correggerlo qui: documentarlo in hardware/v2/logs/decisions.log o
errors.log e, se necessario, applicarlo separatamente al V1 "vivo"
nell'albero principale del repository (rtl/, sim/, ecc.), mai in questa
copia.
Contenuto
rtl/— i 20 moduli RTL V1 (copia dirtl/*.vdell'albero principale).sim/— le 47 testbench V1 (copia disim/*.v, esclusi i.vcdgenerati: rieseguibili in loco coniverilog/vvp, non servono duplicati).tools/— copia ditools/(harness di regressione, netasm, generatore.lpf, oracoli di validazione).constraints/— i vincoli.lpfper ECP5 (spi_neuron_top.lpf,spi_neuron_top_flash.lpf).synthesis/— sottoinsieme rappresentativo dei risultati di sintesi reale già misurati sul V1 (non l'intera storia sperimentale, che resta nell'albero principale sottosynth/ecp5/):post_fix_verify/— sistema completo (spi_neuron_topcon sottosistema flash, PARALLEL=8), stato più recente e autorevole: 0 errori di vincolo, Fmax 68.65 MHz.p2/,p4/,p8/— sweep isolato dineuron_parallela PARALLEL variabile (N_INPUTS=256), stessa fonte dei numeri citati indocs/v2-description.md§3 per P8/P4/P2. Il dato P16 (52.13 MHz) citato nella stessa sezione proviene dadocs/FPGA-Neural-Datapatch-Benchmark.md(copiato indocs/), non da un artefatto di sintesi grezzo separato.
docs/— copia dei documenti di riferimento:WORKLOG.md, i capitoli didocs/validation/(campagna di certificazione + registro bug), il datasheet markdown (FPGA-NeuralNetwork-Engine.md), il report benchmark (FPGA-Neural-Datapatch-Benchmark.md) e il documento hardware (FPGA-Neural-Hardware-Design.md).
Dati baseline citati da V2 (docs/v2-description.md §3)
| Config | Fmax (isolato, N_INPUTS=256) | Fonte |
|---|---|---|
| PARALLEL=16 | 52.13 MHz (FAIL @80MHz) | docs/FPGA-Neural-Datapatch-Benchmark.md |
| PARALLEL=8 | 61.71 MHz (FAIL @80MHz) | synthesis/p8/ |
| PARALLEL=4 | 75.01 MHz (FAIL @80MHz) | synthesis/p4/ |
| PARALLEL=2 | 87.88 MHz (PASS @80MHz) | synthesis/p2/ |
Sistema integrato (spi_neuron_top, PARALLEL=8, sottosistema flash incluso):
68.65 MHz (synthesis/post_fix_verify/, più recente della cifra 65.13 MHz
citata in docs/v2-description.md §3, che si riferiva a uno stato pre-fix
precedente — vedi docs/WORKLOG.md per la cronologia completa).
Percorso critico osservato in ogni misura: logica di neuron_parallel.v
(catena di riporto CCU2C del comparatore/accumulatore) e la sua
interconnessione — mai il controller PSRAM.