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  • v22-final ff5908f25f
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    v22 final: ECP5 architecture, weight-reuse verified, project paused (DEC-0009)

    michele released this 2026-09-16 15:25:30 +00:00 | -12 commits to main since this release

    Frozen as the definitive ECP5-based version. Real, verified, bit-exact
    results: N=16 core parallel neural accelerator, weight-stationary
    layer-reuse (EXP-0057/0058), 9.5-14x measured/estimated speedup vs
    ESP32-S3/Cortex-A7. Paused because the ECP5 family's fixed DSP block
    count (72 on 45F, 156 on 85F) makes the required 100-1000x speedup
    target physically unreachable on this chip family (DEC-0009).

    Follow-up work (if any) targets Xilinx Artix-7 (more DSP48 headroom,
    native INT8 packing, onboard DDR3) on a separate branch -- this tag
    marks the point v22 itself is considered complete.

    Co-Authored-By: Claude Sonnet 5 noreply@anthropic.com
    Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

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