Three chapters (docs/latex/), sourced from the real project docs
(BOM.md, PHYSICAL_REALIZATION.md, ARCHITECTURE_ANALYSIS.md,
experiments.log) -- no invented numbers:
- hardware.tex: board components, DDR3/FPGA/flash/ESP32, real pinout,
SPI protocol, boot procedure.
- architecture.tex: packed INT8 MAC core, N=8 hybrid systolic
architecture (shared-weight broadcast), hierarchical arbiter,
result writeback, why N=8 is the DDR3-bandwidth-bound sweet spot.
- tests_timing.tex: verification methodology, real functional test
results table, full real P&R signoff history (N=2 through N=16),
the definitive N=8 signoff (WNS=0.000ns), and an honestly-caveated
ESP32-S3 comparison (real historical ECP5 measurement vs. the
superseded, never-verified Artix-7 projection).
main.tex ties the three together as report chapters.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
