52 Commits

Include renames

Author	SHA1	Message	Date
micheleandClaude Sonnet 5	3026dcd997	feat(v2): M2 Neural Processor Array, N_PROCESSORS resource sweep ... Implements M2 of the V2 roadmap: neural_processor_array.v instantiates N_PROCESSORS independent neural_processor (M1) units, each with its own dedicated point-to-point job/operand/result interface -- no shared bus or mux at this level (arbitration is explicitly the Neural Director's job, M5). Verified with Verilator (tb_neural_processor_array.v, N_PROCESSORS=4): 7/7 tests pass, including a same-cycle 4-way concurrent launch with different tile counts and a staggered-start test where a later-launched, shorter job completes before an earlier-launched, longer one -- confirming genuine independent concurrent execution (§18/§34: a blocked/busy processor must not block the others). Real resource/timing sweep for N_PROCESSORS in {1,2,4,8} (Yosys + nextpnr-ecp5, real place&route): Fmax stays above the 80MHz target throughout (159.11 -> 134.70 MHz), but MULT18X18D usage scales linearly and reaches 88% of the LFE5U-45F's 72 DSPs at N=8 while LUT/FF stay under 6% -- DSP, not LUT/FF/routing, is the first hard ceiling on N_PROCESSORS at P_IN=8 (decisions.log DEC-0005). Measured via a dedicated synthesis-only timing harness after the array's wide per-processor buses were found to exhaust the device's TRELLIS_IO pin budget as a bare top-level module beyond N=1 (errors.log ERR-0005) -- not a logic limit, an artifact of testing the array in isolation before the Memory Manager/Director (M4/M5) exist to consume those ports on-chip. Full log trail (development/experiments/errors/decisions/simulation/ synthesis/timing/benchmark.log) in hardware/v2/logs/ per the project's logging mandate. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v	2026-09-05 14:15:11 +02:00
micheleandClaude Sonnet 5	dc0b331d3e	feat(v2): scaffold hardware/v1 frozen baseline + M1 Neural Processor ... Begins the V2 Neural Multiprocessor / Dataflow architecture per docs/v2-description.md, per explicit user request to freeze V1 and start V2 development, copying from V1 what's needed. Scaffold: - hardware/v1/: byte-exact, read-only copy of the current V1 codebase (rtl, testbenches, tools, constraints, a representative subset of synthesis results, and reference docs) -- verified identical via diff/cmp against the live top-level tree before being made filesystem-read-only. The live top-level tree is untouched and remains the project's "production" V1 (see hardware/v1/README.md and hardware/v2/logs/decisions.log DEC-0001 for why copy-not-move). - hardware/v2/: mandatory structure (rtl/sim/constraints/synthesis/ reports/scripts/logs/docs) plus the full logging system required by the spec (development/architecture/simulation/synthesis/timing/ benchmark/decisions/experiments/errors.log). M1 -- Neural Processor (hardware/v2/rtl/neural_processor.v): - 8-stage pipelined perceptron unit (P_IN=8): input align, 8 multipliers, 3-level adder tree, accumulator, bias+activation, INT8 saturation. Genuine 1-tile/cycle throughput, not just a wider combinational datapath. - 7-state FSM (NP_IDLE..NP_ERROR per docs/v2-description.md §6, with 4 baseline states merged into NP_WAIT_OPERANDS -- see decisions.log DEC-0002); valid/ready/data/last stream interfaces per §7. - Bit-exact vs the frozen hardware/v1/rtl/neuron_parallel.v + mac8.v + mac_unit.v: 7/7 tests pass (hardware/v2/sim/tb_neural_processor.v), covering regular/mixed-sign/extreme-INT8 vectors, both activations, a zero-idle-gap back-to-back-tiles throughput check, and an 8-tile job -- verified with Verilator (see below for why). - Real synthesis + place&route (Yosys + nextpnr-ecp5): 0 CHECK problems, Fmax 183.12 MHz at ACC_WIDTH=32 (PASS at 80MHz, ~3x V1's isolated PARALLEL=8 Fmax of 61.71 MHz) and 176.21 MHz at ACC_WIDTH=24 (a user-requested comparison experiment, also bit-exact-verified; see experiments.log EXP-0001/EXP-0002 and benchmark.log). Three real bugs found and resolved during M1 development (full diagnostic record in errors.log): - Two independent, reproducible Icarus Verilog v13.0 scheduling defects (ERR-0001, ERR-0002) that silently produced wrong simulation results for standard sequential Verilog -- confirmed via Verilator 5.050 giving correct results on the same minimal repros. Verilator is now the trusted simulator for hardware/v2/ (decisions.log DEC-0004); Icarus's affected protocol-violation check was removed from the RTL and deferred architecturally to the Neural Director (DEC-0003) rather than chased further. - One real RTL bug (ERR-0003): last0 wasn't gated like valid0, letting a "last tile" tag leak into the pipeline ahead of its actual valid tile on back-to-back jobs. Fixed and verified. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v	2026-09-05 14:06:53 +02:00