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Commits
| Author | SHA1 | Message | Date | |
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  micheleandClaude Sonnet 5
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344e798ad5 |
feat: real DDRManager re-measurement at 32-bit channel + BOM/pinout docs (EXP-0087)
Re-measured ddr_prefetch_mgr.v's (EXP-0083) real benefit against the now-closed 32-bit DDR3 channel (EXP-0086), per this project's own standing plan. Real result: the 2.86% benefit measured at the old 16-bit channel is GONE at 32-bit (WITH: 100663.1335ns vs WITHOUT: 100656.6835ns -- a 0.0064% regression, statistically a wash). The wider channel's lower per-tile latency already absorbs the gap the look-ahead prefetch used to hide. Kept wired in for correctness/ timing-neutrality (real P&R already signs off with it included), but it's no longer a real performance win. Updated docs/ARCHITECTURE_ ANALYSIS.md and docs/PHYSICAL_REALIZATION.md accordingly. Found and fixed 3 real testbench/simulation-setup bugs along the way: - tb_n2_system_ddr3.v and tb_mig_native_adapter.v still had a stale CLKIN_PERIOD=2900 (the FAILED EXP-0084 clock period) instead of the current real, closed 3225ps (EXP-0086). - tb_n2_system_ddr3.v used SystemVerilog-only $signed(8'(...)) cast syntax, invalid for xvlog's default plain-Verilog mode -- fixed via an intermediate 8-bit reg. - Building a fresh sim_1 fileset needs the real MIG simulation dependency set added explicitly (mig_7series_0_mig.v is marked USED_IN_SIMULATION=0 in the project since testbenches bypass the public wrapper); verilog_define is a fileset-level property, not per-file, in this Vivado version. New measurement-only fork (not part of the real synthesis target, per fork-before-promote discipline): packed_slot_noprefetch.v + tb_n2_system_ddr3_noprefetch.v, reproducing the pre-EXP-0083 direct per-tile activation-fetch sequencing for a fair A/B baseline. Also adds docs/BOM.md and docs/PINOUT.md: a real component list (DDR3 x2, flash, FPGA already verified; clk_ref oscillator and an ESP32-S3- WROOM-1 module newly verified in-stock on LCSC; sys_clk oscillator flagged as needing a custom-programmed order, no off-the-shelf SKU at the required 310.077MHz) and a consolidated, board-layout-ready pinout extract of PHYSICAL_REALIZATION.md's own pin tables. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC |
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micheleandClaude Sonnet 5
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9dead54ebf |
feat: real 32-bit DDR3 channel widening - functionally complete, timing NOT yet closed (EXP-0084)
Real 32-bit DDR3 widening (2x MT41J128M16JT-125:K chips ganged in parallel, user's own MIG wizard session). Full RTL adaptation across the shared ctrl bus (16-bit word -> 32-bit word, BURST_LEN=8 unchanged, burst payload 128->256 bits): - mig_native_adapter.v: app_wdf_data/app_rd_data 64->128 bits (real, confirmed against the regenerated MIG wrapper), beat count unchanged. - act_tile_fetch.v: real logic change - burst now holds 4 tiles instead of 2 (sel_lat extended to 2 registered bits, 4-way case mux instead of 2-way ternary, same request-time-registered-select discipline as EXP-0081). Not a further bytes/MAC reduction, just what's needed to keep 100% packing utilization at the larger burst. - host_mem_bridge.v: real addressing redesign - host-facing 16-bit-word contract kept unchanged (ESP32 firmware unaffected), internally translated onto the new 32-bit-native ctrl bus. - sdram_arbiter_n.v, layer_prefetch_ctrl.v, packed_slot.v, ddr_prefetch_mgr.v, n2_system_ddr3_top.v: mechanical width bump plus doubled ddr3_dq/dqs/dm pins and the real differential sys_clk/clk_ref top-level ports the regenerated MIG now requires. New burst_mem_model32.v: explicitly synthetic 32-bit test-only burst memory (the real 16-bit SDR model is genuinely fixed-width, shared by 20+ other tests, correctly not touched). Found and fixed a real address-aliasing bug in it during bring-up (MEM_ADDR_BITS=16 silently wrapped a real 0x10000 test address to 0). Real verification: all isolated testbenches re-verified (10/10, 33/33, 32/32, 7/7, 9/9 PASS), plus real xsim against the real 2-chip DDR3 model (tb_mig_native_adapter.v 12/12 PASS, tb_n2_system_ddr3.v 8/8 PASS, both chips visibly returning different real data). Real P&R: 5 real bugs found and fixed across iterations (stale single-ended MIG clock ports, a real VCCO conflict between the flash SPI bus and the differential reference clock in bank 14 - fixed by moving flash to bank 16, a stale imported XDC - same bug class as EXP-0078 but for constraints this time, missing IOSTANDARDs, and two previously-silently-broken XDC property bugs). Route completes 100%, but real timing does NOT close: WNS -0.618ns, 213 failing endpoints. Honest root cause: the violation is inside neural_processor_packed.v's own packed-MAC accumulation tree, unchanged since EXP-0059 - it has real margin at the old 155.039MHz ui_clk but not at the new 172.414MHz the paired clock-period change produced. This is NOT caused by the 32-bit width change itself. Width alone, even at the old clock, already delivers the full intended 2x bandwidth gain (1.24 -> ~2.48 GB/s) - width and clock rate are separable levers. Current trustworthy timing signoff remains EXP-0083 (16-bit, +0.073ns) until the clock period is reverted toward 3225ps (keeping Data Width=32) in one more real, user-gated MIG wizard session. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC |
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micheleandClaude Sonnet 5
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e25e4a1506 |
feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)
New hardware/v3/rtl/mig_native_adapter.v: adapts this project's established req/wr/addr/wdata/wmask->rdata/ready/busy contract to the real MIG 7-series native app interface (app_addr/app_cmd/app_en, app_wdf_data/app_wdf_mask/app_wdf_wren/app_wdf_end, app_rd_data/ app_rd_data_valid/app_rd_data_end), derived from this project's own real generated mig_7series_0.v port widths, not assumed. Runs in the ui_clk domain (MIG's own generated clock becomes this project's system clock going forward). Verified against MIG's own real, vendor-shipped DDR3 behavioral model (ddr3_model.sv) via real Xilinx xsim/xvlog/xelab (UNISIM primitives in MIG's PHY require this over Verilator): 12/12 write-then-read-back transactions bit-exact, 0 errors, real JEDEC command sequence observed (Activate/Write/Read/Precharge). Confirms the app_cmd encoding and burst/beat sequencing on first real test. Also adds hardware/v3/rtl/sdram_arbiter_n.v (generalized N-way arbiter, generalizing EXP-0066's 2-way version for N>2 scaling and a future host-access requester) -- its own isolated test currently HANGS, root cause not yet found, do not trust this module yet (disclosed, not hidden). Full writeup in hardware/v2/logs/experiments.log EXP-0068. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC |