architecture.tex: document the real MAC-pipeline fix (Stage 1a/1b
split) and its real result on both N8 (WNS 0.000ns -> +0.108ns) and
N16 (now closed, WNS=+0.269ns) -- N16 is a real, verified candidate
for a future board revision, N8 remains the configuration in current
physical fabrication.
tests_timing.tex: extended P&R history table, real N8/N16 signoff
tables (post-fix), the new N16 critical path (Director queue logic,
still route-dominated) and the negative result of a second directive
attempt (confirms current result is the best found). Added a new,
clearly-labeled PROJECTION (not a measurement) for N16 vs ESP32-S3 --
30-68x range, built from real measured scaling factors (same core
count as the original ECP5 comparison, real clock ratio, real 2x INT8
packing factor) -- more grounded than the old, superseded ~55-85x
figure, with the same DDR3-bandwidth-bound honest caveat carried
forward.
datasheet.tex: N8/N16 side-by-side timing/utilization/performance
tables, open items and revision history updated to reflect physical
fabrication status and the N16 candidate decision.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Standalone LaTeX document (docs/latex/datasheet.tex), styled like an
ordinary component/module datasheet (features block, ordering info,
block diagram, absolute maximum ratings, recommended operating
conditions, pin configuration, timing/resource/performance tables,
protocol summary, verification status, BOM, open items, revision
history).
Marked PRELIMINARY throughout -- the board has not been physically
fabricated yet, so electrical/thermal ratings not directly measured by
this project defer to the underlying component datasheets (Xilinx
DS181, Micron DDR3, Winbond W25Q32JV) rather than being invented.
Every timing/resource/verification number is real, sourced from actual
P&R and simulation results, matching the rest of the project's own
"real numbers only" discipline.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
Three chapters (docs/latex/), sourced from the real project docs
(BOM.md, PHYSICAL_REALIZATION.md, ARCHITECTURE_ANALYSIS.md,
experiments.log) -- no invented numbers:
- hardware.tex: board components, DDR3/FPGA/flash/ESP32, real pinout,
SPI protocol, boot procedure.
- architecture.tex: packed INT8 MAC core, N=8 hybrid systolic
architecture (shared-weight broadcast), hierarchical arbiter,
result writeback, why N=8 is the DDR3-bandwidth-bound sweet spot.
- tests_timing.tex: verification methodology, real functional test
results table, full real P&R signoff history (N=2 through N=16),
the definitive N=8 signoff (WNS=0.000ns), and an honestly-caveated
ESP32-S3 comparison (real historical ECP5 measurement vs. the
superseded, never-verified Artix-7 projection).
main.tex ties the three together as report chapters.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
micheleandClaude Sonnet 5